Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/763—Polycrystalline semiconductor regions

Definitions

• the present invention relates to trenches in semiconductor products having a substantially planar surface.
• the polysiiicon is also deposited on the oxide layer on the planar surfaces of the silicon substrate between the trenches.
• This polysiiicon is then etched away in order to expose the oxide layer on the planar surface.
• Some of the polysiiicon over the trench is also removed by this etching. This leaves components in the form of an island of silicon surrounded by a trench of isolating polysiiicon.
• each successive layer of the integrated circuit is built upon a substantially planar surface.
• the removal of some of the polysiiicon over the trench leaves a downward vertical step.
• the oxide walls of the trenches usually have sloping tops which incline downwardly towards the inside of the trench.
• the thickness of the polysiiicon in the substantially planar polysiiicon filling in the trench decreases as it approaches the trench walls.
• the polysiiicon is then oxidised to form an isolating oxide cover over the trench.
• This oxidisation it is possible that the silicon substrate in the regions near the trench edges which have only a thin covering of polysiiicon is also oxidised. This produces high mechanical stresses in these regions.
• Subsequent processing often uses wet etching to remove thermally produced oxides. The etching speed for wet etching for oxides is greatly dependent on the mechanical stress in the oxides.
• An object of the present invention is to produce trenches surfaces which are more planar than previous trench surfaces. Another object of the invention is to provide a method for eliminating the problem of strings of surplus conducting material remaining in grooves along trench edges.
• this object is accomplished by providing extra amounts of trench material along the edges of the trenches in order to prevent the occurrence of grooves along the trench edges.
• this is done by depositing on to the trench filling material a layer of polysiiicon, oxide, nitride or the like which is then etched back by an anisotropic etch i.e. an etching process which attacks the layer to be etched significantly faster in the vertical direction than in the horizontal. This leaves extra material along the trench edges. This process can take place before or after the oxide layer is grown on the polysiiicon in the trench.
• the thickness of the extra material after etching should be approximately the same as the height of the downward vertical step.
• the thickness of the polysiiicon deposited is preferably chosen such that when all of the extra polysiiicon is oxidised during the subsequent oxidation the resulting oxide layer has approximately the same height as the step height.
• the extra material in the form of oxide, nitride or polysiiicon strings along the trench edges protect from oxidation the underlying silicon which otherwise would be oxidised and produce regions of high mechanical stress. In the absence of regions of high mechanical stress the subsequent wet etching proceeds more evenly and the production of unwanted grooves at the trench edges is avoided.
• the oxidation of the extra thickness of the polysiiicon material near to the trench edges also provides a thicker oxide layer near to the trench walls.
• oxides layers at the trench edges which are substantially the same thickness as the surrounding oxide layers and in this way achieve a more planar surface.
• deposition temperature it is possible to adjust the grain size of deposited silicon i.e. deposition at 580°C produces amorphous silicon while deposition at 600°C produces micro-crystalline silicon and deposition at 620°C gives polycrystalline silicon.
• Amorphous silicon oxidises more quickly than micro- crystalline silicon which oxidises more quickly than polycrystalline silicon. It is therefore possible to adjust the relative oxidation rates of the trench material and the extra material to form a desired trench cross-sectional profile by adjusting the deposition temperature of the extra material.
• a trench formation formed in accordance with the invention has a number of advantages.
• An obvious advantage is that the surface over the trench no longer has a vertical step which reduces the risk of undesirable material being trapped in the trench and later causing problems.
• An other advantage is that a more even planar surface is achieved after the oxide or nitride has been deposited or after the polysiiicon has been deposited and etched back in a method according to the invention.
• a further advantage is that the mechanical stresses in the trench are reduced.
• Figures la-lh shows in cross-section stages in the formation of a trench according to a prior art method; and, figures 2a-2i shows in cross-section stages in the formation of a trench according to one embodiment of the present invention.
• Figure la shows the first stage in a known method of producing a trench.
• a trench 1 has been etched into a silicon substrate 2 of a wafer which has a planar surface 3.
• An isolation layer 4 of, for example silicon dioxide or silicon nitride or a combination of these, on top of the planar surface acts as a mask during etching of the trench 1.
• a polysiiicon layer 6 has been deposited over substantially the whole of the silicon substrate 2 and in the trench 1 to a thickness which is sufficient to overfill the trench 1.
• a dip or vertically downward step 8' is present over the trench 1.
• the polysiiicon layer 6 has been etched away in order to expose the second insulating layer 9 on the substantially planar surface of the silicon substrate 2.
• This second insulating layer 6 is resistant to the etching. This leaves islands of silicon substrate 2 separated by a trench 1 with walls 9 of isolating oxide and a core of polysiiicon 6. When the polysiiicon 6 is etched away from the wafer surface to expose the second insulating layer 6 a downward vertical step 8 remains over the trench 1. This is caused by over-etching of the polysiiicon layer 6. This over-etching is required to ensure that all the polysiiicon on top of the planar surface 3 is removed.
• the surface of the polysiiicon 6 remaining in the trench 1 is then oxidised to form an isolating oxide cover 10 over the trench as shown in figure le.
• the silicon substrate 2 in the regions 12 where the oxide walls of the trenches 1 have sloping tops which incline downwardly towards the inside of the trench has only a thin covering of polysiiicon 6.
• the silicon substrate 2 is also oxidised, especially in the region where the cover oxide is thin prior to the oxidation step. This produces high mechanical stresses in regions 12 and in the oxide 9, 10 near these regions.
• isolation layer 9 on the planar surface 3 is thinned or even removed entirely.
• isolation layer 4 is still present it is also conceivable that it is also, at least, partially thinned.
• the etching speed for wet etching for oxides is greatly dependent on the mechanical stress in the oxides. This means that the oxides in regions 12 of high mechanical stress are etched deeper than the rest of the surface. As shown in figure If this can leads to irregular grooves 14 along the edges of the trench 1.
• these grooves 14 become filled with conducting material 16 as shown in figure lg.
• the duration of later processing to remove unwanted conducting material 16 may be insufficient to remove all the conducting material 16 at the bottom of the grooves 14 and strings 18 of surplus conducting material 16 may be left in the grooves as shown in figure lh.
• These strings 18 can cause problems such as short circuits particularly if the strings are so high that they contact conductors laid over the trench during subsequent processing.
• a trench is etched in the substrate in a conventional manner, for example, as described above with respect to Figures la- I d.
• the invention is illustrated by embodiments using a silicon substrate, silicon oxides as insulating material and polysiiicon as a filling material. It is also conceivable to use other semiconductors e.g. silicon carbide or other group 3 or group 5 materials, or other suitable materials for the substrate and the insulating materials can be any suitable compounds such as oxides, nitrides or the like, and combinations thereof.
• trench filling material is not limited to polysiiicon but could be, for example, amorphous silicon, micro- crystalline silicon or crystalline silicon compounds.
• the trench structure is formed in a substrate based on a material other than silicon is used then it is naturally possible to use other filling materials with the appropriate properties.
• Film 21 is then etched back a distance t with an anisotropic etch which etches primarily in the vertical direction. This exposes the oxide layer 4 and/or 9 on the planar surface and the polysiiicon in the centre of the trench but leaves extra seams of polysiiicon 20 along the trench edges where the vertical thickness of film 21 is greatest.
• the thickness t of film 21 and the duration of the anisotropic etch is calculated to give a thickness d for the extra seams 20 such that after oxidation of the polysiiicon in the seams 20, the resulting oxide layer has a thickness substantially equal to that of insulating oxide covering the silicon surface 3.
• the topography of the polysiiicon 6, 20 is now such that there are no regions having only a thin covering of polysiiicon.
• the wafer is then oxidised in the conventional manner in order to form an isolating oxide cover 22 over the trench 1 from the exposed polysiiicon 6. 20, as shown in Figure 2f.
• the silicon substrate in region 12 is not oxidised and regions of high mechanical stress do not occur.
• the more uniform thickness of the polysiiicon layer before oxidising leads to a more uniform oxide layer.
• By varying the shape and dimensions of the extra seams of polysiiicon 20 it is possible to produce an oxide layer which is substantially flat and coplanar with the exposed surface of the surrounding substrate.
• deposition temperature it is possible to adjust the grain size of deposited silicon i.e. deposition at 580°C produces amorphous silicon while deposition at 600°C produces micro-crystalline silicon and deposition at 620°C gives polycrystalline silicon.
• Amorphous silicon oxidises more quickly than micro- crystalline silicon which oxidises more quickly than polycrystalline silicon. It is therefore possible to adjust the relative oxidation rates of the trench material and the extra material to form a desired trench cross-sectional profile by adjusting the deposition temperature of the extra material.
• any subsequent filling of conducting material 16 has a more even depth and removal of conducting material 16 can be performed without leaving strings of unwanted conducting material.
• trenches are formed using the processes described above with reference to Figures 2a-2d.
• the polysiiicon 6 in the trench is then oxidised to form a layer of silicon oxide before the extra seams 20 of material are laid along the edges of the trenches.
• This layer of silicon oxide acts as a stop layer with respect to further processing and prevents the underlying polysiiicon 6 in the trench from being etched or oxidised in the following processing stages.
• the polysiiicon is preferably oxidised at a comparatively low temperature in the region of 800 °C to 900 °C.
• a further layer of oxide is deposited over the entire wafer, including the trench walls, after the steps of filling the trench with polysiiicon and subsequent etching back of the polysiiicon have been performed.
• the depth of this further layer is dependent on the height of the vertical step of the trench and the required height of the seams as described later.
• This oxide layer is then etched back to the earlier oxide layer with an anisotropic etch which etches primarily in the vertical direction thus leaving, as in the embodiment above, extra seams of material along the trench edges.
• the thickness of the extra seams (and thus the thickness of the deposited oxide layer) is chosen such that the remaining oxide layer along the trench edges has a thickness (height) substantially equal to that of the original insulating oxide layer and that the trench walls are displaced towards each other an amount sufficient to cover any regions of the trench edges which have a thin covering of polysiiicon. If the thickness of each of the extra seams is greater than half the maximum trench width then the trench will be completely filled by these seams. After anisotropic etching-back a trench surface substantially coplanar with the surrounding exposed planar surface will be produced. These extra seams of oxide will not be oxidised during subsequent processing of the wafer and therefore will prevent high mechanical stresses arising near the trench edges.
• a further layer of nitride is substituted for the further layer of oxide mentioned in the third embodiment of the invention.
• this nitride layer is deposited over the wafer and subsequently etched back.
• the isolating layers can be made from any suitable insulating material including such materials such as oxides, nitrides or the like of the substrate material.
• the methods according to the invention are preferably performed after active components have been created on the substrate and after they have been protected from etching and oxidation by coverings of etch-resistant and oxidation-resistant material.

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
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• Drying Of Semiconductors (AREA)

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Citations (5)

• 1997
  • 1997-03-26 SE SE9701154A patent/SE520115C2/sv not_active IP Right Cessation
  • 1997-04-18 TW TW086105057A patent/TW356579B/zh active
• 1998
  • 1998-03-23 CA CA002285627A patent/CA2285627A1/en not_active Abandoned
  • 1998-03-23 EP EP98912851A patent/EP1018156A1/en not_active Withdrawn
  • 1998-03-23 AU AU67539/98A patent/AU6753998A/en not_active Abandoned
  • 1998-03-23 KR KR10-1999-7008655A patent/KR100374455B1/ko not_active IP Right Cessation
  • 1998-03-23 WO PCT/SE1998/000528 patent/WO1998043293A1/en active IP Right Grant
  • 1998-03-23 JP JP54556198A patent/JP2001519097A/ja not_active Abandoned
  • 1998-03-23 CN CN98805442A patent/CN1110848C/zh not_active Expired - Fee Related

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