CA2131668C - Isolation structure using liquid phase oxide deposition - Google Patents

Isolation structure using liquid phase oxide deposition

Info

Publication number
CA2131668C
CA2131668C CA002131668A CA2131668A CA2131668C CA 2131668 C CA2131668 C CA 2131668C CA 002131668 A CA002131668 A CA 002131668A CA 2131668 A CA2131668 A CA 2131668A CA 2131668 C CA2131668 C CA 2131668C
Authority
CA
Canada
Prior art keywords
trench
oxide
recited
resist
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002131668A
Other languages
English (en)
French (fr)
Other versions
CA2131668A1 (en
Inventor
Carol Galli
Louis L. Hsu
Seiki Ogura
Joseph F. Shepard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2131668A1 publication Critical patent/CA2131668A1/en
Application granted granted Critical
Publication of CA2131668C publication Critical patent/CA2131668C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CA002131668A 1993-12-23 1994-09-08 Isolation structure using liquid phase oxide deposition Expired - Fee Related CA2131668C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US173,396 1988-03-25
US17339693A 1993-12-23 1993-12-23

Publications (2)

Publication Number Publication Date
CA2131668A1 CA2131668A1 (en) 1995-06-24
CA2131668C true CA2131668C (en) 1999-03-02

Family

ID=22631817

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002131668A Expired - Fee Related CA2131668C (en) 1993-12-23 1994-09-08 Isolation structure using liquid phase oxide deposition

Country Status (7)

Country Link
US (1) US5516721A (en:Method)
EP (1) EP0660390A3 (en:Method)
JP (1) JP2804446B2 (en:Method)
KR (1) KR0167813B1 (en:Method)
BR (1) BR9405158A (en:Method)
CA (1) CA2131668C (en:Method)
TW (1) TW265457B (en:Method)

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516720A (en) * 1994-02-14 1996-05-14 United Microelectronics Corporation Stress relaxation in dielectric before metallization
KR0134108B1 (ko) * 1994-06-30 1998-04-20 김주용 반도체 소자의 제조방법
US5530293A (en) 1994-11-28 1996-06-25 International Business Machines Corporation Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits
US5770501A (en) * 1995-12-22 1998-06-23 United Microelectronics Corporation Process of fabricating NAND-structure flash EEPROM using liquid phase deposition
US6322634B1 (en) 1997-01-27 2001-11-27 Micron Technology, Inc. Shallow trench isolation structure without corner exposure
TW337592B (en) * 1997-04-03 1998-08-01 Nat Science Council Process of depositing silicon dioxide on a group III-V semiconductor substrate by ammoniation treatment
US5972570A (en) * 1997-07-17 1999-10-26 International Business Machines Corporation Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby
US6013558A (en) * 1997-08-06 2000-01-11 Vlsi Technology, Inc. Silicon-enriched shallow trench oxide for reduced recess during LDD spacer etch
US6455394B1 (en) * 1998-03-13 2002-09-24 Micron Technology, Inc. Method for trench isolation by selective deposition of low temperature oxide films
US6150072A (en) * 1997-08-22 2000-11-21 Siemens Microelectronics, Inc. Method of manufacturing a shallow trench isolation structure for a semiconductor device
US7157385B2 (en) 2003-09-05 2007-01-02 Micron Technology, Inc. Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
US6087243A (en) * 1997-10-21 2000-07-11 Advanced Micro Devices, Inc. Method of forming trench isolation with high integrity, ultra thin gate oxide
US5952707A (en) * 1997-12-05 1999-09-14 Stmicroelectronics, Inc. Shallow trench isolation with thin nitride as gate dielectric
US6211002B1 (en) * 1998-01-28 2001-04-03 Texas Instruments-Acer Incorporated CMOS process for forming planarized twin wells
DE69835276T2 (de) * 1998-05-22 2007-07-12 Applied Materials, Inc., Santa Clara Verfahren zur Herstellung einer selbst-planarisierten dielektrischen Schicht für eine seichte Grabenisolation
KR100283469B1 (ko) * 1998-06-08 2001-04-02 윤종용 반도체소자제조방법
TW460604B (en) * 1998-10-13 2001-10-21 Winbond Electronics Corp A one-sided and mass production method of liquid phase deposition
US6239002B1 (en) * 1998-10-19 2001-05-29 Taiwan Semiconductor Manufacturing Company Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer
US6120607A (en) * 1998-12-03 2000-09-19 Lsi Logic Corporation Apparatus and method for blocking the deposition of oxide on a wafer
US6140208A (en) * 1999-02-05 2000-10-31 International Business Machines Corporation Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications
JP3439388B2 (ja) * 1999-07-27 2003-08-25 日本電気株式会社 半導体装置の製造方法
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6271100B1 (en) 2000-02-24 2001-08-07 International Business Machines Corporation Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
US6348394B1 (en) 2000-05-18 2002-02-19 International Business Machines Corporation Method and device for array threshold voltage control by trapped charge in trench isolation
FR2828332A1 (fr) * 2000-06-23 2003-02-07 Gemplus Card Int Procede d'isolation electrique de puces comportant des circuits integres par le depot d'une couche isolante
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
US6613641B1 (en) * 2001-01-17 2003-09-02 International Business Machines Corporation Production of metal insulator metal (MIM) structures using anodizing process
US6605506B2 (en) * 2001-01-29 2003-08-12 Silicon-Based Technology Corp. Method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays
WO2002101818A2 (en) * 2001-06-08 2002-12-19 Amberwave Systems Corporation Method for isolating semiconductor devices
WO2003025984A2 (en) * 2001-09-21 2003-03-27 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US7060633B2 (en) * 2002-03-29 2006-06-13 Texas Instruments Incorporated Planarization for integrated circuits
KR100864845B1 (ko) * 2002-07-03 2008-10-23 매그나칩 반도체 유한회사 반도체소자의 소자분리막 제조방법
US6593221B1 (en) * 2002-08-13 2003-07-15 Micron Technology, Inc. Selective passivation of exposed silicon
EP1602125B1 (en) 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation process
US6767786B1 (en) * 2003-04-14 2004-07-27 Nanya Technology Corporation Method for forming bottle trenches by liquid phase oxide deposition
TWI222180B (en) * 2003-04-29 2004-10-11 Nanya Technology Corp Method for forming vertical transistor and trench capacitor
US7125815B2 (en) * 2003-07-07 2006-10-24 Micron Technology, Inc. Methods of forming a phosphorous doped silicon dioxide comprising layer
US7273794B2 (en) * 2003-12-11 2007-09-25 International Business Machines Corporation Shallow trench isolation fill by liquid phase deposition of SiO2
US7053010B2 (en) * 2004-03-22 2006-05-30 Micron Technology, Inc. Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells
US7074690B1 (en) * 2004-03-25 2006-07-11 Novellus Systems, Inc. Selective gap-fill process
US7582555B1 (en) 2005-12-29 2009-09-01 Novellus Systems, Inc. CVD flowable gap fill
US7524735B1 (en) 2004-03-25 2009-04-28 Novellus Systems, Inc Flowable film dielectric gap fill process
US9257302B1 (en) 2004-03-25 2016-02-09 Novellus Systems, Inc. CVD flowable gap fill
US7235459B2 (en) * 2004-08-31 2007-06-26 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry
US7087531B1 (en) * 2005-01-17 2006-08-08 International Business Machines Corporation Shallow trench isolation formation
US7510966B2 (en) * 2005-03-07 2009-03-31 Micron Technology, Inc. Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines
US8012847B2 (en) 2005-04-01 2011-09-06 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
US7482215B2 (en) 2006-08-30 2009-01-27 International Business Machines Corporation Self-aligned dual segment liner and method of manufacturing the same
US7888273B1 (en) 2006-11-01 2011-02-15 Novellus Systems, Inc. Density gradient-free gap fill
US9245739B2 (en) 2006-11-01 2016-01-26 Lam Research Corporation Low-K oxide deposition by hydrolysis and condensation
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US20090072355A1 (en) * 2007-09-17 2009-03-19 International Business Machines Corporation Dual shallow trench isolation structure
CN101452873B (zh) * 2007-12-06 2010-08-11 上海华虹Nec电子有限公司 浅沟槽隔离工艺方法
US8557712B1 (en) 2008-12-15 2013-10-15 Novellus Systems, Inc. PECVD flowable dielectric gap fill
US8278224B1 (en) 2009-09-24 2012-10-02 Novellus Systems, Inc. Flowable oxide deposition using rapid delivery of process gases
US8105956B2 (en) * 2009-10-20 2012-01-31 Micron Technology, Inc. Methods of forming silicon oxides and methods of forming interlevel dielectrics
KR101758944B1 (ko) 2009-12-09 2017-07-18 노벨러스 시스템즈, 인코포레이티드 신규한 갭 충진 집적화
US8685867B1 (en) 2010-12-09 2014-04-01 Novellus Systems, Inc. Premetal dielectric integration process
US9719169B2 (en) 2010-12-20 2017-08-01 Novellus Systems, Inc. System and apparatus for flowable deposition in semiconductor fabrication
US8846536B2 (en) 2012-03-05 2014-09-30 Novellus Systems, Inc. Flowable oxide film with tunable wet etch rate
CN103632961B (zh) * 2012-08-20 2016-08-10 上海华虹宏力半导体制造有限公司 功率mosfet芯片保护结构制造方法
US9847222B2 (en) 2013-10-25 2017-12-19 Lam Research Corporation Treatment for flowable dielectric deposition on substrate surfaces
US10049921B2 (en) 2014-08-20 2018-08-14 Lam Research Corporation Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor
US9916977B2 (en) 2015-11-16 2018-03-13 Lam Research Corporation Low k dielectric deposition via UV driven photopolymerization
US10388546B2 (en) 2015-11-16 2019-08-20 Lam Research Corporation Apparatus for UV flowable dielectric
JP6573575B2 (ja) * 2016-05-02 2019-09-11 東京エレクトロン株式会社 凹部の埋め込み方法
FR3067854B1 (fr) * 2017-06-16 2019-08-02 Universite De Tours Francois Rabelais Realisation par voie liquide de revetements conformes de materiaux oxydes sur des substrats micro- ou macro-structures
WO2020214732A1 (en) 2019-04-19 2020-10-22 Lam Research Corporation Rapid flush purging during atomic layer deposition
CN112366205B (zh) * 2020-11-09 2021-10-22 长江存储科技有限责任公司 一种半导体器件及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4544576A (en) * 1981-07-27 1985-10-01 International Business Machines Corporation Deep dielectric isolation by fused glass
DE3332995A1 (de) * 1983-07-14 1985-01-24 Nippon Sheet Glass Co. Ltd., Osaka Verfahren zum herstellen einer siliciumdioxidbeschichtung
JPS61207029A (ja) * 1985-03-11 1986-09-13 Nec Corp 半導体集積回路装置
JPS61281047A (ja) * 1985-06-06 1986-12-11 Nippon Sheet Glass Co Ltd 二酸化珪素被膜の製造方法
JPH01143254A (ja) * 1987-11-28 1989-06-05 Mitsubishi Electric Corp 半導体記憶装置
US4851370A (en) * 1987-12-28 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Fabricating a semiconductor device with low defect density oxide
JPH01295438A (ja) * 1988-05-24 1989-11-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5270276A (en) * 1989-04-25 1993-12-14 Shell Oil Company Process for the production of elastomeric, primarily syndiotactic polypropylene and catalysts for use in said process
JPH04106954A (ja) * 1990-08-24 1992-04-08 Sony Corp 液相ｃｖｄ法を用いた半導体装置の製造方法
JPH04132240A (ja) * 1990-09-21 1992-05-06 Nippon Steel Corp 半導体装置の製造方法
JPH04245662A (ja) * 1991-01-31 1992-09-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5286664A (en) * 1991-10-01 1994-02-15 Nec Corporation Method for fabricating the LDD-MOSFET
JPH05102136A (ja) * 1991-10-03 1993-04-23 Toshiba Corp 半導体集積回路装置の製造方法
JPH05235157A (ja) * 1992-02-26 1993-09-10 Fujitsu Ltd 半導体装置の製造方法
JPH07122627A (ja) * 1993-10-22 1995-05-12 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH07201979A (ja) 1995-08-04
BR9405158A (pt) 1995-08-01
US5516721A (en) 1996-05-14
CA2131668A1 (en) 1995-06-24
EP0660390A2 (en) 1995-06-28
TW265457B (en:Method) 1995-12-11
JP2804446B2 (ja) 1998-09-24
EP0660390A3 (en) 1997-07-09
KR0167813B1 (ko) 1999-02-01
KR950021405A (ko) 1995-07-26

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