CA1252895A - Byte-wide encoder and decoder system for rll (1,7) code - Google Patents

Byte-wide encoder and decoder system for rll (1,7) code

Info

Publication number
CA1252895A
CA1252895A CA000506442A CA506442A CA1252895A CA 1252895 A CA1252895 A CA 1252895A CA 000506442 A CA000506442 A CA 000506442A CA 506442 A CA506442 A CA 506442A CA 1252895 A CA1252895 A CA 1252895A
Authority
CA
Canada
Prior art keywords
rll
sequence
symbol
byte
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000506442A
Other languages
English (en)
French (fr)
Inventor
Wilson W. Fok
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1252895A publication Critical patent/CA1252895A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • G06T9/005—Statistical coding, e.g. Huffman, run length coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Dc Digital Transmission (AREA)
CA000506442A 1985-06-13 1986-04-11 Byte-wide encoder and decoder system for rll (1,7) code Expired CA1252895A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/745,242 1985-06-13
US06/745,242 US4688016A (en) 1985-06-13 1985-06-13 Byte-wide encoder and decoder system for RLL (1,7) code

Publications (1)

Publication Number Publication Date
CA1252895A true CA1252895A (en) 1989-04-18

Family

ID=24995854

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000506442A Expired CA1252895A (en) 1985-06-13 1986-04-11 Byte-wide encoder and decoder system for rll (1,7) code

Country Status (5)

Country Link
US (1) US4688016A (enExample)
EP (1) EP0205009B1 (enExample)
JP (1) JPS61288624A (enExample)
CA (1) CA1252895A (enExample)
DE (1) DE3678206D1 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833470A (en) * 1986-07-15 1989-05-23 Matsushita Electric Industrial Co., Ltd. Code conversion apparatus
JPH061608B2 (ja) * 1986-12-08 1994-01-05 富士通株式会社 デ−タの変復調装置
US4914438A (en) * 1987-09-01 1990-04-03 Hitachi, Ltd. Digital information coding system
US4868690A (en) * 1987-11-05 1989-09-19 Magnetic Peripherals Inc. Self-initializing 1,7 code decoder with low sensitivity to errors in preamble
JPH01286626A (ja) * 1988-01-18 1989-11-17 Hitachi Ltd データ符号化方式
US4870414A (en) * 1988-03-18 1989-09-26 International Business Machines Corporation Even mark modulation coding method
US5737632A (en) * 1989-12-19 1998-04-07 Hitachi, Ltd. Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder/decoder circuit
US5047767A (en) * 1990-05-21 1991-09-10 Eastman Kodak Company Apparatus utilizing a four state encoder for encoding and decoding A sliding block (1,7) code
DE69024045T2 (de) * 1990-08-16 1996-06-20 Ibm Kodierungsverfahren und Vorrichtung zur Pipeline- und Parallelverarbeitung.
US5392168A (en) * 1990-08-31 1995-02-21 Matsushita Electric Industrial Co., Ltd. Method of recording digital video and audio data
US5231545A (en) * 1991-06-04 1993-07-27 Quantum Corporation Fault tolerant rll data sector address mark decoder
AU3274493A (en) * 1991-12-13 1993-07-19 Avid Technology, Inc. Buffer and frame indexing
US5946445A (en) * 1992-04-10 1999-08-31 Avid Technology, Inc. Media recorder for capture and playback of live and prerecorded audio and/or video information
US6678461B1 (en) 1992-04-10 2004-01-13 Avid Technology, Inc. Media recorder for capture and playback of live and prerecorded audio and/or video information
US5424881A (en) * 1993-02-01 1995-06-13 Cirrus Logic, Inc. Synchronous read channel
US7623754B1 (en) 1995-02-23 2009-11-24 Avid Technology, Inc. Motion picture recording device using digital, computer-readable non-linear media
US6977673B1 (en) 1995-02-23 2005-12-20 Avid Technology, Inc. Portable moving picture recording device including switching control for multiple data flow configurations
US5999406A (en) * 1995-02-23 1999-12-07 Avid Technology, Inc. Dockable electronic equipment container
US7532807B2 (en) * 1995-04-07 2009-05-12 Avid Technology, Inc. Combined editing system and digital moving picture recording system
US6775217B1 (en) * 2000-05-18 2004-08-10 Cirrus Logic, Inc. Multi-stage ring oscillator for providing stable delays on EFM data pulses for recording CD-R and CD-RW medium
US6763477B1 (en) 2000-07-31 2004-07-13 Hewlett-Packard Development Company, L.P. Method and apparatus for transmitting and receiving data using a self clocking link protocol
US6504493B1 (en) 2000-10-31 2003-01-07 Marvell International, Ltd. Method and apparatus for encoding/decoding data
US7502433B1 (en) 2004-08-17 2009-03-10 Xilinx, Inc. Bimodal source synchronous interface
US7091890B1 (en) * 2004-08-17 2006-08-15 Xilinx, Inc. Multi-purpose source synchronous interface circuitry
US7787526B2 (en) * 2005-07-12 2010-08-31 Mcgee James Ridenour Circuits and methods for a multi-differential embedded-clock channel

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3685033A (en) * 1970-08-24 1972-08-15 Honeywell Inc Block encoding for magnetic recording systems
US3852687A (en) * 1973-07-02 1974-12-03 Ibm High rate digital modulation/demodulation method
DE2508706C2 (de) * 1974-05-02 1984-10-11 International Business Machines Corp., Armonk, N.Y. Schaltungsanordnung zur Codierung von Datenbitfolgen
JPS5634266A (en) * 1979-08-29 1981-04-06 Hitachi Ltd Double run length encoding system
US4337458A (en) * 1980-02-19 1982-06-29 Sperry Corporation Data encoding method and system employing two-thirds code rate with full word look-ahead
US4413251A (en) * 1981-07-16 1983-11-01 International Business Machines Corporation Method and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3
US4488142A (en) * 1981-12-31 1984-12-11 International Business Machines Corporation Apparatus for encoding unconstrained data onto a (1,7) format with rate 2/3

Also Published As

Publication number Publication date
DE3678206D1 (de) 1991-04-25
EP0205009B1 (en) 1991-03-20
US4688016A (en) 1987-08-18
EP0205009A3 (en) 1989-05-03
JPS61288624A (ja) 1986-12-18
EP0205009A2 (en) 1986-12-17
JPH0214816B2 (enExample) 1990-04-10

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