BRPI0814501A2 - Método para fabricar uma estrutura de diodo emissor de luz - Google Patents

Método para fabricar uma estrutura de diodo emissor de luz

Info

Publication number
BRPI0814501A2
BRPI0814501A2 BRPI0814501-6A2A BRPI0814501A BRPI0814501A2 BR PI0814501 A2 BRPI0814501 A2 BR PI0814501A2 BR PI0814501 A BRPI0814501 A BR PI0814501A BR PI0814501 A2 BRPI0814501 A2 BR PI0814501A2
Authority
BR
Brazil
Prior art keywords
manufacturing
led structure
led
Prior art date
Application number
BRPI0814501-6A2A
Other languages
English (en)
Inventor
Grigoriy Basin
Robert S West
Paul S Martin
Original Assignee
Koninkl Philips Electronics Nv
Philips Lumileds Lighting Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Lumileds Lighting Co filed Critical Koninkl Philips Electronics Nv
Publication of BRPI0814501A2 publication Critical patent/BRPI0814501A2/pt
Publication of BRPI0814501B1 publication Critical patent/BRPI0814501B1/pt

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/54Encapsulations having a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/56Materials, e.g. epoxy or silicone resin

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
BRPI0814501A 2007-07-09 2008-07-03 método para fabricar uma estrutura de diodo emissor de luz BRPI0814501B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/775,059 US7867793B2 (en) 2007-07-09 2007-07-09 Substrate removal during LED formation
PCT/IB2008/052681 WO2009007886A1 (en) 2007-07-09 2008-07-03 Substrate removal during led formation

Publications (2)

Publication Number Publication Date
BRPI0814501A2 true BRPI0814501A2 (pt) 2015-02-03
BRPI0814501B1 BRPI0814501B1 (pt) 2018-12-11

Family

ID=39952224

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0814501A BRPI0814501B1 (pt) 2007-07-09 2008-07-03 método para fabricar uma estrutura de diodo emissor de luz

Country Status (9)

Country Link
US (1) US7867793B2 (pt)
EP (1) EP2168178B1 (pt)
JP (1) JP5654344B2 (pt)
KR (1) KR101535168B1 (pt)
CN (1) CN101743648B (pt)
BR (1) BRPI0814501B1 (pt)
RU (1) RU2466480C2 (pt)
TW (1) TWI467796B (pt)
WO (1) WO2009007886A1 (pt)

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JP5343040B2 (ja) * 2010-06-07 2013-11-13 株式会社東芝 半導体発光装置
KR20130136906A (ko) 2010-06-18 2013-12-13 글로 에이비 나노와이어 led 구조와 이를 제조하기 위한 방법
JP2012094716A (ja) * 2010-10-27 2012-05-17 Asahi Kasei E-Materials Corp 接続構造体及びその製造方法
KR101591991B1 (ko) * 2010-12-02 2016-02-05 삼성전자주식회사 발광소자 패키지 및 그 제조 방법
US8350251B1 (en) 2011-09-26 2013-01-08 Glo Ab Nanowire sized opto-electronic structure and method for manufacturing the same
KR102031654B1 (ko) * 2012-05-23 2019-10-15 삼성디스플레이 주식회사 윈도우 구조물, 그 제조 방법, 윈도우 구조물을 포함하는 카메라가 탑재된 전자 장치 및 그 제조 방법
TW201403892A (zh) * 2012-07-10 2014-01-16 Lextar Electronics Corp 發光二極體的基板及使用該基板的固晶方法
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JP6519127B2 (ja) * 2014-09-19 2019-05-29 日亜化学工業株式会社 発光装置の製造方法
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CN105244423B (zh) * 2015-10-30 2018-11-20 漳州立达信光电子科技有限公司 无衬底led芯片的封装方法及无衬底led芯片
US9721812B2 (en) * 2015-11-20 2017-08-01 International Business Machines Corporation Optical device with precoated underfill
US10461068B2 (en) * 2017-03-15 2019-10-29 The United States Of America As Represented By The Secretary Of The Air Force Highly integrated RF power and power conversion based on Ga2O3 technology
US11024611B1 (en) * 2017-06-09 2021-06-01 Goertek, Inc. Micro-LED array transfer method, manufacturing method and display device
US10490428B2 (en) * 2017-12-22 2019-11-26 Lumidleds LLC Method and system for dual stretching of wafers for isolated segmented chip scale packages
US10964867B2 (en) * 2018-10-08 2021-03-30 Facebook Technologies, Llc Using underfill or flux to promote placing and parallel bonding of light emitting diodes
JP7257187B2 (ja) * 2019-03-05 2023-04-13 東レエンジニアリング株式会社 チップ転写板ならびにチップ転写方法、画像表示装置の製造方法および半導体装置の製造方法
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Also Published As

Publication number Publication date
RU2466480C2 (ru) 2012-11-10
TWI467796B (zh) 2015-01-01
TW200924237A (en) 2009-06-01
JP5654344B2 (ja) 2015-01-14
EP2168178B1 (en) 2019-03-20
BRPI0814501B1 (pt) 2018-12-11
EP2168178A1 (en) 2010-03-31
WO2009007886A1 (en) 2009-01-15
JP2010533374A (ja) 2010-10-21
US7867793B2 (en) 2011-01-11
KR20100047255A (ko) 2010-05-07
US20090017566A1 (en) 2009-01-15
KR101535168B1 (ko) 2015-07-09
CN101743648A (zh) 2010-06-16
CN101743648B (zh) 2013-02-06
RU2010104249A (ru) 2011-08-20

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Legal Events

Date Code Title Description
B25G Requested change of headquarter approved

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V. (NL) , PHILIP

B25D Requested change of name of applicant approved

Owner name: PHILIPS LUMILEDS LIGHTING COMPANY, LLC (US) , KONI

B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
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