CN102194985B - 晶圆级封装之方法 - Google Patents

晶圆级封装之方法 Download PDF

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CN102194985B
CN102194985B CN201010117886XA CN201010117886A CN102194985B CN 102194985 B CN102194985 B CN 102194985B CN 201010117886X A CN201010117886X A CN 201010117886XA CN 201010117886 A CN201010117886 A CN 201010117886A CN 102194985 B CN102194985 B CN 102194985B
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CN102194985A (zh
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林升柏
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Rongchuang Energy Technology Co ltd
Zhanjing Technology Shenzhen Co Ltd
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Zhanjing Technology Shenzhen Co Ltd
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Abstract

本发明揭露一种晶圆级封装之方法，利用二次封装制程将一半导体组件以及一封装基板紧密地结合，藉此减少晶圆以及封装基板间的缝隙产生，并提升晶圆与封装基板之密合度。

Description

晶圆级封装之方法
技术领域
本发明涉及一种封装之方法，特别是关于晶圆级封装之方法。
背景技术
随着半导体发光组件之需求量日益增加，其封装之产能需求也越来越高。因此，许多的技术被揭露出来之目的在于增加半导体发光组件封装产能以及生产效率，例如晶圆级封装(wafer level package，WLP)技术结合微机电系统(micro-electromechanical system，MEMS)，利用黄光(photolithography process)以及微影技术(lithography)将电路设计与晶圆切割在晶圆级完成以提高产效率以及大量制造，同时亦可以将封装结构体积缩小，是符合现代化需求的一项技术。
然而，晶圆级封装制程仍有需多问题须待改善。例如美国专利公开号2007/0202623之技术，其利用晶圆级封装技术制造表面黏着(surface mount)之发光二极管封装结构。该项先技艺利用覆晶(flip chip)的技术将发光二极管晶粒固着于封装基板上，惟固晶的接着点(bump)之高度与大小往往不同而造成焊接不良或空焊，导致封装组件的失效以及降低制程的良率。
为解决上述技术之缺失，有一项技术利用底部填充胶(underfill)来改善上述问题，请参照美国专利公开号2009/0230409。此项先前技艺利用毛细现象使得封装胶渗入晶粒与封装基板之间的空间中，但其晶粒与封装基板之间仍然会有缝隙产生，且造成组件封装不完成且影响长期可靠性功能。因此，现今仍需要一项新的技术以克服上述技艺的缺失。
发明内容
凿于上述发明背景，本发明之目的为提供一种提高封装良率的晶圆级封装之方法。
一种晶圆级封装之方法，包含提供一暂时基板；形成一半导体组件于该暂时基板上，其中该半导体组件包含复数个发光单元，并且每一个发光单元具有至少一正电极以及一负电极；分别形成复数个凸块于该发光单元之该正电极以及该负电极上；形成一第一封装层于该暂时基板上并覆盖该半导体组件；设置一封装基板覆盖该封装层，其中该封装基板连结该复数个凸块；移除该暂时基板；形成一第二封装层于该半导体组件上，其中该第二封装层与该封装基板分别位于该半导体组件之相对两端；以及，切割该复数个发光单元，形成复数个半导体发光组件封装结构。
藉由上述晶圆级封装之方法，可增加晶圆与封装基板之密合度进而提升制程的良率，以及能提升晶圆与封装基板之密合度与一致性。
下面参照附图，结合具体实施例对本发明作进一步的描述。
附图说明
图1至图10A显示本发明之晶圆级封装方法之制程示意图，其中图9A和图9B系显示二种不同实施态样；以及
图10B显示依本发明所揭露制程所获得之一种半导体发光组件封装结构的放大剖面示意图。
主要元件符号说明
半导体发光组件封装结构    1
暂时基板                  10
半导体组件                11
凸块                      12a、12b
第一封装层                13
封装基板                  14
第二封装层                15
切割线                    16
导通道                    17
黏着层                    20
研磨工具                  100
发光单元                110
p型半导体层             111
发光层                  112
n型半导体层             113
正电极                  114
负电极                  115
表面                    131
电路结构                141
第一电路结构            141a
第二电路结构            141b
波长转换单元            151、152
具体实施方式
本发明在此所探讨的方向为一种晶圆级封装之方法。为了能彻底地了解本发明，将在下列的描述中提出详尽的步骤及其组成。显然地，本发明的施行并未限定于半导体封装结构之技艺者所熟习的特殊细节。另一方面，众所周知的组成或步骤并未描述于细节中，以避免造成本发明不必要之限制。本发明的较佳实施例会详细描述如下，然而除了这些详细描述之外，本发明还可以广泛地施行在其它的实施例中，且本发明的范围不受限定，其以之后的权利要求为准。
下文将配合图标与范例，详细说明本发明提供之各个较佳实施例及技术内容。
本发明揭露一种晶圆级封装之方法，能提升晶圆与封装基板之密合度与一致性，其晶圆级封装之步骤如下所述：
请参照图1，首先提供一暂时基板10，其中暂时基板10可以为磊晶基板，例如蓝宝石(Al2O3)基板、碳化硅(SiC)基板、铝酸锂基板(LiAlO2)、镓酸锂基板(LiGaO2)、硅(Si)基板、氮化镓(GaN)基板、氧化锌(ZnO)基板、氧化铝锌基板(AlZnO)、砷化镓(GaAs)基板、磷化镓(GaP)基板、锑化镓基板(GaSb)、磷化铟(InP)基板、砷化铟(InAs)基板或硒化锌(ZnSe)基板。
请参照图2，接着形成一半导体组件11于暂时基板10上，其中半导体组件11可以利用化学气相沉积法(chemical vapor deposition，CVD)形成，例如有机金属化学气相沉积(metal organic chemical vapor deposition，MOCVD)机台或是分子束磊晶(molecularbeam epitaxy，MBE)。于本发明较佳的实施例中，半导体组件11更包含一p型半导体层111，至少一发光层112以及一n型半导体层113。而半导体组件11可以为III-V族化合物半导体或II-VI族化合物半导体。另外，发光层112包含一单层单异质结构、双异质结构、单量子井层或多重量子井层结构，可以发出至少一种波长之光线。
请参照图3，接着将半导体组件11形成复数个发光单元110，其中复数个发光单元110可以利用黄光及微影技术形成。此外每一个发光单元110具有至少一正电极114以及一负电极115，并且正电极114系电性连结p型半导体层111，而负电极115系电性连结n型半导体层113。于本发明较佳实施例中，正电极114以及负电极115是镍(Ni)、铬(Cr)、金(Au)、银(Ag)、铂(Pt)、铜(Cu)、锌(Zn)、钛(Ti)、硅(Si)或其组成的合金，并且利用蒸镀(evoaporation)或溅镀(sputtering)的技术以及蚀刻(etching)技术形成。
请参照图4，接着形成复数个凸块12a于发光单元110之正电极114以及复数个凸块12b负电极115上。复数个凸块12a与复数个凸块12b彼此不相邻，并且其材质包含镍(Ni)、锡(Sn)、铬(Cr)、铜(Cu)、金(Au)、银(Ag)、铅(Pb)、铂(Pt)、锌(Zn)、钛(Ti)、硅(Si)或其组成的合金，可以利用钢板印刷(stencil printing)的技术制程。
请参照图5，接着形成一第一封装层13于暂时基板10上并覆盖复数个发光单元110。于本发明一较佳实施例中，第一封装层13的材质为环氧树脂(epoxy)、硅胶(silicone)或其组合或改质的胶材，并且利用转注成型(transfermolding)、旋转涂布(spin coating)或注射成型(injection molding)之手段形成。
请参照图6，接着利用研磨工具100研磨(grinding)第一封装层13之表面131，使得第一封装层13之表面131形成一光滑之平面。值得说明的是，复数个凸块12a、12b可以藉由研磨之步骤，外露出第一封装层13之表面131并形成平整之外露面；或者，于形成第一封装层13之步骤时，便外露出第一封装层13之表面131，再藉由研磨之步骤形成平整之表面。
请参照图7A，接着提供一封装基板14固定于第一封装层13之表面131，其中封装基板14与暂时基板10分别位于第一封装层13之相对两侧。封装基板14包含一电路结构141，其具有复数个第一电路结构141a以及复数个第二电路结构141b所构成。此外，复数个第一电路结构141a与复数个第二电路结构141b彼此对应且电性连结，其中复数个发光单元110之正、负电极114、115可以分别藉由复数个凸块12a、12b以及电路结构141电性导通至封装基板14表面之第二电路结构141b。于本发明较佳实施例中，封装基板14可以是印刷电路板(printed circuit board，PCB)、陶瓷(ceramic)基板、硅(silicon)基板、金属基板、氧化硅(SiO)或绝缘胶材等。再者，电路结构141则为导电材料所组成，例如铜(Cu)、镍(Ni)、金(Au)、银(Ag)或其组合。
请参照图7B，于本发明另一较佳实施例中，是利用一黏着层20将封装基板14固定于表面131之手段。值得说明的是，黏着层20可以为异方性导电(anisotropic conductive)的薄膜(film)、胶(gel)或膏(paste)，利用热压转印(thermaltransfer printing)之手段形成于第一封装层13之表面131。值得说明的是，异方性导电的材料为导电粒子均匀的散布在有机树脂材料中，利用适当的压力、温度及时间使得有机材料开始流动而达到不同材质相互连结且能够紧密结合连结材料，同时具有垂直结构电性导通而水平面绝缘的特性。
请参照图8，接着将暂时基板10从复数个发光单元110以及第一封装层13之表面移除。于本发明较佳的实施例中，移除暂时基板10之手段包含了剥离技术(lift off)、蚀刻技术(etching)、切割(cutting)或研磨(grinding)。
请参照图9A以及图9B，接着形成一第二封装层15于复数个发光单元110以及第一封装层13之表面，其中第二封装层15与封装基板14分别位于第一封装层13之相对两侧。第二封装层15之材质包含环氧树脂、硅胶或其组合或改质的材料，可以利用转注成型、注射成型或旋转涂布之手段形成。再者，第二封装层15可以包含至少一种波长转换单元151，其中波长转换单元151受到发光单元110之光线激发并发出另一波长之光线。于本发明较佳的实施例中，波长转换单元151可以为钇铝石榴石(YAG)、铽铝石榴石(TAG)、硅酸盐、氮化物、氮氧化物、磷化物、硫化物或其组合。值得说明的是，波长转换单元151可以为粉末状且均匀地掺杂于第二封装层15中，如图9A所示；或者，为层状(layer)之波长转换单元152且均匀地覆盖发光单元110之表面，如图9B所示，其中波长转换单元152可以为薄膜(film)、贴片(patch)或荧光片(Lumiramic plate)，利用涂覆(coating)、胶(paste)或喷雾(spray)之手段形成。
请参照图10A以及图10B，沿着复数条切割线16切割上述结构，以形成复数个半导体发光组件封装结构1，其中每一个半导体发光组件封装结构1包含封装基板14具有电路结构141、发光单元110、第一封装层13、波长转换单元152以及第二封装层15。于本发明另一较佳的实施例中，第二半导体发光组件封装结构是包含复数个发光单元所组成(未显示图)，以形成高功率之封装组件。值得说明的是，电路结构141之第一电路结构141a可以分别藉由导通道17电性连结于电路结构141之第二电路结构141b，使得半导体发光组件封装结构1形成一表面黏着组件。然而，熟知本项技艺者皆知，导通道17不仅可以设置于封装基板14内部(如图10B)，亦可以位于封装基板14之侧边并露出半导体发光组件封装结构1之外(未显示图)。
从本发明之手段与具有的功效中，可以得到本发明具有诸多的优点。首先，利用本发明所揭露的制程以及结构，所制作出的半导体发光组件封装结构，不仅能有效的增加晶圆与封装基板之密合度进而提升封装制程的良率。再者，藉由本发明的手段亦可以缩小封装结构厚度，以减少组件所占用之体积与缩短封装结构之散热路径。
显然地，依照上面实施例中的描述，本发明可能有许多的修正与差异。因此需要在其附加的权利要求项之范围内加以理解，除了上述详细的描述外，本发明还可以广泛地在其它的实施例中施行。上述仅为本发明之较佳实施例而已，并非用以限定本发明之权利要求；凡其它未脱离本发明所揭示之精神下所完成的等效改变或修饰，均应包含在下述权利要求。

Claims (9)

1.一种晶圆级封装之方法，包含:
(i)提供一暂时基板；
(ii)形成一半导体组件于该暂时基板上，其中该半导体组件包含复数个发光单元，并且每一个发光单元具有至少一正电极以及一负电极；
(iii)分别形成复数个凸块于该发光单元之该正电极以及该负电极上；
(iv)形成一第一封装层于该暂时基板上并覆盖该半导体组件，研磨第一封装层表面，使第一封装层表面形成一光滑平面，并使连接正电极及负电极的凸块外露于第一封装层而形成平整表面；
(v)设置一封装基板黏着该第一封装层，其中该封装基板系电性连结该复数个凸块；
(vi)移除该暂时基板；
(vii)形成一第二封装层于该半导体组件上，其中该第二封装层与该封装基板分别位于该半导体组件之相对两端；以及
(viii)切割该复数个发光单元，形成复数个半导体发光组件封装结构。
2.根据权利要求1所述的晶圆级封装之方法，其特征在于:
每一个该发光单元包含一p型半导体层，至少一发光层以及一n型半导体层，并且该至少一发光层可以发出至少一种波长之光线。
3.根据权利要求1所述的晶圆级封装之方法，其特征在于:
该(iv)步骤系利用转注成型(transfer molding)、旋转涂布(spincoating)或注射成型(injection molding)之手段形成，而该第一封装层包含环氧树脂(epoxy)、硅胶(silicone)或其混合或改质之材料。
4.根据权利要求1所述的晶圆级封装之方法，其特征在于:
该(vii)步骤系利用转注成型(transfer molding)、旋转涂布(spincoating)或注射成型(injection molding)之手段形成，而该第二封装层包含环氧树脂(epoxy)、硅胶(silicone)或其混合或改质之材料。
5.根据权利要求1所述的晶圆级封装之方法，其特征在于:
该封装基板黏着该第一封装层之手段系利用异方性导电(anisotropic conductive)材料固接而成，并且该异方性导电材料包含薄膜(film)、胶(gel)或膏(paste)，利用热压转印(thermal transfer printing)之手段形成。
6.根据权利要求1所述的晶圆级封装之方法，其特征在于:
该封装基板包含一电路结构，并且该电路结构具有一第一电路结构以及一第二电路结构分别位于该封装基板之相对两侧，而该发光单元系藉由该复数个凸块电性连结该电路结构之该第一电路结构。
7.根据权利要求6所述的晶圆级封装之方法，其特征在于:
该电路结构具有至少一导信道，并且该导信道连结该第一电路结构以及该第二电路结构。
8.根据权利要求1所述的晶圆级封装之方法，其特征在于:
更包含一覆盖至少一荧光层于该发光单元的步骤于该(vi)步骤与该(vii)步骤之间，其中该至少一荧光层包含钇铝石榴石(YAG)、铽铝石榴石(TAG)、硅酸盐、氮化物、氮氧化物、磷化物、硫化物或其组合。
9.根据权利要求1所述的晶圆级封装之方法，其特征在于，所述的半导体发光组件封装结构，包含:
一部分之该封装基板；
至少一该发光单元，位于该封装基板上；
一部分之该第一封装层，位于该封装基板上并且环绕该至少一发光单元；以及
一部份之该第二封装层，覆盖该至少一发光单元与该一部分之第一封装层。
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