BR8700839A - Metodo para fabricacao de circuitos integrados cmos,sem a formacao de ondulados(no oxido)nas regioes de isolacao - Google Patents
Metodo para fabricacao de circuitos integrados cmos,sem a formacao de ondulados(no oxido)nas regioes de isolacaoInfo
- Publication number
- BR8700839A BR8700839A BR8700839A BR8700839A BR8700839A BR 8700839 A BR8700839 A BR 8700839A BR 8700839 A BR8700839 A BR 8700839A BR 8700839 A BR8700839 A BR 8700839A BR 8700839 A BR8700839 A BR 8700839A
- Authority
- BR
- Brazil
- Prior art keywords
- corrugated
- oxide
- manufacture
- formation
- integrated circuits
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/840,180 US4729006A (en) | 1986-03-17 | 1986-03-17 | Sidewall spacers for CMOS circuit stress relief/isolation and method for making |
Publications (1)
Publication Number | Publication Date |
---|---|
BR8700839A true BR8700839A (pt) | 1987-12-22 |
Family
ID=25281647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR8700839A BR8700839A (pt) | 1986-03-17 | 1987-02-23 | Metodo para fabricacao de circuitos integrados cmos,sem a formacao de ondulados(no oxido)nas regioes de isolacao |
Country Status (7)
Country | Link |
---|---|
US (1) | US4729006A (pt) |
EP (1) | EP0242506B1 (pt) |
JP (1) | JPH0680724B2 (pt) |
AU (1) | AU579764B2 (pt) |
BR (1) | BR8700839A (pt) |
CA (1) | CA1245373A (pt) |
DE (1) | DE3784958T2 (pt) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4892840A (en) * | 1986-03-27 | 1990-01-09 | Texas Instruments Incorporated | EPROM with increased floating gate/control gate coupling |
US5008722A (en) * | 1986-03-27 | 1991-04-16 | Texas Instruments Incorporated | Non-volatile memory |
US4855800A (en) * | 1986-03-27 | 1989-08-08 | Texas Instruments Incorporated | EPROM with increased floating gate/control gate coupling |
US5292671A (en) * | 1987-10-08 | 1994-03-08 | Matsushita Electric Industrial, Co., Ltd. | Method of manufacture for semiconductor device by forming deep and shallow regions |
EP0794575A3 (en) * | 1987-10-08 | 1998-04-01 | Matsushita Electric Industrial Co., Ltd. | Structure and method of manufacture for CMOS semiconductor device against latch-up effect |
US4905062A (en) * | 1987-11-19 | 1990-02-27 | Texas Instruments Incorporated | Planar famos transistor with trench isolation |
WO1989005517A1 (en) * | 1987-12-02 | 1989-06-15 | Advanced Micro Devices, Inc. | Self-aligned, planarized contacts for semiconductor devices |
US5081516A (en) * | 1987-12-02 | 1992-01-14 | Advanced Micro Devices, Inc. | Self-aligned, planarized contacts for semiconductor devices |
FR2631488B1 (fr) * | 1988-05-10 | 1990-07-27 | Thomson Hybrides Microondes | Circuit integre hyperfrequence de type planar, comportant au moins un composant mesa, et son procede de fabrication |
US5164813A (en) * | 1988-06-24 | 1992-11-17 | Unitrode Corporation | New diode structure |
US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
US5248894A (en) * | 1989-10-03 | 1993-09-28 | Harris Corporation | Self-aligned channel stop for trench-isolated island |
US5132774A (en) * | 1990-02-05 | 1992-07-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including interlayer insulating film |
US5250468A (en) * | 1990-02-05 | 1993-10-05 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device including interlaying insulating film |
US5340754A (en) * | 1992-09-02 | 1994-08-23 | Motorla, Inc. | Method for forming a transistor having a dynamic connection between a substrate and a channel region |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
DE4409863C1 (de) * | 1994-03-22 | 1995-05-04 | Siemens Ag | Verfahren zur Herstellung eines Einzelelektronen-Bauelementes |
JP3171764B2 (ja) * | 1994-12-19 | 2001-06-04 | シャープ株式会社 | 半導体装置の製造方法 |
US6225230B1 (en) * | 1996-05-28 | 2001-05-01 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
US5834358A (en) * | 1996-11-12 | 1998-11-10 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
US5923992A (en) * | 1997-02-11 | 1999-07-13 | Advanced Micro Devices, Inc. | Integrated circuit formed with shallow isolation structures having nitride placed on the trench dielectric |
US5770504A (en) * | 1997-03-17 | 1998-06-23 | International Business Machines Corporation | Method for increasing latch-up immunity in CMOS devices |
KR100230431B1 (ko) * | 1997-07-25 | 1999-11-15 | 윤종용 | 2 종류의 산화막을 사용하는 트렌치 소자 분리 방법 |
US6239002B1 (en) * | 1998-10-19 | 2001-05-29 | Taiwan Semiconductor Manufacturing Company | Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer |
US6239476B1 (en) | 1998-10-21 | 2001-05-29 | Advanced Micro Devices, Inc. | Integrated circuit isolation structure employing a protective layer and method for making same |
DE19920333A1 (de) * | 1999-05-03 | 2000-11-16 | Siemens Ag | Verfahren zur Herstellung einer Halbleitervorrichtung |
US6281084B1 (en) | 1999-08-31 | 2001-08-28 | Infineon Technologies Corporation | Disposable spacers for improved array gapfill in high density DRAMs |
KR100346842B1 (ko) * | 2000-12-01 | 2002-08-03 | 삼성전자 주식회사 | 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 디바이스및 그 제조방법 |
US6806584B2 (en) | 2002-10-21 | 2004-10-19 | International Business Machines Corporation | Semiconductor device structure including multiple fets having different spacer widths |
GB0226402D0 (en) * | 2002-11-12 | 2002-12-18 | Koninkl Philips Electronics Nv | Semiconductor device channel termination |
US7279746B2 (en) * | 2003-06-30 | 2007-10-09 | International Business Machines Corporation | High performance CMOS device structures and method of manufacture |
US6956266B1 (en) | 2004-09-09 | 2005-10-18 | International Business Machines Corporation | Structure and method for latchup suppression utilizing trench and masked sub-collector implantation |
US7141836B1 (en) * | 2005-05-31 | 2006-11-28 | International Business Machines Corporation | Pixel sensor having doped isolation structure sidewall |
JP2007189110A (ja) * | 2006-01-13 | 2007-07-26 | Sharp Corp | 半導体装置及びその製造方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3853633A (en) * | 1972-12-04 | 1974-12-10 | Motorola Inc | Method of making a semi planar insulated gate field-effect transistor device with implanted field |
US3890632A (en) * | 1973-12-03 | 1975-06-17 | Rca Corp | Stabilized semiconductor devices and method of making same |
US3969168A (en) * | 1974-02-28 | 1976-07-13 | Motorola, Inc. | Method for filling grooves and moats used on semiconductor devices |
US4005452A (en) * | 1974-11-15 | 1977-01-25 | International Telephone And Telegraph Corporation | Method for providing electrical isolating material in selected regions of a semiconductive material and the product produced thereby |
US4056415A (en) * | 1975-08-04 | 1977-11-01 | International Telephone And Telegraph Corporation | Method for providing electrical isolating material in selected regions of a semiconductive material |
US4054895A (en) * | 1976-12-27 | 1977-10-18 | Rca Corporation | Silicon-on-sapphire mesa transistor having doped edges |
JPS5529116A (en) * | 1978-08-23 | 1980-03-01 | Hitachi Ltd | Manufacture of complementary misic |
US4394196A (en) * | 1980-07-16 | 1983-07-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of etching, refilling and etching dielectric grooves for isolating micron size device regions |
DE3170644D1 (en) * | 1980-11-29 | 1985-06-27 | Toshiba Kk | Method of filling a groove in a semiconductor substrate |
EP0061855B1 (en) * | 1981-03-20 | 1985-08-14 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
JPS57204148A (en) * | 1981-06-10 | 1982-12-14 | Toshiba Corp | Manufacture of semiconductor device |
US4613885A (en) * | 1982-02-01 | 1986-09-23 | Texas Instruments Incorporated | High-voltage CMOS process |
US4433008A (en) * | 1982-05-11 | 1984-02-21 | Rca Corporation | Doped-oxide diffusion of phosphorus using borophosphosilicate glass |
US4514440A (en) * | 1983-12-12 | 1985-04-30 | Allied Corporation | Spin-on dopant method |
JPS59161046A (ja) * | 1983-03-04 | 1984-09-11 | Fujitsu Ltd | 半導体装置における配線方法 |
JPS59169149A (ja) * | 1983-03-16 | 1984-09-25 | Fujitsu Ltd | 半導体装置 |
JPS59175744A (ja) * | 1983-03-25 | 1984-10-04 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPS59182537A (ja) * | 1983-04-01 | 1984-10-17 | Hitachi Ltd | 半導体装置の製造方法 |
US4498227A (en) * | 1983-07-05 | 1985-02-12 | Fairchild Camera & Instrument Corporation | Wafer fabrication by implanting through protective layer |
JPS6020529A (ja) * | 1983-07-13 | 1985-02-01 | Matsushita Electronics Corp | 半導体装置の製造方法 |
DE3472604D1 (en) * | 1983-10-11 | 1988-08-11 | American Telephone & Telegraph | Semiconductor integrated circuits containing complementary metal oxide semiconductor devices |
JPS60164335A (ja) * | 1984-02-06 | 1985-08-27 | Nec Corp | 半導体装置の製造方法 |
US4599789A (en) * | 1984-06-15 | 1986-07-15 | Harris Corporation | Process of making twin well VLSI CMOS |
US4556585A (en) * | 1985-01-28 | 1985-12-03 | International Business Machines Corporation | Vertically isolated complementary transistors |
-
1986
- 1986-03-17 US US06/840,180 patent/US4729006A/en not_active Expired - Fee Related
-
1987
- 1987-01-09 JP JP62002007A patent/JPH0680724B2/ja not_active Expired - Lifetime
- 1987-01-23 EP EP87100962A patent/EP0242506B1/en not_active Expired - Lifetime
- 1987-01-23 DE DE87100962T patent/DE3784958T2/de not_active Expired - Lifetime
- 1987-02-16 CA CA000529768A patent/CA1245373A/en not_active Expired
- 1987-02-23 BR BR8700839A patent/BR8700839A/pt not_active IP Right Cessation
- 1987-03-12 AU AU69959/87A patent/AU579764B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
EP0242506A2 (en) | 1987-10-28 |
DE3784958D1 (de) | 1993-04-29 |
EP0242506A3 (en) | 1990-03-14 |
AU579764B2 (en) | 1988-12-08 |
CA1245373A (en) | 1988-11-22 |
JPS62219943A (ja) | 1987-09-28 |
EP0242506B1 (en) | 1993-03-24 |
JPH0680724B2 (ja) | 1994-10-12 |
AU6995987A (en) | 1987-09-24 |
US4729006A (en) | 1988-03-01 |
DE3784958T2 (de) | 1993-09-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B21A | Expiry acc. art. 78, item i of ipl- expiry of the term of protection |
Free format text: PATENTE EXTINTA EM 23/02/2002 |