BR8604530A - Controlador periferico - Google Patents

Controlador periferico

Info

Publication number
BR8604530A
BR8604530A BR8604530A BR8604530A BR8604530A BR 8604530 A BR8604530 A BR 8604530A BR 8604530 A BR8604530 A BR 8604530A BR 8604530 A BR8604530 A BR 8604530A BR 8604530 A BR8604530 A BR 8604530A
Authority
BR
Brazil
Prior art keywords
data transfers
peripheral
tape
master microprocessor
units
Prior art date
Application number
BR8604530A
Other languages
English (en)
Inventor
Jerrold E Buggert
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of BR8604530A publication Critical patent/BR8604530A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
BR8604530A 1985-01-07 1986-01-06 Controlador periferico BR8604530A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/689,209 US4750107A (en) 1985-01-07 1985-01-07 Printer-tape data link processor with DMA slave controller which automatically switches between dual output control data chomels
PCT/US1986/000009 WO1986004169A1 (en) 1985-01-07 1986-01-06 Printer-tape data link processor

Publications (1)

Publication Number Publication Date
BR8604530A true BR8604530A (pt) 1987-07-14

Family

ID=24767486

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8604530A BR8604530A (pt) 1985-01-07 1986-01-06 Controlador periferico

Country Status (8)

Country Link
US (1) US4750107A (pt)
EP (1) EP0209565B1 (pt)
JP (1) JPS62500962A (pt)
AT (1) ATE89424T1 (pt)
BR (1) BR8604530A (pt)
CA (1) CA1246749A (pt)
DE (1) DE3688408T2 (pt)
WO (1) WO1986004169A1 (pt)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07117886B2 (ja) * 1985-11-28 1995-12-18 キヤノン株式会社 デ−タ制御装置
JPS6336461A (ja) * 1986-07-31 1988-02-17 Pfu Ltd 汎用チャネル制御方式
US5070477A (en) * 1987-04-13 1991-12-03 Unisys Coporation Port adapter system including a controller for switching channels upon encountering a wait period of data transfer
US4905184A (en) * 1987-09-21 1990-02-27 Unisys Corporation Address control system for segmented buffer memory
US5121479A (en) * 1988-01-27 1992-06-09 Storage Technology Corporation Early start mode data transfer apparatus
US5003471A (en) * 1988-09-01 1991-03-26 Gibson Glenn A Windowed programmable data transferring apparatus which uses a selective number of address offset registers and synchronizes memory access to buffer
JPH0269821A (ja) * 1988-09-06 1990-03-08 Seiko Epson Corp 画像表示制御装置
US5012404A (en) * 1988-10-28 1991-04-30 United Technologies Corporation Integrated circuit remote terminal stores interface for communication between CPU and serial bus
US4888727A (en) * 1989-01-10 1989-12-19 Bull Hn Information Systems Inc. Peripheral controller with paged data buffer management
JP2550496B2 (ja) * 1989-03-30 1996-11-06 三菱電機株式会社 Ｄｍａコントローラ
JP2995752B2 (ja) * 1989-07-21 1999-12-27 日本電気株式会社 バスアーキテクチャ変換回路
GB9018990D0 (en) * 1990-08-31 1990-10-17 Ncr Co Register control for workstation interfacing means
JPH087715B2 (ja) * 1990-11-15 1996-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理装置及びアクセス制御方法
DE69124946T2 (de) * 1990-11-30 1997-09-18 Ibm Bidirektionaler FIFO-Puffer zur Schnittstellenbildung zwischen zwei Bussen
US5530901A (en) * 1991-11-28 1996-06-25 Ricoh Company, Ltd. Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively
US5386532A (en) * 1991-12-30 1995-01-31 Sun Microsystems, Inc. Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels
EP0582535A1 (en) * 1992-07-07 1994-02-09 International Business Machines Corporation Communication system and method utilizing picoprocessors for performing complex functions out of main communication data path
US5499384A (en) * 1992-12-31 1996-03-12 Seiko Epson Corporation Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device
AT400786B (de) * 1993-09-15 1996-03-25 Fendt Johann Mag Vorrichtung zur datenübertragung zwischen einem faxgerät und einer gegenstation
US5664223A (en) * 1994-04-05 1997-09-02 International Business Machines Corporation System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
US5828903A (en) * 1994-09-30 1998-10-27 Intel Corporation System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer
KR100200968B1 (ko) * 1996-10-17 1999-06-15 윤종용 화상형성장치의 호스트 인터페이스회로
JP2000048549A (ja) * 1998-08-03 2000-02-18 Fujitsu Ltd テープ装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573852A (en) * 1968-08-30 1971-04-06 Texas Instruments Inc Variable time slot assignment of virtual processors
US4162520A (en) * 1976-09-30 1979-07-24 Burroughs Corporation Intelligent input-output interface control unit for input-output subsystem
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4516199A (en) * 1979-10-11 1985-05-07 Nanodata Computer Corporation Data processing system
JPS5868346A (ja) * 1981-10-18 1983-04-23 Toshiba Corp デ−タ伝送システム
JPS5877034A (ja) * 1981-10-30 1983-05-10 Hitachi Ltd 記録方法
US4443850A (en) * 1981-12-01 1984-04-17 Burroughs Corporation Interface circuit for subsystem controller
US4538224A (en) * 1982-09-30 1985-08-27 At&T Bell Laboratories Direct memory access peripheral unit controller
US4543626A (en) * 1982-12-06 1985-09-24 Digital Equipment Corporation Apparatus and method for controlling digital data processing system employing multiple processors
US4549263A (en) * 1983-02-14 1985-10-22 Texas Instruments Incorporated Device interface controller for input/output controller
US4616337A (en) * 1983-03-30 1986-10-07 Burroughs Corporation Automatic read system for peripheral-controller
US4602331A (en) * 1983-06-30 1986-07-22 Burroughs Corporation Magnetic tape-data link processor providing automatic data transfer

Also Published As

Publication number Publication date
EP0209565A1 (en) 1987-01-28
US4750107A (en) 1988-06-07
DE3688408D1 (de) 1993-06-17
ATE89424T1 (de) 1993-05-15
JPH0442698B2 (pt) 1992-07-14
JPS62500962A (ja) 1987-04-16
WO1986004169A1 (en) 1986-07-17
DE3688408T2 (de) 1993-08-26
CA1246749A (en) 1988-12-13
EP0209565B1 (en) 1993-05-12

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