ES487173A1 - Un controlador de entrada-salida en un sistema de tratamien-to de datos - Google Patents

Un controlador de entrada-salida en un sistema de tratamien-to de datos

Info

Publication number
ES487173A1
ES487173A1 ES487173A ES487173A ES487173A1 ES 487173 A1 ES487173 A1 ES 487173A1 ES 487173 A ES487173 A ES 487173A ES 487173 A ES487173 A ES 487173A ES 487173 A1 ES487173 A1 ES 487173A1
Authority
ES
Spain
Prior art keywords
host processor
transfer
input
data processing
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES487173A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES487173A1 publication Critical patent/ES487173A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)

Abstract

Un controlador de entrada salida en un sistema de tratamiento de datos para transferir datos entre un ordenador central y una pluralidad de dispositivos de entrada salida, en donde el ordenador central genera una orden de transferencia y cada uno de los dispositivos de la pluralidad de dispositivos de entrada salida genera solicitudes de servicios asíncrono múltiples para transferencia al ordenador central, que comprende: medios de control para controlar la transferencia de las solicitudes de servicio desde la pluralidad de dispositivos de entrada salida al ordenador central; y generando dichos medios de control una señal de interrupción de ordenador central para aplicación al ordenador central, de tal modo que en respuesta a dicha señal de interrupción de ordenador central, el ordenador central genera la orden de transferencia para permitir que dichos medios de control transfieran las solicitudes de servicios al ordenador central, de tal modo que en respuesta a dicha señal de interrupciónde ordenador central, el ordenador central general la orden de transferencia para permitir que dichos medios de control central mientras permiten concurrentemente la transferencia de datos entre el ordenador central y la pluralidad de dispositivos de entrada salida.
ES487173A 1978-12-22 1979-12-21 Un controlador de entrada-salida en un sistema de tratamien-to de datos Expired ES487173A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/972,381 US4268906A (en) 1978-12-22 1978-12-22 Data processor input/output controller

Publications (1)

Publication Number Publication Date
ES487173A1 true ES487173A1 (es) 1980-09-16

Family

ID=25519589

Family Applications (1)

Application Number Title Priority Date Filing Date
ES487173A Expired ES487173A1 (es) 1978-12-22 1979-12-21 Un controlador de entrada-salida en un sistema de tratamien-to de datos

Country Status (9)

Country Link
US (1) US4268906A (es)
EP (1) EP0012886B1 (es)
JP (1) JPS5847049B2 (es)
AU (1) AU534448B2 (es)
BR (1) BR7908412A (es)
CA (1) CA1128209A (es)
DE (1) DE2964318D1 (es)
ES (1) ES487173A1 (es)
IT (1) IT1209157B (es)

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JPS5833770A (ja) * 1981-08-24 1983-02-28 Sony Corp デジタルデ−タのプログラム転送方法
JPS58129644A (ja) * 1982-01-29 1983-08-02 Nec Corp デ−タ処理装置
GB8310003D0 (en) * 1983-04-13 1983-05-18 Gen Electric Co Plc Input signal handling apparatus
US4654820A (en) * 1983-11-30 1987-03-31 At&T Bell Laboratories Interrupt bus structure
US4750113A (en) * 1985-02-28 1988-06-07 Unisys Corporation Dual function I/O controller
US4747047A (en) * 1985-12-06 1988-05-24 Unisys Corporation Data transfer system using two peripheral controllers to access dual-ported data storage units
US4961067A (en) * 1986-07-28 1990-10-02 Motorola, Inc. Pattern driven interrupt in a digital data processor
JPS6375955A (ja) * 1986-09-19 1988-04-06 Fujitsu Ltd プログラムモ−ド・アクセス制御方式
US5134706A (en) * 1987-08-07 1992-07-28 Bull Hn Information Systems Inc. Bus interface interrupt apparatus
US5131081A (en) * 1989-03-23 1992-07-14 North American Philips Corp., Signetics Div. System having a host independent input/output processor for controlling data transfer between a memory and a plurality of i/o controllers
US5097439A (en) * 1989-11-08 1992-03-17 Quantum Corporation Expansible fixed disk drive subsystem for computer
US5333301A (en) * 1990-12-14 1994-07-26 International Business Machines Corporation Data transfer bus system and method serving multiple parallel asynchronous units
JPH0656601B2 (ja) * 1991-11-28 1994-07-27 インターナショナル・ビジネス・マシーンズ・コーポレイション データ転送制御用インタフェース回路
US5734924A (en) * 1993-08-27 1998-03-31 Advanced System Products, Inc. System for host accessing local memory by asserting address signal corresponding to host adapter and data signal indicating address of location in local memory
US5727184A (en) * 1994-06-27 1998-03-10 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5794014A (en) * 1994-06-27 1998-08-11 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5661848A (en) * 1994-09-08 1997-08-26 Western Digital Corp Multi-drive controller with encoder circuitry that generates ECC check bytes using the finite field for optical data for appending to data flowing to HDA
US6434630B1 (en) 1999-03-31 2002-08-13 Qlogic Corporation Host adapter for combining I/O completion reports and method of using the same
US6430643B1 (en) * 1999-09-02 2002-08-06 International Business Machines Corporation Method and system for assigning interrupts among multiple interrupt presentation controllers
US7138989B2 (en) * 2000-09-15 2006-11-21 Silicon Graphics, Inc. Display capable of displaying images in response to signals of a plurality of signal formats
US7154886B2 (en) * 2002-07-22 2006-12-26 Qlogic Corporation Method and system for primary blade selection in a multi-module fiber channel switch
US7230929B2 (en) * 2002-07-22 2007-06-12 Qlogic, Corporation Method and system for dynamically assigning domain identification in a multi-module fibre channel switch
US7397768B1 (en) 2002-09-11 2008-07-08 Qlogic, Corporation Zone management in a multi-module fibre channel switch
US7319669B1 (en) 2002-11-22 2008-01-15 Qlogic, Corporation Method and system for controlling packet flow in networks
US7646767B2 (en) * 2003-07-21 2010-01-12 Qlogic, Corporation Method and system for programmable data dependant network routing
US7234101B1 (en) 2003-08-27 2007-06-19 Qlogic, Corporation Method and system for providing data integrity in storage systems
US7219263B1 (en) 2003-10-29 2007-05-15 Qlogic, Corporation Method and system for minimizing memory corruption
US7930377B2 (en) 2004-04-23 2011-04-19 Qlogic, Corporation Method and system for using boot servers in networks
US7669190B2 (en) 2004-05-18 2010-02-23 Qlogic, Corporation Method and system for efficiently recording processor events in host bus adapters
US7577772B2 (en) * 2004-09-08 2009-08-18 Qlogic, Corporation Method and system for optimizing DMA channel selection
US20060064531A1 (en) * 2004-09-23 2006-03-23 Alston Jerald K Method and system for optimizing data transfer in networks
US7676611B2 (en) 2004-10-01 2010-03-09 Qlogic, Corporation Method and system for processing out of orders frames
US7380030B2 (en) * 2004-10-01 2008-05-27 Qlogic, Corp. Method and system for using an in-line credit extender with a host bus adapter
US7398335B2 (en) * 2004-11-22 2008-07-08 Qlogic, Corporation Method and system for DMA optimization in host bus adapters
US7164425B2 (en) * 2004-12-21 2007-01-16 Qlogic Corporation Method and system for high speed network application
US7392437B2 (en) 2005-01-20 2008-06-24 Qlogic, Corporation Method and system for testing host bus adapters
US7281077B2 (en) * 2005-04-06 2007-10-09 Qlogic, Corporation Elastic buffer module for PCI express devices
US7231480B2 (en) * 2005-04-06 2007-06-12 Qlogic, Corporation Method and system for receiver detection in PCI-Express devices
US7461195B1 (en) 2006-03-17 2008-12-02 Qlogic, Corporation Method and system for dynamically adjusting data transfer rates in PCI-express devices
US10238146B2 (en) 2016-02-27 2019-03-26 Brandon Nedelman Hookah vaporizor machine

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US3447135A (en) * 1966-08-18 1969-05-27 Ibm Peripheral data exchange
US3665415A (en) * 1970-04-29 1972-05-23 Honeywell Inf Systems Data processing system with program interrupt priority apparatus utilizing working store for multiplexing interrupt requests
GB1397438A (en) * 1971-10-27 1975-06-11 Ibm Data processing system
IT988956B (it) * 1973-06-12 1975-04-30 Olivetti & Co Spa Governo multiplo
IT1002275B (it) * 1973-12-27 1976-05-20 Honeywell Inf Systems Sistema di elaborazione dati a piu canali di ingresso uscita a risorse orientate per livelli di servizio distinti e interrompi bili
US4079448A (en) * 1975-04-07 1978-03-14 Compagnie Honeywell Bull Apparatus for synchronizing tasks on peripheral devices
US4060849A (en) * 1975-10-28 1977-11-29 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull Data input and output controller
US4038642A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Input/output interface logic for concurrent operations
US4080649A (en) * 1976-12-16 1978-03-21 Honeywell Information Systems Inc. Balancing the utilization of I/O system processors
US4115854A (en) * 1977-03-28 1978-09-19 International Business Machines Corporation Channel bus controller
US4126897A (en) * 1977-07-05 1978-11-21 International Business Machines Corporation Request forwarding system
US4110830A (en) * 1977-07-05 1978-08-29 International Business Machines Corporation Channel storage adapter

Also Published As

Publication number Publication date
AU5374779A (en) 1980-06-26
JPS5587218A (en) 1980-07-01
IT1209157B (it) 1989-07-10
BR7908412A (pt) 1980-10-07
US4268906A (en) 1981-05-19
JPS5847049B2 (ja) 1983-10-20
EP0012886A1 (fr) 1980-07-09
IT7928121A0 (it) 1979-12-18
AU534448B2 (en) 1984-02-02
CA1128209A (en) 1982-07-20
EP0012886B1 (fr) 1982-12-15
DE2964318D1 (en) 1983-01-20

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970203