JPS57143670A - Parallel processing system - Google Patents

Parallel processing system

Info

Publication number
JPS57143670A
JPS57143670A JP2943481A JP2943481A JPS57143670A JP S57143670 A JPS57143670 A JP S57143670A JP 2943481 A JP2943481 A JP 2943481A JP 2943481 A JP2943481 A JP 2943481A JP S57143670 A JPS57143670 A JP S57143670A
Authority
JP
Japan
Prior art keywords
transferred
central processing
operating
processing device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2943481A
Other languages
Japanese (ja)
Inventor
Hirotoshi Torigoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2943481A priority Critical patent/JPS57143670A/en
Publication of JPS57143670A publication Critical patent/JPS57143670A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To reduce the load of a central processing device to make the processing high-speed, by providing a common control device, which selects an operating device to transfer data each time when an operation execution command is transferred between the central processing device and plural operating devices. CONSTITUTION:Each time an operation execution command is transferred from a central processing device 1, one of operating devices 3 and 4 which is idle is selected by a selecting circuit of a common control device 2, and operation data is transferred to the selected operating device 3 or 4 through a selecting line. In case of an operation result read command, the designated operating device 3 or 4 is selected, and an operation result read indication is transferred to the designated operating device 3 or 4 through a data bus 107. When the operation result is transferred next through the data bus 107, the common control device 2 passes data to the central processing device 1. Consequently, operating devices 3 and 4 are used efficiently.
JP2943481A 1981-03-03 1981-03-03 Parallel processing system Pending JPS57143670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2943481A JPS57143670A (en) 1981-03-03 1981-03-03 Parallel processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2943481A JPS57143670A (en) 1981-03-03 1981-03-03 Parallel processing system

Publications (1)

Publication Number Publication Date
JPS57143670A true JPS57143670A (en) 1982-09-04

Family

ID=12276024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2943481A Pending JPS57143670A (en) 1981-03-03 1981-03-03 Parallel processing system

Country Status (1)

Country Link
JP (1) JPS57143670A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199437A (en) * 1975-02-27 1976-09-02 Nippon Signal Co Ltd
JPS51144543A (en) * 1975-06-06 1976-12-11 Toshiba Corp Processing system of composite computer system
JPS55154653A (en) * 1979-05-22 1980-12-02 Nec Corp Interruption distributing system to multiprocessor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199437A (en) * 1975-02-27 1976-09-02 Nippon Signal Co Ltd
JPS51144543A (en) * 1975-06-06 1976-12-11 Toshiba Corp Processing system of composite computer system
JPS55154653A (en) * 1979-05-22 1980-12-02 Nec Corp Interruption distributing system to multiprocessor

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