JPS57168331A - Control method for shared input and output bus - Google Patents

Control method for shared input and output bus

Info

Publication number
JPS57168331A
JPS57168331A JP56052416A JP5241681A JPS57168331A JP S57168331 A JPS57168331 A JP S57168331A JP 56052416 A JP56052416 A JP 56052416A JP 5241681 A JP5241681 A JP 5241681A JP S57168331 A JPS57168331 A JP S57168331A
Authority
JP
Japan
Prior art keywords
station
cpu
release
stations
source address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56052416A
Other languages
Japanese (ja)
Other versions
JPS6321944B2 (en
Inventor
Hideo Yanai
Hiroaki Nakanishi
Hiroshi Kobayashi
Yasushi Fukunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56052416A priority Critical patent/JPS57168331A/en
Publication of JPS57168331A publication Critical patent/JPS57168331A/en
Publication of JPS6321944B2 publication Critical patent/JPS6321944B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To release a station from an occupied state, by receiving down information and a release command in the occupied station in the system where one input/output device is shared among plural computers. CONSTITUTION:Source addresses indicating CPUs which occupy stations are stored in stations themselves, and each station compares the source address in a frame, which is transferred through a loop bus 7, with the stored source address of the occupying CPU to perform the control for occupation and release, and the detecting function for CPU down and the function for transmitting a frame, which consists of the source address indicating a down CPU and a command instructing the release of occupation due to this CPU, to all stations simultaneously are given to one station 8 on the loop bus 7; and by the control from this station 8, stations for common I/O which are occupied when CPUs are down are released.
JP56052416A 1981-04-09 1981-04-09 Control method for shared input and output bus Granted JPS57168331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56052416A JPS57168331A (en) 1981-04-09 1981-04-09 Control method for shared input and output bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56052416A JPS57168331A (en) 1981-04-09 1981-04-09 Control method for shared input and output bus

Publications (2)

Publication Number Publication Date
JPS57168331A true JPS57168331A (en) 1982-10-16
JPS6321944B2 JPS6321944B2 (en) 1988-05-10

Family

ID=12914180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56052416A Granted JPS57168331A (en) 1981-04-09 1981-04-09 Control method for shared input and output bus

Country Status (1)

Country Link
JP (1) JPS57168331A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51140537A (en) * 1975-05-30 1976-12-03 Fuji Electric Co Ltd System for establishing priority of terminal devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51140537A (en) * 1975-05-30 1976-12-03 Fuji Electric Co Ltd System for establishing priority of terminal devices

Also Published As

Publication number Publication date
JPS6321944B2 (en) 1988-05-10

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