JPS6423358A - Advance read control system - Google Patents
Advance read control systemInfo
- Publication number
- JPS6423358A JPS6423358A JP17967387A JP17967387A JPS6423358A JP S6423358 A JPS6423358 A JP S6423358A JP 17967387 A JP17967387 A JP 17967387A JP 17967387 A JP17967387 A JP 17967387A JP S6423358 A JPS6423358 A JP S6423358A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- invalid
- advance reading
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To prevent the deterioration of the processing seed of an information processing system by excluding completely the invalid advance reading actions with a channel controller and reducing the invalid load against a main memory. CONSTITUTION:The working of an advance reading control means 100 of a channel controller 1 is stopped when it is detected that a transfer request of data is given to an input/output controller 5b from a main memory 3 while this memory 3 is transferring (200) data to another input/output controller 5a. Therefore the means 100 works to carry out an advance reading action when the data are transferred continuously to the same input/output controller from the memory 3. However, the means 100 does not work when the data are transferred to different input/output controllers from the memory 3. As a result, the invalid advance reading actions are avoided and the reactive load of the memory 3 is reduced. Then the deterioration of the processing speed is prevented for an information processing system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17967387A JPS6423358A (en) | 1987-07-17 | 1987-07-17 | Advance read control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17967387A JPS6423358A (en) | 1987-07-17 | 1987-07-17 | Advance read control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6423358A true JPS6423358A (en) | 1989-01-26 |
Family
ID=16069874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17967387A Pending JPS6423358A (en) | 1987-07-17 | 1987-07-17 | Advance read control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6423358A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6028590U (en) * | 1983-08-02 | 1985-02-26 | 株式会社シマノ | bicycle rear derailleur |
-
1987
- 1987-07-17 JP JP17967387A patent/JPS6423358A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6028590U (en) * | 1983-08-02 | 1985-02-26 | 株式会社シマノ | bicycle rear derailleur |
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