BR8008519A - Ordenacao de memoria de acesso aleatorio (ram)8 estavel em ca, de transistor de efeito de campo (fet) de dispositivo unico - Google Patents

Ordenacao de memoria de acesso aleatorio (ram)8 estavel em ca, de transistor de efeito de campo (fet) de dispositivo unico

Info

Publication number
BR8008519A
BR8008519A BR8008519A BR8008519A BR8008519A BR 8008519 A BR8008519 A BR 8008519A BR 8008519 A BR8008519 A BR 8008519A BR 8008519 A BR8008519 A BR 8008519A BR 8008519 A BR8008519 A BR 8008519A
Authority
BR
Brazil
Prior art keywords
fet
ram
stable
random access
access memory
Prior art date
Application number
BR8008519A
Other languages
English (en)
Inventor
R Scheuerlein
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8008519A publication Critical patent/BR8008519A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
BR8008519A 1979-12-26 1980-12-23 Ordenacao de memoria de acesso aleatorio (ram)8 estavel em ca, de transistor de efeito de campo (fet) de dispositivo unico BR8008519A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/106,641 US4319342A (en) 1979-12-26 1979-12-26 One device field effect transistor (FET) AC stable random access memory (RAM) array

Publications (1)

Publication Number Publication Date
BR8008519A true BR8008519A (pt) 1981-07-21

Family

ID=22312496

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8008519A BR8008519A (pt) 1979-12-26 1980-12-23 Ordenacao de memoria de acesso aleatorio (ram)8 estavel em ca, de transistor de efeito de campo (fet) de dispositivo unico

Country Status (8)

Country Link
US (1) US4319342A (pt)
EP (1) EP0031490B1 (pt)
JP (1) JPS5826830B2 (pt)
AU (1) AU537761B2 (pt)
BR (1) BR8008519A (pt)
CA (1) CA1163714A (pt)
DE (1) DE3072030D1 (pt)
ES (1) ES8202178A1 (pt)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4827448A (en) * 1976-09-13 1989-05-02 Texas Instruments Incorporated Random access memory cell with implanted capacitor region
DE2926417A1 (de) * 1979-06-29 1981-01-22 Siemens Ag Dynamische halbleiterspeicherzelle und verfahren zu ihrer herstellung
US4423490A (en) * 1980-10-27 1983-12-27 Burroughs Corporation JFET Dynamic memory
JPS6059677B2 (ja) * 1981-08-19 1985-12-26 富士通株式会社 半導体記憶装置
JPS594159A (ja) * 1982-06-30 1984-01-10 Mitsubishi Electric Corp 半導体集積回路
US4493056A (en) * 1982-06-30 1985-01-08 International Business Machines Corporation RAM Utilizing offset contact regions for increased storage capacitance
JPS59155955A (ja) * 1983-02-25 1984-09-05 Mitsubishi Electric Corp 半導体記憶装置
JPS59154025U (ja) * 1983-04-04 1984-10-16 ヤンマー農機株式会社 脱穀機の選別装置
JPS59178040U (ja) * 1983-05-17 1984-11-28 ヤンマー農機株式会社 脱穀装置
JPS60109249A (ja) * 1983-11-18 1985-06-14 Hitachi Micro Comput Eng Ltd 多層配線部材
DE3572422D1 (en) * 1984-06-14 1989-09-21 Ibm Dynamic ram cell
US4721987A (en) * 1984-07-03 1988-01-26 Texas Instruments Incorporated Trench capacitor process for high density dynamic RAM
US5170234A (en) * 1984-07-03 1992-12-08 Texas Instruments Incorporated High density dynamic RAM with trench capacitor
USRE33261E (en) * 1984-07-03 1990-07-10 Texas Instruments, Incorporated Trench capacitor for high density dynamic RAM
US5208657A (en) * 1984-08-31 1993-05-04 Texas Instruments Incorporated DRAM Cell with trench capacitor and vertical channel in substrate
US4824793A (en) * 1984-09-27 1989-04-25 Texas Instruments Incorporated Method of making DRAM cell with trench capacitor
US4682201A (en) * 1984-10-19 1987-07-21 California Devices, Inc. Gate array cell
JPH0666442B2 (ja) * 1985-03-08 1994-08-24 三菱電機株式会社 半導体メモリ装置
US5102817A (en) * 1985-03-21 1992-04-07 Texas Instruments Incorporated Vertical DRAM cell and method
JPH0831578B2 (ja) * 1986-06-19 1996-03-27 日本電気株式会社 マスタ−スライス方式のゲ−トアレ−半導体集積回路装置
US4829017A (en) * 1986-09-25 1989-05-09 Texas Instruments Incorporated Method for lubricating a high capacity dram cell
JPS6387763A (ja) * 1987-08-13 1988-04-19 Nec Corp 半導体集積回路メモリ
US5109259A (en) * 1987-09-22 1992-04-28 Texas Instruments Incorporated Multiple DRAM cells in a trench
US5105245A (en) * 1988-06-28 1992-04-14 Texas Instruments Incorporated Trench capacitor DRAM cell with diffused bit lines adjacent to a trench
US5225363A (en) * 1988-06-28 1993-07-06 Texas Instruments Incorporated Trench capacitor DRAM cell and method of manufacture
JP2681285B2 (ja) * 1988-09-19 1997-11-26 富士通株式会社 半導体記憶装置
JPH07109878B2 (ja) * 1988-11-16 1995-11-22 株式会社東芝 半導体記憶装置
JP2974252B2 (ja) * 1989-08-19 1999-11-10 富士通株式会社 半導体記憶装置
KR920007358B1 (ko) * 1990-03-28 1992-08-31 금성일렉트론 주식회사 고집적 메모리 셀 및 코아 어레이 구조
JP2564695B2 (ja) * 1990-09-14 1996-12-18 富士通株式会社 半導体記憶装置
JP3302796B2 (ja) * 1992-09-22 2002-07-15 株式会社東芝 半導体記憶装置
US5485572A (en) * 1994-04-26 1996-01-16 Unisys Corporation Response stack state validation check
US6903437B1 (en) * 2004-01-07 2005-06-07 Micron Technology, Inc. Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods
US7977661B2 (en) * 2007-06-07 2011-07-12 Qimonda Ag Memory having shared storage material
US7821039B2 (en) * 2008-06-23 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Layout architecture for improving circuit performance

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
JPS5539073B2 (pt) * 1974-12-25 1980-10-08
JPS5853512B2 (ja) * 1976-02-13 1983-11-29 株式会社東芝 半導体記憶装置の製造方法
US4103347A (en) * 1976-10-29 1978-07-25 Texas Instruments Incorporated Zig-zag sps ccd memory
DE2743619A1 (de) * 1977-09-28 1979-03-29 Siemens Ag Halbleiter-speicherelement und verfahren zu seiner herstellung
US4219834A (en) * 1977-11-11 1980-08-26 International Business Machines Corporation One-device monolithic random access memory and method of fabricating same

Also Published As

Publication number Publication date
DE3072030D1 (en) 1987-10-22
EP0031490A3 (en) 1983-05-25
EP0031490B1 (en) 1987-09-16
JPS5826830B2 (ja) 1983-06-06
JPS5694769A (en) 1981-07-31
CA1163714A (en) 1984-03-13
US4319342A (en) 1982-03-09
AU6410280A (en) 1981-08-20
EP0031490A2 (en) 1981-07-08
ES498133A0 (es) 1982-01-01
AU537761B2 (en) 1984-07-12
ES8202178A1 (es) 1982-01-01

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Legal Events

Date Code Title Description
MK Patent expired

Effective date: 19951223