IT7826101A0 - Circuito fet particolarmente atto all'impiego in matrici logiche programmate. - Google Patents

Circuito fet particolarmente atto all'impiego in matrici logiche programmate.

Info

Publication number
IT7826101A0
IT7826101A0 IT7826101A IT2610178A IT7826101A0 IT 7826101 A0 IT7826101 A0 IT 7826101A0 IT 7826101 A IT7826101 A IT 7826101A IT 2610178 A IT2610178 A IT 2610178A IT 7826101 A0 IT7826101 A0 IT 7826101A0
Authority
IT
Italy
Prior art keywords
matrixes
particularly suitable
programmed logic
fet circuit
circuit particularly
Prior art date
Application number
IT7826101A
Other languages
English (en)
Other versions
IT1110487B (it
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT7826101A0 publication Critical patent/IT7826101A0/it
Application granted granted Critical
Publication of IT1110487B publication Critical patent/IT1110487B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT26101/78A 1977-08-31 1978-07-26 Circuito fet particolarmente atto all impiego in matrici logiche programmate IT1110487B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/829,417 US4140921A (en) 1977-08-31 1977-08-31 Generalized performance power optimized PLA circuits

Publications (2)

Publication Number Publication Date
IT7826101A0 true IT7826101A0 (it) 1978-07-26
IT1110487B IT1110487B (it) 1985-12-23

Family

ID=25254488

Family Applications (1)

Application Number Title Priority Date Filing Date
IT26101/78A IT1110487B (it) 1977-08-31 1978-07-26 Circuito fet particolarmente atto all impiego in matrici logiche programmate

Country Status (6)

Country Link
US (1) US4140921A (it)
JP (1) JPS5437546A (it)
DE (1) DE2837574A1 (it)
FR (1) FR2402351A1 (it)
GB (1) GB1570336A (it)
IT (1) IT1110487B (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295064A (en) * 1978-06-30 1981-10-13 International Business Machines Corporation Logic and array logic driving circuits
US4233667A (en) * 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4500800A (en) * 1982-08-30 1985-02-19 International Business Machines Corporation Logic performing cell for use in array structures
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
JP2859234B2 (ja) * 1996-12-26 1999-02-17 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置
US6094726A (en) * 1998-02-05 2000-07-25 George S. Sheng Digital signal processor using a reconfigurable array of macrocells
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
US3993919A (en) * 1975-06-27 1976-11-23 Ibm Corporation Programmable latch and other circuits for logic arrays
US4016431A (en) * 1975-12-31 1977-04-05 International Business Machines Corporation Optimal driver for LSI

Also Published As

Publication number Publication date
FR2402351A1 (fr) 1979-03-30
FR2402351B1 (it) 1981-07-24
GB1570336A (en) 1980-06-25
IT1110487B (it) 1985-12-23
US4140921A (en) 1979-02-20
JPS5437546A (en) 1979-03-20
DE2837574A1 (de) 1979-03-08

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