FR2402351A1 - Reseau logique programme a rapport puissance-performance optimise - Google Patents

Reseau logique programme a rapport puissance-performance optimise

Info

Publication number
FR2402351A1
FR2402351A1 FR7822193A FR7822193A FR2402351A1 FR 2402351 A1 FR2402351 A1 FR 2402351A1 FR 7822193 A FR7822193 A FR 7822193A FR 7822193 A FR7822193 A FR 7822193A FR 2402351 A1 FR2402351 A1 FR 2402351A1
Authority
FR
France
Prior art keywords
programmed logic
logic network
circuits
performance ratio
optimized power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7822193A
Other languages
English (en)
Other versions
FR2402351B1 (fr
Inventor
Peruvemba S Balasubramanian
Stephen B Greenspan
Krishnamurthi Venkataraman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2402351A1 publication Critical patent/FR2402351A1/fr
Application granted granted Critical
Publication of FR2402351B1 publication Critical patent/FR2402351B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Réseau logique programmé à rapport puissance-performance optimisé. Un réseau de circuits parallèles de charges à transistors à effet de champ sur une microplaquette de circuits intégrés est conçu pour avoir les retards de signaux respectifs de ces circuits rendus égaux lorsque leurs capacités de noeud sont différentes ou alternativement pour avoir les retards de signaux de ces circuits établis à différentes valeurs pour satisfaire aux besoins d'un circuit suivant, en ajustant la capacité d'entraînement de courant d'un circuit de commande de chaque circuit pour obtenir les différents retards requis. Peut être utilisé avec tout type de réseau logique programmé.
FR7822193A 1977-08-31 1978-07-21 Reseau logique programme a rapport puissance-performance optimise Granted FR2402351A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/829,417 US4140921A (en) 1977-08-31 1977-08-31 Generalized performance power optimized PLA circuits

Publications (2)

Publication Number Publication Date
FR2402351A1 true FR2402351A1 (fr) 1979-03-30
FR2402351B1 FR2402351B1 (fr) 1981-07-24

Family

ID=25254488

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7822193A Granted FR2402351A1 (fr) 1977-08-31 1978-07-21 Reseau logique programme a rapport puissance-performance optimise

Country Status (6)

Country Link
US (1) US4140921A (fr)
JP (1) JPS5437546A (fr)
DE (1) DE2837574A1 (fr)
FR (1) FR2402351A1 (fr)
GB (1) GB1570336A (fr)
IT (1) IT1110487B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0105088A2 (fr) * 1982-08-30 1984-04-11 International Business Machines Corporation Circuit pour accélérer les transferts de charge dans les réseaux logiques programmables

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295064A (en) * 1978-06-30 1981-10-13 International Business Machines Corporation Logic and array logic driving circuits
US4233667A (en) * 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
JP2859234B2 (ja) * 1996-12-26 1999-02-17 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置
US6094726A (en) * 1998-02-05 2000-07-25 George S. Sheng Digital signal processor using a reconfigurable array of macrocells
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile
US3993919A (en) * 1975-06-27 1976-11-23 Ibm Corporation Programmable latch and other circuits for logic arrays
US4016431A (en) * 1975-12-31 1977-04-05 International Business Machines Corporation Optimal driver for LSI

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/75 *
EXBK/76 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0105088A2 (fr) * 1982-08-30 1984-04-11 International Business Machines Corporation Circuit pour accélérer les transferts de charge dans les réseaux logiques programmables
EP0105088A3 (en) * 1982-08-30 1985-03-13 International Business Machines Corporation Circuit for speeding up transfers of charges in programmable logic array structures

Also Published As

Publication number Publication date
JPS5437546A (en) 1979-03-20
DE2837574A1 (de) 1979-03-08
GB1570336A (en) 1980-06-25
FR2402351B1 (fr) 1981-07-24
IT7826101A0 (it) 1978-07-26
US4140921A (en) 1979-02-20
IT1110487B (it) 1985-12-23

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Legal Events

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