BR112018075661A2 - gerenciamento de atualização para memória flash - Google Patents

gerenciamento de atualização para memória flash

Info

Publication number
BR112018075661A2
BR112018075661A2 BR112018075661-0A BR112018075661A BR112018075661A2 BR 112018075661 A2 BR112018075661 A2 BR 112018075661A2 BR 112018075661 A BR112018075661 A BR 112018075661A BR 112018075661 A2 BR112018075661 A2 BR 112018075661A2
Authority
BR
Brazil
Prior art keywords
update
flash memory
memory
host
destination
Prior art date
Application number
BR112018075661-0A
Other languages
English (en)
Inventor
Shin Hyunsuk
Hardacker Robert
Vuong Hung
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112018075661A2 publication Critical patent/BR112018075661A2/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Dram (AREA)

Abstract

sistemas e métodos para uma atualização de dados de uma memória flash dirigida por um hospedeiro incluem registros fornecidos na memória flash para armazenar diversas configurações relacionadas a operações de atualização, como, quando iniciar/parar a atualização, segmentar partições na memória, início/fim de destino de intervalos de endereços para atualização, algoritmos de atualização, requisitos de taxa de atualização, etc. um hospedeiro pode controlar as diversas configurações de atualização de iniciar/parar, partições de destino na memória, intervalos de endereços de início/fim para atualização, algoritmos de atualização, através dos registradores correspondentes; e a memória flash pode controlar vários valores relacionados aos requisitos de taxa de atualização através de registros correspondentes. dessa maneira, uma plataforma ou interface padrão é fornecida dentro da memória flash para operações de atualização.
BR112018075661-0A 2016-06-20 2017-06-07 gerenciamento de atualização para memória flash BR112018075661A2 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662352393P 2016-06-20 2016-06-20
US62/352,393 2016-06-20
US15/615,827 US10199115B2 (en) 2016-06-20 2017-06-06 Managing refresh for flash memory
US15/615,827 2017-06-06
PCT/US2017/036397 WO2017222818A1 (en) 2016-06-20 2017-06-07 Managing refresh for flash memory

Publications (1)

Publication Number Publication Date
BR112018075661A2 true BR112018075661A2 (pt) 2019-04-09

Family

ID=60659776

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018075661-0A BR112018075661A2 (pt) 2016-06-20 2017-06-07 gerenciamento de atualização para memória flash

Country Status (9)

Country Link
US (2) US10199115B2 (pt)
EP (2) EP3594952A1 (pt)
JP (2) JP7213690B2 (pt)
KR (1) KR102508868B1 (pt)
CN (2) CN109328386B (pt)
BR (1) BR112018075661A2 (pt)
CA (1) CA3026804C (pt)
ES (1) ES2874279T3 (pt)
WO (1) WO2017222818A1 (pt)

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Also Published As

Publication number Publication date
US10199115B2 (en) 2019-02-05
JP2022070884A (ja) 2022-05-13
CN109328386B (zh) 2022-04-29
US20170365352A1 (en) 2017-12-21
CN114758711A (zh) 2022-07-15
CA3026804A1 (en) 2017-12-28
JP7348325B2 (ja) 2023-09-20
CN109328386A (zh) 2019-02-12
US10360987B2 (en) 2019-07-23
US20190066811A1 (en) 2019-02-28
ES2874279T3 (es) 2021-11-04
EP3594952A1 (en) 2020-01-15
EP3472840B1 (en) 2021-02-24
CA3026804C (en) 2023-09-05
EP3472840A1 (en) 2019-04-24
KR20190016968A (ko) 2019-02-19
JP2019522284A (ja) 2019-08-08
KR102508868B1 (ko) 2023-03-09
WO2017222818A1 (en) 2017-12-28
JP7213690B2 (ja) 2023-01-27

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B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]
B12B Appeal against refusal [chapter 12.2 patent gazette]