BR112016006103A2 - conversor analógico para digital de aproximação sucessiva sequenciada - Google Patents
conversor analógico para digital de aproximação sucessiva sequenciadaInfo
- Publication number
- BR112016006103A2 BR112016006103A2 BR112016006103A BR112016006103A BR112016006103A2 BR 112016006103 A2 BR112016006103 A2 BR 112016006103A2 BR 112016006103 A BR112016006103 A BR 112016006103A BR 112016006103 A BR112016006103 A BR 112016006103A BR 112016006103 A2 BR112016006103 A2 BR 112016006103A2
- Authority
- BR
- Brazil
- Prior art keywords
- stage
- signal
- significant bits
- unit configured
- analog
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
- H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
- H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Power Engineering (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/031,512 US9059730B2 (en) | 2013-09-19 | 2013-09-19 | Pipelined successive approximation analog-to-digital converter |
| PCT/US2014/055312 WO2015041937A1 (en) | 2013-09-19 | 2014-09-12 | Pipelined successive approximation analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BR112016006103A2 true BR112016006103A2 (pt) | 2017-08-01 |
Family
ID=51589557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR112016006103A BR112016006103A2 (pt) | 2013-09-19 | 2014-09-12 | conversor analógico para digital de aproximação sucessiva sequenciada |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9059730B2 (https=) |
| EP (1) | EP3047574A1 (https=) |
| JP (1) | JP2016531532A (https=) |
| KR (1) | KR20160058140A (https=) |
| CN (1) | CN105556847A (https=) |
| BR (1) | BR112016006103A2 (https=) |
| WO (1) | WO2015041937A1 (https=) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9455737B1 (en) | 2015-09-25 | 2016-09-27 | Qualcomm Incorporated | Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer |
| JP2017135616A (ja) * | 2016-01-28 | 2017-08-03 | 日本放送協会 | アナログ・デジタル変換回路 |
| US9705520B1 (en) | 2016-09-08 | 2017-07-11 | Stmicroelectronics International N.V. | Circuit and method for generating reference signals for hybrid analog-to-digital convertors |
| US9973202B2 (en) * | 2016-09-20 | 2018-05-15 | Kabushiki Kaisha Toshiba | Successive approximation register analog-to-digital converter |
| US9647740B1 (en) | 2016-10-25 | 2017-05-09 | Motorola Mobility Llc | Proximal user detection with a complex measurement receiver |
| EP3334047B1 (en) * | 2016-12-08 | 2021-04-21 | Stichting IMEC Nederland | A method of gain calibration in a two-stage pipelined successive approximation register analog-to-digital converter and a two-stage pipelined successive approximation register analog-to-digital converter |
| EP3334050A1 (en) * | 2016-12-08 | 2018-06-13 | Stichting IMEC Nederland | A method of offset calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter |
| EP3334049B1 (en) * | 2016-12-08 | 2021-04-21 | Stichting IMEC Nederland | A method of digital-to-analog converter mismatch calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter |
| US11018668B2 (en) * | 2017-11-14 | 2021-05-25 | Shuze Zhao | Characterization of power delivery network in field programmable gate arrays or digital integrated circuits |
| CN108880546B (zh) * | 2018-07-09 | 2021-04-30 | 电子科技大学 | 一种应用于逐次逼近模数转换器的电容校正方法 |
| US10763886B1 (en) * | 2019-08-20 | 2020-09-01 | Texas Instruments Incorporated | Dithering and calibration technique in multi-stage ADC |
| KR102744050B1 (ko) | 2020-02-06 | 2024-12-17 | 삼성전자주식회사 | 아날로그 디지털 변환 장치 및 아날로그 디지털 변환 방법 |
| US12261619B2 (en) | 2022-12-20 | 2025-03-25 | International Business Machines Corporation | Stochastic rounding switched capacitor computation cores useful for efficient deep learning inference |
| US12506487B2 (en) * | 2023-05-18 | 2025-12-23 | Realtek Semiconductor Corporation | Compensation circuit and compensation method for successive-approximation register (SAR) analog-to-digital converter (ADC) |
| US20250183905A1 (en) * | 2023-12-05 | 2025-06-05 | Arctic Semiconductor Corporation | Multi-stage pipeline sar analog-to-digital converter (adc) |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151700A (en) * | 1989-08-04 | 1992-09-29 | Matsushita Electric Industrial Co., Ltd. | Serial-parallel type a/d converter |
| JP3182444B2 (ja) * | 1992-03-04 | 2001-07-03 | 株式会社日立製作所 | Ad変換器 |
| JPH0774635A (ja) * | 1993-07-02 | 1995-03-17 | Mitsubishi Electric Corp | アナログ・デジタル変換装置 |
| JP3510306B2 (ja) * | 1994-01-31 | 2004-03-29 | ソニー株式会社 | アナログデイジタル変換回路 |
| US5771012A (en) | 1996-09-11 | 1998-06-23 | Harris Corporation | Integrated circuit analog-to-digital converter and associated calibration method and apparatus |
| US6124818A (en) | 1998-10-21 | 2000-09-26 | Linear Technology Corporation | Pipelined successive approximation analog-to-digital converters |
| US6489914B1 (en) | 2001-12-04 | 2002-12-03 | Motorola, Inc. | RSD analog to digital converter |
| JP5072607B2 (ja) * | 2008-01-07 | 2012-11-14 | 株式会社東芝 | A/d変換装置 |
| DE102009004564B4 (de) | 2009-01-14 | 2013-08-22 | Texas Instruments Deutschland Gmbh | ADC mit energiesparender Abtastung |
| KR101381250B1 (ko) | 2010-09-15 | 2014-04-04 | 한국전자통신연구원 | 아날로그 디지털 변환 장치 및 그것의 기준 전압 제어 방법 |
| KR101678842B1 (ko) | 2010-10-22 | 2016-11-23 | 삼성전자주식회사 | 아날로그 디지털 컨버터 및 이를 포함하는 이미지 센서 |
| CN102571094B (zh) * | 2010-12-10 | 2014-11-26 | 乐金显示有限公司 | 逐次逼近寄存器模数转换器以及利用其的模数转换方法 |
| US8471751B2 (en) * | 2011-06-30 | 2013-06-25 | Intel Corporation | Two-stage analog-to-digital converter using SAR and TDC |
| US8643529B2 (en) * | 2012-06-05 | 2014-02-04 | Himax Technologies Limited | SAR assisted pipelined ADC and method for operating the same |
| US8614638B1 (en) * | 2012-06-19 | 2013-12-24 | Qualcomm Incorporated | Hybrid successive approximation analog-to-digital converter |
| JP6111662B2 (ja) * | 2012-12-28 | 2017-04-12 | 富士通株式会社 | アナログ/デジタル変換器 |
| CN103281080B (zh) * | 2013-04-25 | 2017-03-15 | 清华大学 | 一种流水线结构模数转换器的前端电路及其时序控制方法 |
-
2013
- 2013-09-19 US US14/031,512 patent/US9059730B2/en not_active Expired - Fee Related
-
2014
- 2014-09-12 BR BR112016006103A patent/BR112016006103A2/pt not_active Application Discontinuation
- 2014-09-12 JP JP2016543936A patent/JP2016531532A/ja not_active Ceased
- 2014-09-12 KR KR1020167009667A patent/KR20160058140A/ko not_active Withdrawn
- 2014-09-12 CN CN201480051723.2A patent/CN105556847A/zh active Pending
- 2014-09-12 WO PCT/US2014/055312 patent/WO2015041937A1/en not_active Ceased
- 2014-09-12 EP EP14772044.5A patent/EP3047574A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| WO2015041937A1 (en) | 2015-03-26 |
| EP3047574A1 (en) | 2016-07-27 |
| US20150077280A1 (en) | 2015-03-19 |
| US9059730B2 (en) | 2015-06-16 |
| JP2016531532A (ja) | 2016-10-06 |
| KR20160058140A (ko) | 2016-05-24 |
| CN105556847A (zh) | 2016-05-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
| B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
| B11B | Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements |