BR112017018231A2 - conversor tempo-digital em circuito travado por fase - Google Patents

conversor tempo-digital em circuito travado por fase

Info

Publication number
BR112017018231A2
BR112017018231A2 BR112017018231-9A BR112017018231A BR112017018231A2 BR 112017018231 A2 BR112017018231 A2 BR 112017018231A2 BR 112017018231 A BR112017018231 A BR 112017018231A BR 112017018231 A2 BR112017018231 A2 BR 112017018231A2
Authority
BR
Brazil
Prior art keywords
delay
time
chain
retarder
phase
Prior art date
Application number
BR112017018231-9A
Other languages
English (en)
Chinese (zh)
Inventor
Zhou Shenghua
Song Ran
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of BR112017018231A2 publication Critical patent/BR112017018231A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Abstract

a presente invenção refere-se a um conversor tempo-digital em um circuito travado por fase, de modo que a precisão de travamento por fase possa ser aprimorada. o conversor tempo-digital inclui uma unidade de atraso (301, 601) em que um primeiro sinal é inserido e uma unidade de amostragem (302, 602) na qual um segundo sinal é inserido, em que a unidade de atraso inclui uma primeira cadeia de atraso (3011, 6011), uma segunda cadeia de atraso (3012, 6012) e uma terceira cadeia de atraso (3013, 6013) que são conectadas em série em sequência, e é configurado para atrasar o primeiro sinal, em que a primeira cadeia de atraso inclui pelo menos um primeiro retardador, a segunda cadeia de atraso inclui pelo menos três segundos retardadores, a terceira cadeia de atraso inclui pelo menos um terceiro retardador, e a duração do atraso do primeiro retardador e a duração do atraso do terceiro retardador são maiores que a duração do atraso do segundo retardador; e a unidade de amostragem é configurada para: realizar a amostragem em sinais de saída de primeiros retardadores na primeira cadeia de atraso, segundos retardadores na segunda cadeia de atraso, e terceiros retardadores na terceira cadeia de atraso na unidade de atraso em um ponto de tempo predefinido do segundo sinal, e sinais amostrados de saída.
BR112017018231-9A 2015-03-25 2015-11-27 conversor tempo-digital em circuito travado por fase BR112017018231A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201510134242.4A CN104716955B (zh) 2015-03-25 2015-03-25 一种锁相环中的时间数字转换器
CN201510134242.4 2015-03-25
PCT/CN2015/095807 WO2016150182A1 (zh) 2015-03-25 2015-11-27 一种锁相环中的时间数字转换器

Publications (1)

Publication Number Publication Date
BR112017018231A2 true BR112017018231A2 (pt) 2018-04-17

Family

ID=53415974

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017018231-9A BR112017018231A2 (pt) 2015-03-25 2015-11-27 conversor tempo-digital em circuito travado por fase

Country Status (5)

Country Link
US (1) US10673445B2 (pt)
EP (1) EP3249816A4 (pt)
CN (2) CN109379077A (pt)
BR (1) BR112017018231A2 (pt)
WO (1) WO2016150182A1 (pt)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109379077A (zh) * 2015-03-25 2019-02-22 华为技术有限公司 一种锁相环中的时间数字转换器
KR20170140150A (ko) 2016-05-17 2017-12-20 후아웨이 테크놀러지 컴퍼니 리미티드 시간-디지털 변환기 및 디지털 위상 로킹 루프
US11079723B2 (en) 2018-02-06 2021-08-03 Integrated Device Technology, Inc. Apparatus and methods for automatic time measurements
CN108566180A (zh) * 2018-05-04 2018-09-21 中国科学技术大学 一种产生两路延时的单延时链电路

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US5945862A (en) * 1997-07-31 1999-08-31 Rambus Incorporated Circuitry for the delay adjustment of a clock signal
JP4114291B2 (ja) * 1999-01-20 2008-07-09 ソニー株式会社 半導体装置およびその構成方法
KR100311046B1 (ko) * 1999-05-15 2001-11-02 윤종용 시간/디지털 변환기, 이를 이용하는 동기 회로 및 동기 방법
GB2363009B (en) * 2000-05-31 2004-05-05 Mitel Corp Reduced jitter phase lock loop using a technique multi-stage digital delay line
KR100400041B1 (ko) * 2001-04-20 2003-09-29 삼성전자주식회사 정밀한 위상 조절이 가능한 지연 동기 루프 및 위상 조절방법
US6868047B2 (en) * 2001-12-12 2005-03-15 Teradyne, Inc. Compact ATE with time stamp system
US7427940B2 (en) * 2006-12-29 2008-09-23 Texas Instruments Incorporated Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, SOC including such converter and method of phase detection for use in synthesizing a clock signal
US7564284B2 (en) 2007-03-26 2009-07-21 Infineon Technologies Ag Time delay circuit and time to digital converter
US8219343B2 (en) * 2008-04-24 2012-07-10 Realtek Semiconductor Corp. Method and apparatus for calibrating a delay chain
TWI373917B (en) * 2008-05-09 2012-10-01 Mediatek Inc Frequency divider, frequency dividing method thereof, and phase locked loop utilizing the frequency divider
TWI364169B (en) * 2008-12-09 2012-05-11 Sunplus Technology Co Ltd All digital phase locked loop circuit
CN101504861A (zh) * 2009-03-16 2009-08-12 东南大学 全数字延时锁定环电路
GB201003030D0 (en) * 2010-02-23 2010-04-07 Icera Inc Digital frequency locked loop
CN103684437B (zh) * 2013-02-04 2016-08-10 中国科学院电子学研究所 延时链控制码自适应的快速延时锁定环路
CN103338037B (zh) * 2013-06-19 2016-11-02 华为技术有限公司 一种锁相环中时钟信号转数字信号的方法和装置
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CN103684438B (zh) * 2013-11-25 2016-06-08 龙芯中科技术有限公司 延迟锁相环
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CN109379077A (zh) * 2015-03-25 2019-02-22 华为技术有限公司 一种锁相环中的时间数字转换器

Also Published As

Publication number Publication date
CN109379077A (zh) 2019-02-22
US20180013437A1 (en) 2018-01-11
CN104716955B (zh) 2018-10-02
CN104716955A (zh) 2015-06-17
WO2016150182A1 (zh) 2016-09-29
EP3249816A1 (en) 2017-11-29
EP3249816A4 (en) 2018-03-07
US10673445B2 (en) 2020-06-02

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2698 DE 20-09-2022 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.