BR112015027965A2 - Técnica de aumento de taxa de transferência de link de dados síncrono baseada em ciclo de trabalho de sinal de dados e modulação/desmodulação de fase - Google Patents

Técnica de aumento de taxa de transferência de link de dados síncrono baseada em ciclo de trabalho de sinal de dados e modulação/desmodulação de fase

Info

Publication number
BR112015027965A2
BR112015027965A2 BR112015027965A BR112015027965A BR112015027965A2 BR 112015027965 A2 BR112015027965 A2 BR 112015027965A2 BR 112015027965 A BR112015027965 A BR 112015027965A BR 112015027965 A BR112015027965 A BR 112015027965A BR 112015027965 A2 BR112015027965 A2 BR 112015027965A2
Authority
BR
Brazil
Prior art keywords
demodulation
duty cycle
phase modulation
technique based
data link
Prior art date
Application number
BR112015027965A
Other languages
English (en)
Inventor
T Chun Dexter
J Mishra Lalan
Datta Animesh
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112015027965A2 publication Critical patent/BR112015027965A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902—Pulse width modulation; Pulse position modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

Abstract

TÉCNICA DE AUMENTO DE TAXA DE TRANSFERÊNCIA DE LINK DE DADOS SÍNCRONO BASEADA EM CICLO DE TRABALHO DE SINAL DE DADOS E MODULAÇÃO/DESMODULAÇÃO DE FASE. A presente invenção se refere à técnica de aumento de taxa de transferência de link de dados síncrono baseada em ciclo de trabalho de sinal de dados e modulação/desmodulação de fase. Um método inclui recebimento de bits múltiplos a serem transmitidos, codificação dos bits múltiplos para gerar um sinal de multi-bit que representa os bits múltiplos e transmissão, através de uma interface síncrona, do sinal de multi-bit durante um período de tempo que corresponde a uma metade de um ciclo de um sinal de sincronização.
BR112015027965A 2013-05-06 2014-04-23 Técnica de aumento de taxa de transferência de link de dados síncrono baseada em ciclo de trabalho de sinal de dados e modulação/desmodulação de fase BR112015027965A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/887,846 US9875209B2 (en) 2013-05-06 2013-05-06 Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation
PCT/US2014/035075 WO2014182448A2 (en) 2013-05-06 2014-04-23 Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation

Publications (1)

Publication Number Publication Date
BR112015027965A2 true BR112015027965A2 (pt) 2017-09-05

Family

ID=50841966

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015027965A BR112015027965A2 (pt) 2013-05-06 2014-04-23 Técnica de aumento de taxa de transferência de link de dados síncrono baseada em ciclo de trabalho de sinal de dados e modulação/desmodulação de fase

Country Status (7)

Country Link
US (1) US9875209B2 (pt)
EP (1) EP2995051B1 (pt)
JP (1) JP2016518794A (pt)
KR (1) KR20160005083A (pt)
CN (1) CN105191243B (pt)
BR (1) BR112015027965A2 (pt)
WO (1) WO2014182448A2 (pt)

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Also Published As

Publication number Publication date
CN105191243B (zh) 2018-11-09
US20140330994A1 (en) 2014-11-06
WO2014182448A3 (en) 2014-12-24
EP2995051A2 (en) 2016-03-16
EP2995051B1 (en) 2018-09-12
CN105191243A (zh) 2015-12-23
WO2014182448A2 (en) 2014-11-13
JP2016518794A (ja) 2016-06-23
US9875209B2 (en) 2018-01-23
KR20160005083A (ko) 2016-01-13

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

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B350 Update of information on the portal [chapter 15.35 patent gazette]