BR112018004159A2 - Recuperação de dados de relógio multifásico para uma interface trifásica - Google Patents
Recuperação de dados de relógio multifásico para uma interface trifásicaInfo
- Publication number
- BR112018004159A2 BR112018004159A2 BR112018004159A BR112018004159A BR112018004159A2 BR 112018004159 A2 BR112018004159 A2 BR 112018004159A2 BR 112018004159 A BR112018004159 A BR 112018004159A BR 112018004159 A BR112018004159 A BR 112018004159A BR 112018004159 A2 BR112018004159 A2 BR 112018004159A2
- Authority
- BR
- Brazil
- Prior art keywords
- data recovery
- clock data
- phase interface
- multiphase clock
- multiphase
- Prior art date
Links
- 238000011084 recovery Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0037—Delay of clock signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/842,644 US9496879B1 (en) | 2015-09-01 | 2015-09-01 | Multiphase clock data recovery for a 3-phase interface |
| US14/842,644 | 2015-09-01 | ||
| PCT/US2016/046211 WO2017039985A1 (en) | 2015-09-01 | 2016-08-09 | Multiphase clock data recovery for a 3-phase interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| BR112018004159A2 true BR112018004159A2 (pt) | 2018-10-02 |
| BR112018004159B1 BR112018004159B1 (pt) | 2023-12-05 |
Family
ID=56694265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR112018004159-9A BR112018004159B1 (pt) | 2015-09-01 | 2016-08-09 | Recuperação de dados de relógio multifásico para uma interface trifásica |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US9496879B1 (pt) |
| EP (1) | EP3345334B1 (pt) |
| JP (1) | JP6876681B2 (pt) |
| KR (1) | KR102522742B1 (pt) |
| CN (1) | CN107925563B (pt) |
| BR (1) | BR112018004159B1 (pt) |
| CA (1) | CA2992751C (pt) |
| ES (1) | ES2777373T3 (pt) |
| TW (1) | TWI720008B (pt) |
| WO (1) | WO2017039985A1 (pt) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8064535B2 (en) | 2007-03-02 | 2011-11-22 | Qualcomm Incorporated | Three phase and polarity encoded serial interface |
| US9231790B2 (en) * | 2007-03-02 | 2016-01-05 | Qualcomm Incorporated | N-phase phase and polarity encoded serial interface |
| US9711041B2 (en) | 2012-03-16 | 2017-07-18 | Qualcomm Incorporated | N-phase polarity data transfer |
| KR20170008076A (ko) * | 2015-07-13 | 2017-01-23 | 에스케이하이닉스 주식회사 | 고속 통신을 위한 인터페이스 회로 및 이를 포함하는 시스템 |
| US9485080B1 (en) * | 2015-09-01 | 2016-11-01 | Qualcomm Incorporated | Multiphase clock data recovery circuit calibration |
| US10742390B2 (en) * | 2016-07-13 | 2020-08-11 | Novatek Microelectronics Corp. | Method of improving clock recovery and related device |
| US10419246B2 (en) * | 2016-08-31 | 2019-09-17 | Qualcomm Incorporated | C-PHY training pattern for adaptive equalization, adaptive edge tracking and delay calibration |
| US10284361B2 (en) * | 2017-05-05 | 2019-05-07 | Mediatek Inc. | Channel skew calibration method and associated receiver and system |
| KR101899247B1 (ko) * | 2017-05-31 | 2018-09-14 | 한양대학교 산학협력단 | 동시 스위칭 잡음을 제거하는 송신기 및 이에 있어서 데이터 전송 방법 |
| KR102401996B1 (ko) | 2018-05-28 | 2022-05-24 | 삼성전자주식회사 | 타이밍 조절이 가능한 고속 멀티 레벨 신호 수신기를 포함하는 반도체 장치 및 상기 수신기를 포함하는 반도체 테스트 장치 |
| US10469214B1 (en) * | 2018-12-13 | 2019-11-05 | Intel Corporation | Clock recovery circuit and method of operating same |
| US10581587B1 (en) * | 2019-04-29 | 2020-03-03 | Advanced Micro Devices, Inc. | Deskewing method for a physical layer interface on a multi-chip module |
| US11095425B2 (en) * | 2019-10-25 | 2021-08-17 | Qualcomm Incorporated | Small loop delay clock and data recovery block for high-speed next generation C-PHY |
| US11038666B1 (en) | 2019-12-11 | 2021-06-15 | Qualcomm Incorporated | Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces |
| KR20210088808A (ko) | 2020-01-06 | 2021-07-15 | 삼성전자주식회사 | 전자 장치 및 전자 장치의 동작 방법 |
| KR20210088807A (ko) * | 2020-01-06 | 2021-07-15 | 삼성전자주식회사 | 전자 장치 및 전자 장치의 동작 방법 |
| US11031939B1 (en) * | 2020-03-19 | 2021-06-08 | Mellanox Technologies, Ltd. | Phase detector command propagation between lanes in MCM USR serdes |
| US11349445B2 (en) * | 2020-09-10 | 2022-05-31 | Qualcomm Incorporated | Compensation of common mode voltage drop of sensing amplifier output due to decision feedback equalizer (DFE) taps |
| KR102265187B1 (ko) * | 2021-02-08 | 2021-06-16 | 슈가스 주식회사 | 클럭 복구 회로 |
| JP2022146532A (ja) | 2021-03-22 | 2022-10-05 | キオクシア株式会社 | メモリシステム及び遅延制御方法 |
| US11520729B2 (en) | 2021-05-04 | 2022-12-06 | Qualcomm Incorporated | I2C bus architecture using shared clock and dedicated data lines |
| US11545980B1 (en) | 2021-09-08 | 2023-01-03 | Qualcomm Incorporated | Clock and data recovery for multi-phase, multi-level encoding |
| CN113886300B (zh) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种总线接口的时钟数据自适应恢复系统及芯片 |
| US11956342B2 (en) * | 2021-12-27 | 2024-04-09 | Nvidia Corporation | Reliable link management for a high-speed signaling interconnect |
| CN114298075B (zh) * | 2021-12-30 | 2024-02-06 | 江苏集萃智能集成电路设计技术研究所有限公司 | 基于mcu的超高频国标阅读器基带解码方法 |
| US11967964B1 (en) * | 2022-03-31 | 2024-04-23 | Amazon Technologies, Inc. | Clock synchronization in a network using a distributed pulse signal |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5771264A (en) * | 1996-08-29 | 1998-06-23 | Altera Corporation | Digital delay lock loop for clock signal frequency multiplication |
| US5796392A (en) * | 1997-02-24 | 1998-08-18 | Paradise Electronics, Inc. | Method and apparatus for clock recovery in a digital display unit |
| JP3523069B2 (ja) * | 1998-06-30 | 2004-04-26 | 株式会社東芝 | 遅延型位相同期回路 |
| DE10202879B4 (de) * | 2002-01-25 | 2004-01-29 | Infineon Technologies Ag | DLL-(Delay-Locked-Loop)Schaltung |
| DE102004014695B4 (de) * | 2003-03-26 | 2007-08-16 | Infineon Technologies Ag | Takt- und Datenwiedergewinnungseinheit |
| KR100570632B1 (ko) * | 2004-07-06 | 2006-04-12 | 삼성전자주식회사 | 클록복원회로 및 방법과 이를 이용한 고속 데이터송수신회로 |
| WO2007125963A1 (ja) * | 2006-04-27 | 2007-11-08 | Panasonic Corporation | 多重差動伝送システム |
| US7742551B2 (en) | 2006-07-31 | 2010-06-22 | Mosaid Technologies Incorporated | Pulse counter with clock edge recovery |
| US9711041B2 (en) * | 2012-03-16 | 2017-07-18 | Qualcomm Incorporated | N-phase polarity data transfer |
| US8649460B2 (en) * | 2007-06-05 | 2014-02-11 | Rambus Inc. | Techniques for multi-wire encoding with an embedded clock |
| US7622969B2 (en) * | 2007-12-18 | 2009-11-24 | Micron Technology, Inc. | Methods, devices, and systems for a delay locked loop having a frequency divided feedback clock |
| US7826279B2 (en) | 2008-04-10 | 2010-11-02 | Advanced Micro Devices, Inc. | Programmable bias circuit architecture for a digital data/clock receiver |
| US8395446B1 (en) | 2009-01-31 | 2013-03-12 | Xilinx, Inc. | Dual-mode amplifier |
| US8538355B2 (en) | 2010-04-19 | 2013-09-17 | Rf Micro Devices, Inc. | Quadrature power amplifier architecture |
| US20130216003A1 (en) * | 2012-02-16 | 2013-08-22 | Qualcomm Incorporated | RESETTABLE VOLTAGE CONTROLLED OSCILLATORS (VCOs) FOR CLOCK AND DATA RECOVERY (CDR) CIRCUITS, AND RELATED SYSTEMS AND METHODS |
| US9137008B2 (en) * | 2013-07-23 | 2015-09-15 | Qualcomm Incorporated | Three phase clock recovery delay calibration |
| US9215063B2 (en) * | 2013-10-09 | 2015-12-15 | Qualcomm Incorporated | Specifying a 3-phase or N-phase eye pattern |
-
2015
- 2015-09-01 US US14/842,644 patent/US9496879B1/en active Active
-
2016
- 2016-08-09 CN CN201680049777.4A patent/CN107925563B/zh active Active
- 2016-08-09 BR BR112018004159-9A patent/BR112018004159B1/pt active IP Right Grant
- 2016-08-09 CA CA2992751A patent/CA2992751C/en active Active
- 2016-08-09 ES ES16753549T patent/ES2777373T3/es active Active
- 2016-08-09 JP JP2018510826A patent/JP6876681B2/ja active Active
- 2016-08-09 WO PCT/US2016/046211 patent/WO2017039985A1/en unknown
- 2016-08-09 EP EP16753549.1A patent/EP3345334B1/en active Active
- 2016-08-09 TW TW105125371A patent/TWI720008B/zh active
- 2016-08-09 KR KR1020187009217A patent/KR102522742B1/ko active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| ES2777373T3 (es) | 2020-08-04 |
| KR20180048952A (ko) | 2018-05-10 |
| BR112018004159B1 (pt) | 2023-12-05 |
| JP2018526912A (ja) | 2018-09-13 |
| CN107925563B (zh) | 2020-12-08 |
| KR102522742B1 (ko) | 2023-04-17 |
| CN107925563A (zh) | 2018-04-17 |
| JP6876681B2 (ja) | 2021-05-26 |
| TW201714425A (zh) | 2017-04-16 |
| EP3345334A1 (en) | 2018-07-11 |
| EP3345334B1 (en) | 2019-11-20 |
| CA2992751C (en) | 2024-01-09 |
| WO2017039985A1 (en) | 2017-03-09 |
| TWI720008B (zh) | 2021-03-01 |
| CA2992751A1 (en) | 2017-03-09 |
| US9496879B1 (en) | 2016-11-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
| B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
| B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 09/08/2016, OBSERVADAS AS CONDICOES LEGAIS |