WO2016171681A1 - Communication using phase modulation over an interconnect - Google Patents

Communication using phase modulation over an interconnect

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Publication number
WO2016171681A1
WO2016171681A1 PCT/US2015/027029 US2015027029W WO2016171681A1 WO 2016171681 A1 WO2016171681 A1 WO 2016171681A1 US 2015027029 W US2015027029 W US 2015027029W WO 2016171681 A1 WO2016171681 A1 WO 2016171681A1
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WO
Grant status
Application
Patent type
Prior art keywords
phase
data
memory
device
interconnect
Prior art date
Application number
PCT/US2015/027029
Other languages
French (fr)
Inventor
Melvin K. Benedict
Original Assignee
Hewlett Packard Enterprise Development Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying includes continuous phase systems
    • H04L27/20Modulator circuits; Transmitter circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying includes continuous phase systems
    • H04L27/22Demodulator circuits; Receiver circuits

Abstract

An interconnect is provided between a requester device and a storage subsystem, the requester device and the storage subsystem to communicate over the interconnect using phase modulation that varies a phase of a signal on the interconnect for respective different values of data communicated over the interconnect.

Description

COMMUNICATION USING PHASE MODULATION OVER AN INTERCONNECT Background

[0001 ] A system can include a memory to store data. Various devices, including a processor or an input/output (I/O) device, are able to access the memory to read data or to write data. A memory bus interconnects a device and the memory.

Brief Description Of The Drawings

[0002] Some implementations are described with respect to the following figures.

[0003] Fig. 1 is a block diagram of an example arrangement including a requester device and a storage subsystem, according to some implementations.

[0004] Fig. 2 is a block diagram of an example memory device including a phase modulator/demodulator according to some implementations.

[0005] Fig. 3 is a flow diagram of a process of a storage subsystem according to some implementations.

[0006] Fig. 4 is a block diagram of an example memory according to further implementations.

[0007] Fig. 5 is a block diagram of a system that includes memory modules interconnected by an interconnect, according to some implementations.

Detailed Description

[0008] Data between a requester device (e.g. a processor, an I/O device, or any other device that is able to request access of stored data) and a memory can be communicated over an interconnect between the requester device and the memory. An interconnect can refer to any physical communication medium that is used to carry information. The physical communication medium can include an electrical communication medium (e.g. electrical conductors) and/or an optical communication medium (e.g. optical fibers or other optical transport media). [0009] The data can be communicated over the interconnect at a frequency that is supported by the requester device and the memory. An increase in the frequency of data communication on the interconnect can lead to signal integrity issues, due to increased noise or other factors. Such signal integrity issues can constrain the speed at which data communications can occur over the interconnect. As a result, memory access performance can suffer.

[0010] In accordance with some implementations of the present disclosure, phase modulation can be applied in communicating data between a requester device and a storage subsystem, such as a memory. A memory can be implemented with one or multiple memory devices, where a memory device can include a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a memristor memory, and so forth.

[001 1 ] In alternative examples, a storage subsystem can also include other types of storage devices, such as disk-based storage devices or other storage devices.

[0012] Phase modulation introduces different phase offsets into a signal (referred to as a "carrier signal") that is used to carry data over an interconnect between a requester device and a memory (or more generally, a storage subsystem). With phase modulation, different values of data map to different phase offsets that are introduced onto the carrier signal on the interconnect.

[0013] In the ensuing discussion, although reference is made to communications over an interconnect between a requester device with a memory, it is noted that techniques or mechanisms according to some implementations can also be applied to communications with other types of storage subsystems.

[0014] Fig. 1 is a block diagram of an example arrangement that includes a requester device 102 and a storage subsystem 104. The requester device 102 and the storage subsystem 104 are able to communicate with each other over an interconnect 106. The interconnect 106 can be an electrical interconnect (formed with electrical conductors) or an optical interconnect (formed with optical fibers or other forms of optical conduits). The requester device 102 includes a phase modulator/demodulator 108, and the storage subsystem 104 includes a phase modulator/demodulator 1 10. A phase modulator/demodulator includes a phase modulator and a phase demodulator.

[0015] Although just one requester device 102 and one storage subsystem 104 are depicted in Fig. 1 as connected to the interconnect 106, it is noted that in other examples, multiple requester devices 102 and/or multiple storage subsystems 104 can be connected to the interconnect 106.

[0016] A phase modulator is able to apply phase modulation based on data values to be communicated over the interconnect 106, by introducing respective phase offsets onto carrier signals depending on which data values are to be communicated over the interconnect 106. A phase modulated signal communicated over the interconnect 106 includes a carrier signal onto which a phase offset (selected from multiple different phase offsets) is introduced (modulated), where different phase offsets represent respective different data values.

[0017] A phase demodulator receives a phase modulated signal over the interconnect 106, and applies phase demodulation to extract a respective phase offset from the phase demodulated signal. The extracted phase offset, as extracted by the phase demodulator, corresponds to a respective data value.

[0018] As an example, the requester device 102 can issue a read request over the interconnect 106 to the storage subsystem 104, to read data from the storage subsystem 104. The storage subsystem 104 responds to the read request by retrieving data from a storage medium in the storage subsystem 104, and provides the retrieved data to the phase modulator/demodulator 1 10 to apply phase modulation. The phase modulation produces a phase modulated signal that is communicated over the interconnect 106 to the requester device 102. The phase demodulator/demodulator 108 in the requester device 102 applies phase

demodulation on the received phase modulated signal, to extract the respective data value(s), which is then used by the requester device 102. [0019] As another example, the requester device 102 can issue a write request to the storage subsystem 104 to write data to the storage subsystem 104. In this case, the phase modulator/demodulator 108 applies phase modulation based on the write data, and sends a phase modulated signal corresponding to the write data over the interconnect 106 to the storage subsystem 104. The phase

modulator/demodulator 1 10 in the storage subsystem 104 applies phase

demodulation on the received phase modulated signal, and extracts the

corresponding data value(s) for writing to the storage medium of the storage subsystem 104.

[0020] Different forms of phase modulation can be applied by the phase modulator/demodulator 108 or phase modulator/demodulator 1 10 according to some implementations. An n-bit (n > 1 ) phase modulation can be applied, where the n-bit phase modulation encodes n bits of data onto a phase modulated signal that is communicated over the interconnect 106. If n = 1 , then a phase modulated signal produced by a phase modulation represents one bit of data. If n = 4, as another example, then a phase modulated signal represents four bits of data. The n-bit phase modulation effectively corresponds to the number of bits of data that can be transferred in a clock cycle over the interconnect 106. Increasing the value of n can lead to increased bandwidth over the interconnect 106, since more bits can be communicated in each individual clock cycle over the interconnect 106.

[0021 ] An n-bit phase modulation corresponds to a 2n-state phase modulation. For example, if n = 4, then a phase modulator can produce 16 states that correspond to 16 phase offsets that can be modulated onto a carrier signal. Each phase offset of the 16 phase offsets represents 4 bits of data. More generally, a phase offset modulated onto a carrier signal by the n-bit phase modulation represents n bit(s) of data.

[0022] Note that each phase modulated signal is communicated over a single input/output (I/O) pin (e.g. data pin) of the requester device 102 or the storage subsystem 104. The interconnect 106 can be connected to multiple data pins of the requester device 102 or the storage subsystem 104, where each data pin can communicate a respective phase modulated signal over the interconnect 106. Each phase modulated signal of a respective data pin can thus represent n bit(s).

[0023] Fig. 2 is a block diagram of an example memory device 200 according to some implementations. The memory device 200 is an example of the storage subsystem 104 of Fig .1 . In examples where the memory device 200 is provided, the interconnect 106 connected to the memory device 200 can be referred to as a memory bus.

[0024] The memory device 200 includes a memory array 202, which includes memory storage elements to store data. In some examples, the memory device 200 can be a DRAM device, and the memory array 202 can include DRAM cells. In other examples, the memory device 200 can include other types of memory devices.

[0025] The memory device 200 includes a modulator/demodulator 204, which corresponds to the phase modulator/demodulator 1 10 shown in Fig. 1 . The modulator/demodulator 204 includes a phase modulator 206 and a phase

demodulator 208.

[0026] The memory device 200 also includes a local oscillator 210, which produces an oscillating signal (also referred to as a clock signal) provided to the phase modulator 206 and phase demodulator 208. Although the local oscillator 210 is shown as being part of the memory device 200, it is noted that in other examples, the local oscillator 210 can be external of the memory device 200.

[0027] The oscillating signal produced by the local oscillator 210 can form a carrier signal onto which phase offsets can be introduced by the phase modulator 206 to communicate data values over the interconnect 106. The phase modulator 206 produces an output signal 210, which is a phase modulated signal produced after application of the phase modulation by the phase modulator 206.

[0028] The phase modulator 206 receives encoded data from an encoder 212 in the memory device 200. The encoder 212 receives data from a buffer 214. Data in the buffer 214 is retrieved from the memory array 202. [0029] During a read operation, data is retrieved from the memory array 202 and temporarily stored in the buffer 214. The data in the buffer 214 (or a portion of the data in the buffer 214) is encoded by the encoder 212. The encoding applied by the encoder 212 can increase the number of bits of data, where the encoded data produced by the encoder 212 has a larger number of bits than the data portion from the buffer 214 encoded by the encoder 212. For example, the encoder 212 can receive 8 input data bits from the buffer 214, and after encoding applied by the encoder 212, a 10-bit data is output to the phase modulator 206 by the encoder 212. Such an encoding is referred to as an 8b to 10b encoding. As another example, the encoder 212 can receive 16 input data bits from the buffer 214, and produce 20 output data bits, to provide 16b to 20b encoding.

[0030] In other examples, other types of encoding can be applied by the encoder 212. Encoding applied by the encoder 212 introduces data transitions (transitions between 0 and 1 ) into the data so that synchronization between a source device and a target device can be maintained. The source device is the device that sends data, and the recipient device is the device that receives the data. The memory device 200 can be the source device for read operations, and the recipient device for write operations.

[0031 ] In cases where the data retrieved from a portion of the memory array 202 is relatively static data (e.g. all 0s or all 1 s or large portions of the data are 0s and 1 s), the encoding applied by the encoder 212 can change the static data to more dynamic data that includes a larger number of transitions between 0s and 1 s. The data transitions allow the source device and recipient device to synchronize their respective oscillators (or clocks) with each other. More generally, the encoding applied by the encoder 212 can increase the number of transitions in data to allow for synchronization between a source device and a recipient device.

[0032] The encoding applied by the encoder 212 can also introduce control characters (also referred to as framing characters) into a sequence of data bits. A control character is a specified control information element that provides any one of several different indications. For example, a first control character can indicate a start of a data transfer, a second control character can indicate an end of a data transfer, and a third control character can indicate that the data being transmitted is idle data. The transmitted idle data is dummy data since no actual data is being communicated between the source device and the recipient device, but the communication of data is performed when the source device is idle to allow for synchronization over the interconnect between the source device and the recipient device.

[0033] In other examples, other control characters can be introduced into a sequence of data bits by the encoder 212.

[0034] The phase modulator 206 receives the encoded data from the encoder 212, and applies phase modulation based on the encoded data to produce

respective output signals (phase modulated signals). Although just one output signal 210 is shown in Fig. 2, it is noted that the memory device 200 can have multiple data pins through which the phase modulator 206 can output respective phase modulated signals for communication over the interconnect 106.

[0035] Fig. 2 also shows receipt of an input signal 216 by the memory device 200, where the input signal 216 is a phase modulated signal communicated over the interconnect 106. Although just one input signal 216 is shown in Fig. 2, it is noted that there can be multiple input signals corresponding to the multiple data pins of the memory device 200.

[0036] The input signal 216 is received by the phase demodulator 208, which also receives the oscillating signal from the local oscillator 210. The phase

demodulator 208 applies phase demodulation on the input signal 216 to extract a phase offset of the input signal 216. Based on the phase offset, the phase

demodulator 208 outputs the corresponding data, n bit(s), which is provided to a decoder 218. Note that the extracted data is encoded data encoded by the source device that sent the data over the input signal 216 to the memory device 200. The decoder 218 in the memory device 200 applies decoding of the data received from the phase demodulator 208, where the decoding is the reverse of the encoding applied by the encoder 212. [0037] The decoded data is provided by the decoder 218 to a buffer 220, which temporarily stores the decoded data for writing to the memory array 202.

[0038] The requester device 102 with which the memory device 200 can communicate over the interconnect 106 can similarly include a phase

modulator/demodulator (similar to 204), an encoder (similar to 212), and a decoder (similar to 218).

[0039] Fig. 3 is a flow diagram of a process performed by a phase modulator (e.g. 1 10 or 206) in the storage subsystem (e.g. 104 or 200). A similar process can be performed by the phase modulator of the requestor device 102 in other examples.

[0040] The phase modulator of the storage subsystem phase modulates (at 302) data for communication over an interconnect between the storage subsystem and a recipient device (e.g. the requester device 102). The storage subsystem then sends (at 304) the phase modulated data over the interconnect to the recipient device. The phase modulated data includes a phase offset modulated onto a carrier signal.

[0041 ] Fig. 4 is a block diagram of an example memory 400 according to further implementations. The memory 400 can be a memory device (e.g. memory device 200 of Fig. 2), where the memory device can be a memory chip. In other examples, the memory 400 can be a memory module that includes multiple memory chips. As an example, the memory module can include a dual inline memory module (DIMM) or other type of memory module.

[0042] The memory 400 includes a memory storage medium 402, a phase modulator 404, and a phase demodulator 406. The memory 400 also includes an interface 408 that is able to communicate over the interconnect 106.

[0043] The phase modulator 404 can apply phase modulation on data retrieved from the memory storage medium 402, and to send the phase modulated data through the interface 408 over the interconnect 106 to a requester device (e.g. 102 in Fig. 1 ). [0044] The phase demodulator 406 can apply phase demodulation of phase modulated data received through the interface 408 from the interconnect 106 from the requester device, where the phase demodulated data is for writing to the memory storage medium 402.

[0045] The phase modulator 404 and phase demodulator 406 can operate in similar fashion as the phase modulator 206 and phase demodulator 208,

respectively, of Fig. 2.

[0046] In some examples, the interface 408 can include drivers and buffers to output data to the interconnect 106 and to receive data from the interconnect 106.

[0047] Fig. 5 is a block diagram of an example system that includes multiple memory modules (502 and 504 depicted in the example of Fig. 5) connected to the interconnect 106. The memory module 502 includes memory devices 506-1 to 506- p. The memory module 504 includes memory devices 508-1 to 508-p, where p > 2. The interconnect 106 in Fig. 5 is a multi-drop interconnect, since multiple memory modules are connected to the interconnect 106.

[0048] The memory module 502 also includes a local oscillator LO1 , and the memory module 504 includes a local oscillator LO2.

[0049] The interconnect 106 is associated with multiple channels 510-1 to 510-p. The memory devices 506-1 and 508-1 can communicate over the channel 510-1 , while the memory devices 506-p and 508-p can communicate over the channel 510- p. More generally, each set of memory devices 506-i and 508-i can communicate over a respective channel 510-i, where i = 1 to p.

[0050] Each memory device 506-1 to 506-p includes a respective phase modulator/demodulator 512, and each memory device 508-1 to 508-p includes a respective modulator/demodulator 514. The phase modulator/demodulator 512 or 514 includes a phase modulator and a phase demodulator that operate in a manner as discussed above. [0051 ] The multiple channels 510-1 to 510-p are defined by use of a multiplexing technique performed by the memory devices 506-1 to 506-p and 508-1 to 508-p. As an example, frequency division multiplexing (FDM) can be performed to produce the multiple channels 510-1 to 510-p, where different frequency bands correspond to the different channels. Thus, the memory devices 506-1 and 508-1 can communicate data in a first frequency band that corresponds to the first channel 510-1 , while the memory devices 506-p and 508-p can communicate data in another frequency band that corresponds to the channel 510-p. FDM can be applied by FDM circuitry in the interface 408 (Fig. 4) for example.

[0052] In other examples, other types of multiplexing techniques can be employed. For example, code division multiple access (CDMA) can be applied by the memory devices, where different codes are used to code data corresponding to the different channels 510-1 to 510-p. Data in the first channel 510-1 is coded with a first code, and data in another channel 510-p is coded with another different code. The coding applied for CDMA can be applied by the encoder 212 shown in Fig. 2, for example.

[0053] In examples where the interconnect 106 is an optical interconnect, then the channels 510-1 to 510-p can correspond to different optical wavelengths. In this case, wavelength division multiplexing (WDM) is performed, such that different sets of memory devices communicate using different wavelengths over the interconnect 106. The different wavelengths correspond to the multiple respective channels 510- 1 to 510-p. WDM can be applied by WDM circuitry in the interface 408 (Fig. 4) for example.

[0054] Fig. 5 also shows a requester device 520 connected to the interconnect 106, which includes a local oscillator LO1 and a local oscillator LO2. The local oscillators LO1 and LO2 correspond to LO1 and LO2, respectively, in the memory modules 502 and 504.

[0055] Using techniques according to some examples, various benefits may be achieved. For example, if drivers in interfaces of the storage subsystem 104 and the requester device 102 use low signal levels (signals having low amplitude swings), then the power consumption of the drivers used to drive the signals over the interconnect 106 can be reduced. Also, by using the encoder 212 of Fig. 2 to encode data, the interconnect 106 can be self-timed to maintain synchronization between a source device and a recipient device. Also, by using phase modulation, sensitivity to noise can be reduced. Additionally, the use of multiple local oscillators enables multi-drop connectivity on the interconnect 106.

[0056] In the foregoing description, numerous details are set forth to provide an understanding of the subject disclosed herein. However, implementations may be practiced without some of these details. Other implementations may include modifications and variations from the details discussed above. It is intended that the appended claims cover such modifications and variations.

Claims

What is claimed is: 1 . A system comprising:
a requester device;
a storage subsystem; and
an interconnect between the requester device and the storage subsystem, the requester device and the storage subsystem to communicate over the interconnect using phase modulation that varies a phase of a signal on the interconnect for respective different values of data communicated over the interconnect.
2. The system of claim 1 , wherein the storage subsystem comprises a memory module, and the interconnect comprises a memory bus.
3. The system of claim 1 , wherein the storage subsystem comprises a modulator to apply the phase modulation responsive to data retrieved from a storage medium of the storage subsystem, the applied phase modulation introducing a phase offset onto a carrier signal to produce a phase modulated signal for sending from the storage subsystem to the requester device over the interconnect.
4. The system of claim 1 , wherein the memory subsystem further comprises an oscillator to provide a clock signal, and wherein the phase modulation produces phase modulated data that represents n bits per cycle of the clock signal, where n is greater than or equal to one.
5. The system of claim 1 , wherein the storage subsystem comprises a
demodulator to apply phase demodulation responsive to a phase modulated signal received from the requester device over the interconnect, the phase demodulation to produce data for writing to a storage medium of the storage subsystem.
6. The system of claim 1 , wherein the storage subsystem comprises an encoder to encode data retrieved from a storage medium of the storage subsystem, to form encoded data that includes at least one control character and transitions for synchronizing the storage subsystem and the requester device.
7. The system of claim 6, wherein the control character indicates at least one selected from among a start of a transfer of data, an end of a transfer of data, and a transfer of idle data.
8. The system of claim 1 , wherein the requester device and the storage subsystem are to further communicate over a plurality of channels on the
interconnect, the plurality of channels provided by a multiplexing technique selected from among frequency division multiplexing (FDM), code division multiple access (CDMA), and wavelength division multiplexing (WDM).
9. The system of claim 1 , wherein the interconnect comprises one of an electrical interconnect and an optical interconnect.
10. A method comprising:
phase modulating, by a modulator in a storage subsystem, data for communication over an interconnect between the storage subsystem and a recipient device; and
sending, by the storage subsystem, the phase modulated data over the interconnect to the recipient device.
1 1 . The method of claim 10, wherein the phase modulating is an n-bit phase modulating, where phase modulated data produced by the phase modulating represents n bits to be communicated over the interconnect per cycle of a clock signal of the storage subsystem, where n > 1 .
12. The method of claim 10, further comprising encoding data to be communicated over the interconnect to form encoded data, the encoded data including transitions to maintain synchronization between the storage subsystem and the recipient device.
13. The method of claim 12, wherein the encoding further comprises inserting at least one control character into the encoded data, the control character to indicate at least one selected from among a start of data transfer, an end of data transfer, and a transfer of idle data.
14. A memory comprising:
a memory storage medium;
an interface to communicate over an interconnect with a device;
a phase modulator to apply phase modulation on data retrieved from the memory storage medium to produce phase modulated data, and to send the phased modulated data through the interface over the interconnect to the device; and
a phase demodulator to phase demodulate phase modulated data received through the interface from the interconnect from the device to produce phase demodulated data, the phase demodulated data for writing to the memory storage medium.
15. The memory of claim 14, wherein the memory is to apply multiplexing to communicate over respective channels of the interconnect.
PCT/US2015/027029 2015-04-22 2015-04-22 Communication using phase modulation over an interconnect WO2016171681A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040047434A1 (en) * 2002-09-10 2004-03-11 Waltho Alan E. Apparatus and method for WGIO phase modulation
US20050083179A1 (en) * 2000-06-06 2005-04-21 Battelle Memorial Institute Phase modulation in RF tag
US20070299998A1 (en) * 2006-06-23 2007-12-27 Mordechay Beck Method and System for Facilitating Faster Data Transmission between a Central Processing Unit and a Connected Memory Device
US7941056B2 (en) * 2001-08-30 2011-05-10 Micron Technology, Inc. Optical interconnect in high-speed memory systems
WO2014182448A2 (en) * 2013-05-06 2014-11-13 Qualcomm Incorporated Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050083179A1 (en) * 2000-06-06 2005-04-21 Battelle Memorial Institute Phase modulation in RF tag
US7941056B2 (en) * 2001-08-30 2011-05-10 Micron Technology, Inc. Optical interconnect in high-speed memory systems
US20040047434A1 (en) * 2002-09-10 2004-03-11 Waltho Alan E. Apparatus and method for WGIO phase modulation
US20070299998A1 (en) * 2006-06-23 2007-12-27 Mordechay Beck Method and System for Facilitating Faster Data Transmission between a Central Processing Unit and a Connected Memory Device
WO2014182448A2 (en) * 2013-05-06 2014-11-13 Qualcomm Incorporated Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation

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