CN108563604B

CN108563604B - PCS protocol multiplexing chip and method

Info

Publication number: CN108563604B
Application number: CN201810377350.8A
Authority: CN
Inventors: 刘长江; 刘勤让; 吕平; 沈剑良; 宋克; 朱珂; 陈艇; 陶常勇; 汪欣; 杨镇西; 李沛杰; 付豪; 张楠; 黄雅静; 张帆
Original assignee: Information Technology Innovation Center Of Tianjin Binhai New Area; Tianjin Xinhaichuang Technology Co ltd
Current assignee: Information Technology Innovation Center Of Tianjin Binhai New Area; Tianjin Xinhaichuang Technology Co ltd
Priority date: 2018-04-24
Filing date: 2018-04-24
Publication date: 2020-07-10
Anticipated expiration: 2038-04-24
Also published as: CN108563604A

Abstract

The invention provides a PCS protocol multiplexing chip and a method, wherein the chip comprises: the first coding module is used for coding the transmission data in the transmission path; the second coding module is used for coding the transmission data in the transmission path; and the coding selection module is used for receiving a first enabling signal transmitted by the first enabling signal line and coding the sending data by using the first coding module or the second coding module under the control of the first enabling signal. The embodiment of the invention can realize the transmission of data packaged according to the RapidIO PCS protocol and the 1000Base-X PCS protocol under the same architecture, thereby saving a large amount of logic resources and reducing the use cost of a chip.

Description

PCS protocol multiplexing chip and method

Technical Field

The invention relates to the technical field of computer software, in particular to a PCS protocol multiplexing chip and a method.

Background

Ethernet is a computer local area network based on data frame transmission. With the continuous development of ethernet technology, the application of ethernet technology has been expanded from the original local area network to the metropolitan area network and the wide area network, and the application range is extremely wide.

The high-speed serial (RapidIO) technology is mainly oriented to the interconnection communication of a high-performance embedded system, has higher transmission efficiency than the Ethernet, and can realize high-performance reliable data transmission based on hardware because the RapidIO technology has perfect consideration on routing, exchange, fault tolerance, error correction and use convenience.

1000Base-X and RapidIO are widely applied protocols, and under some complex application scenes, two protocols of Ethernet and RapidIO need to be realized, and dynamic switching can be carried out between the two protocols. The PCS architecture for these two protocols has many similar parts, especially in low transmission rate applications (below 10 Gbps). In the prior art, when the problem is solved, the two protocols are respectively realized in application, that is, under the same architecture, only the Ethernet PCS and the RapidIO PCS can be realized independently. In this way, the design of PCS realized by two protocols separately occupies a large amount of logic resources, and increases the use cost of the chip.

Disclosure of Invention

In view of this, the present invention provides a PCS protocol multiplexing chip and a method thereof, so as to alleviate the technical problems of the prior art, such as waste of logic resources and high chip use cost.

In a first aspect, an embodiment of the present invention provides a PCS protocol multiplexing chip, including: the device comprises a first coding module used for processing sending data packaged according to a RapidIO PCS protocol, a second coding module used for processing sending data packaged according to a 1000Base-X PCS protocol, and a coding selection module respectively connected with the first coding module and the second coding module, wherein the coding selection module is connected with a first enabling signal line;

the first coding module is used for coding the transmission data in the transmission path;

the second coding module is used for coding the sending data in the sending path;

the encoding selection module is configured to receive a first enable signal transmitted by the first enable signal line, and encode the transmission data by using the first encoding module or by using the second encoding module under the control of the first enable signal.

With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, where the chip further includes: the scrambling module is electrically connected with the code selection module, and the transmission gearbox is electrically connected with the scrambling module;

the scrambling module is used for scrambling the coded data output by the coding selection module as input;

and the transmission gearbox is used for performing bit width conversion processing and frequency conversion processing by taking the scrambled data output by the scrambling module as input.

With reference to the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where the chip further includes: the system comprises a sending end asynchronous FIFO module, an asynchronous clock selection module and a sending end polarity control module which is electrically connected with the sending gearbox, wherein the asynchronous clock selection module is connected with a second enabling signal line;

the sending end asynchronous FIFO module is used for performing clock domain crossing processing on the initial data received by the sending path;

the asynchronous clock selection module is configured to receive a second enable signal transmitted by the second enable signal line, perform clock domain crossing processing on the initial data by using the sending-end asynchronous FIFO module under the control of the second enable signal, and send the obtained sending data to the coding node, or send the sending data to the coding node;

and the transmitting end polarity control module is used for carrying out inversion processing on the variable speed data output by the transmission gearbox.

In a second aspect, an embodiment of the present invention further provides another PCS protocol multiplexing chip, including: the decoding device comprises a first decoding module used for processing received data packaged according to a RapidIO PCS protocol, a second decoding module used for processing received data packaged according to a 1000Base-X PCS protocol and a decoding selection module respectively connected with the first decoding module and the second decoding module, wherein the decoding selection module is connected with a third enabling signal line;

the first decoding module is used for decoding the received data in the receiving path;

the second decoding module is used for decoding the received data in the receiving path;

the decoding selection module is configured to receive a third enable signal transmitted by the third enable signal line, and decode the received data by using the first decoding module or the second decoding module under the control of the third enable signal.

With reference to the second aspect, an embodiment of the present invention provides a first possible implementation manner of the second aspect, where the chip further includes:

the device comprises a receiving end polarity control module, a synchronous head detection module, a receiving gearbox and a descrambling module which is electrically connected between the receiving gearbox and a decoding node;

the receiving end polarity control module is used for carrying out inversion processing on the initial data received by the receiving channel;

the synchronous head detection module is used for carrying out packet head detection processing by taking the reverse data output by the receiving end polarity control module as input;

the receiving gearbox is used for performing bit width conversion processing and frequency conversion processing on the initial data by taking packet header detection data output by the synchronous header detection module as input;

and the descrambling module is used for performing descrambling processing by taking the variable speed data output by the receiving gearbox as input and sending the received data obtained after descrambling processing to the decoding node.

With reference to the second aspect, an embodiment of the present invention provides a second possible implementation manner of the second aspect, where the chip further includes: the elastic cache module is electrically connected with the decoding selection module;

and the elastic buffer module is used for performing frequency deviation calibration processing by taking the decoding data output by the decoding selection module as input.

In a third aspect, an embodiment of the present invention further provides a PCS protocol multiplexing method, where the PCS protocol multiplexing chip according to any one of the first aspects is applied, and the method includes:

and enabling the coding selection module to receive a first enabling signal transmitted by the first enabling signal line, and coding the sending data by using the first coding module or the second coding module under the control of the first enabling signal.

With reference to the third aspect, an embodiment of the present invention provides a first possible implementation manner of the third aspect, where the method further includes:

enabling the asynchronous clock selection module to receive a second enable signal transmitted by the second enable signal line, performing clock-crossing processing on the initial data by using the sending-end asynchronous FIFO module under the control of the second enable signal, and sending the obtained sending data to a coding node, or sending the sending data to the coding node;

enabling the scrambling module to perform scrambling processing by taking the coded data output by the coding selection module as input;

the sending gearbox takes the scrambled data output by the scrambling module as input to carry out bit width conversion processing and frequency conversion processing;

and enabling the polarity control module at the sending end to perform inversion processing according to the variable speed data output by the transmission gearbox.

In a fourth aspect, an embodiment of the present invention further provides another PCS protocol multiplexing method, where the PCS protocol multiplexing chip according to any one of the second aspects is applied, and the method includes:

and enabling the decoding selection module to receive a third enable signal transmitted by the third enable signal line, and decoding the received data by using the first decoding module or the second decoding module under the control of the third enable signal.

With reference to the fourth aspect, an embodiment of the present invention provides a first possible implementation manner of the fourth aspect, where the method further includes:

enabling the elastic buffer module to carry out frequency deviation calibration processing by taking the decoding data output by the decoding selection module as input;

enabling the receiving end polarity control module to perform inversion processing on initial data received by a receiving channel;

enabling the synchronous head detection module to perform packet head detection processing by taking the reverse data output by the receiving end polarity control module as input;

enabling the receiving gearbox to perform bit width conversion processing and frequency conversion processing on the initial data by taking packet header detection data output by the synchronous header detection module as input;

and enabling the descrambling module to perform descrambling processing by taking the variable speed data output by the receiving gearbox as input, and sending the received data obtained after descrambling processing to the decoding node.

The embodiment of the invention has the following beneficial effects: after receiving the first enable signal transmitted by the first enable signal line, the coding selection module according to the embodiment of the present invention codes the transmission data encapsulated according to the RapidIO PCS protocol by using the first coding module under the control of the first enable signal, or codes the transmission data encapsulated according to the 1000Base-X PCS protocol by using the second coding module.

The PCS protocol multiplexing chip provided by the embodiment of the invention can realize the transmission of data packaged according to the RapidIO PCS protocol and the 1000Base-X PCS protocol under the same framework, thereby saving a large amount of logic resources and reducing the use cost of the chip.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a block diagram of a PCS protocol multiplexing chip according to an embodiment of the present invention;

fig. 2 is a block diagram of another PCS protocol multiplexing chip according to an embodiment of the present invention;

fig. 3 is a flowchart of a PCS protocol multiplexing method according to an embodiment of the present invention;

fig. 4 is a flowchart of another PCS protocol multiplexing method according to an embodiment of the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

At present, under the same architecture, the transmission of data in a 10G backplane Ethernet physical coding sublayer or a 10.3125G high-speed serial physical coding sublayer can be realized only independently, a large amount of logic resources are occupied, and the use cost of a chip is increased.

To facilitate understanding of the present embodiment, first, a PCS protocol multiplexing chip disclosed in the embodiment of the present invention is described in detail, and fig. 1 is a block diagram of a structure of a PCS protocol multiplexing chip provided in the embodiment of the present invention, as shown in fig. 1, where the chip includes: the device comprises a first coding module 11 used for processing transmission data packaged according to RapidIO PCS protocol, a second coding module 12 used for processing transmission data packaged according to 1000Base-X PCS protocol, and a coding selection module 13 respectively connected with the first coding module 11 and the second coding module 12, wherein the coding selection module 13 is connected with a first enabling signal line 10;

a first encoding module 11, configured to encode transmission data in a transmission path;

a second encoding module 12, configured to encode the transmission data in the transmission path;

and the coding selection module 13 is configured to receive a first enable signal transmitted by the first enable signal line 10, and code the transmission data by using the first coding module 11 or the second coding module 12 under the control of the first enable signal.

Specifically, after the coding selection module 13 receives the first enable signal transmitted by the first enable signal line 10, the first coding module 11 is used to code the transmission data encapsulated according to the RapidIO PCS protocol under the control of the first enable signal, or the second coding module 12 is used to code the transmission data encapsulated according to the 1000Base-X PCS protocol under the control of the first enable signal.

Illustratively, when the first enable signal received by the coding selection module 13 is 1, the first coding module 11 is used to code the transmission data encapsulated according to the RapidIO PCS protocol; when the first enable signal received by the coding selection module 13 is 0, the second coding module 12 is used to code the transmission data encapsulated according to the 1000Base-X PCS protocol.

The invention provides a method for selecting different rates through a register. The protocol is selected by the value of the protocol register, and the rate is selected by the value of the rate register, and the specific corresponding relationship is as shown in table 1 below.

TABLE 1

Rate register value	1000Base-X	RapidIO
			0b000	1.25G	1.25G
0b001	1.25G	2.5G
			0b010	1.25G	5G
0b011	1.25G	3.125G
			0b100	1.25G	6.25G

The PCS protocol multiplexing chip provided in the embodiment of the present invention further includes: a scrambling module 14 electrically connected with the code selection module 13 and a transmission gearbox 15 electrically connected with the scrambling module 14.

And a scrambling module 14, configured to perform scrambling processing with the encoded data output by the encoding selection module 13 as input.

Specifically, the encoded data is scrambled to ensure dc balance. Because the scrambling mode of the sending data encapsulated by the RapidIO PCS protocol and the 1000Base-X PCS protocol is the same, the two protocols can multiplex the same scrambling module 14.

And the transmission gearbox 15 is used for performing bit width conversion processing and frequency conversion processing by taking the scrambled data output by the scrambling module 14 as input.

Specifically, the bit widths of the transmission data encapsulated by the RapidIO PCS protocol and the 1000Base-X PCS protocol are different, the first encoding module 11 encodes the transmission data encapsulated by the RapidIO PCS protocol into 66 bits, and the transmission gearbox 15 converts the 66 bits of data into 40 bits of data; the second encoding module 12 encodes the encoded data encapsulated according to the 1000Base-X PCS protocol into 67 bits, and the transmission gearbox 15 converts the 67 bits of data into 40 bits of data.

The PCS protocol multiplexing chip provided in the embodiment of the present invention further includes: the system comprises a sending end asynchronous FIFO module 16, an asynchronous clock selection module 17 and a sending end polarity control module 18 electrically connected with the sending gearbox 15, wherein the asynchronous clock selection module 17 is connected with a second enabling signal line 19.

And the sending-end asynchronous FIFO module 16 is configured to perform clock domain crossing processing on the initial data received by the sending path.

And the asynchronous clock selection module 17 is configured to receive a second enable signal transmitted by a second enable signal line 19, perform clock domain crossing processing on the initial data by using the sending-end asynchronous FIFO module 16 under the control of the second enable signal, and send the obtained sending data to the coding node, or send the sending data to the coding node.

Specifically, when the clocks at the two ends of the initial data received by the transmission path are not consistent, the asynchronous clock selection module 17 performs clock domain crossing processing on the initial data by using the asynchronous FIFO module 16 at the transmission end under the control of the second enable signal, and transmits the obtained transmission data to the coding node; when the clocks at the two ends of the initial data received by the transmission path are consistent, the asynchronous clock selection module 17 transmits the obtained transmission data to the coding node under the control of the second enable signal.

And the sending end polarity control module 18 is used for performing inversion processing on the transmission data output by the sending gearbox 15.

In another embodiment of the present invention, a PCS protocol multiplexing chip is further provided, and it should be understood that the PCS protocol multiplexing chip provided in the embodiment of the present invention and the PCS protocol multiplexing chip provided in the foregoing embodiment are associated with each other and cannot be used separately because one is used for encoding data in a transmission path and one is used for decoding data in a reception path. Fig. 2 is a block diagram of another structure of a PCS protocol multiplexing chip according to an embodiment of the present invention, and as shown in fig. 2, the chip includes: a first decoding module 21 for processing the received data encapsulated according to RapidIO PCS protocol, a second decoding module 22 for processing the received data encapsulated according to 1000Base-X PCS protocol, and a decoding selection module 23 respectively connected with the first decoding module 21 and the second decoding module 22, wherein the decoding selection module 23 is connected with a third enabling signal line 20;

a first decoding module 21, configured to decode received data in a receive path;

a second decoding module 22, configured to decode the received data in the receiving path;

and a decoding selection module 23, configured to receive a third enable signal transmitted by the third enable signal line 20, and decode the received data by using the first decoding module 21 or the second decoding module 22 under the control of the third enable signal.

Specifically, after the decoding selection module 23 receives the third enable signal transmitted by the third enable signal line 20, the first decoding module 21 is used to decode the received data encapsulated according to the RapidIO PCS protocol under the control of the third enable signal, or the second decoding module 22 is used to decode the received data encapsulated according to the 1000Base-X PCS protocol under the control of the third enable signal.

Illustratively, when the third enable signal received by the decoding selection module 23 is 1, the first decoding module 21 is used to decode the received data encapsulated according to the RapidIO PCS protocol; when the third enable signal received by the decoding selection module 23 is 0, the second decoding module 22 is utilized to decode the received data encapsulated according to the 1000Base-X PCS protocol.

The PCS protocol multiplexing chip provided by the embodiment of the present invention further includes: the receiving terminal polarity control module 24, the sync head detection module 25, the receiving gearbox 26 and the descrambling module 27 electrically connected between the receiving gearbox and the decoding node.

And the receiving end polarity control module 24 is configured to perform inversion processing on the initial data received by the receiving channel.

And a sync header detection module 25, configured to perform packet header detection processing by using the inverted data output by the receiving end polarity control module 24 as an input.

Specifically, since the packet length of the data packet of the received data encapsulated by the RapidIO PCS protocol is 66 bits, and the packet length of the data packet of the received data encapsulated by the 1000Base-X PCS protocol is 67 bits, the sync header detection module 25 needs to detect the packet header for different protocols.

For a data packet of received data encapsulated according to the RapidIO PCS protocol, the sync header detection module 25 performs packet header detection on the received data based on the packet length of the data packet being 66 bits, and further delimitates the received data; for the data packet of the received data encapsulated according to the 1000Base-X PCS protocol, the sync header detection module 25 performs packet header detection on the received data based on the packet length of the data packet being 67 bits, and further delimitates the received data.

And the receiving gearbox 26 is configured to perform bit width conversion processing and frequency conversion processing on the initial data by using the packet header detection data output by the synchronous header detection module 25 as input.

Specifically, the bit widths of the received data encapsulated by the RapidIO PCS protocol and the 1000Base-X PCS protocol are different, the first decoding module 21 decodes the received data encapsulated by the RapidIO PCS protocol into 66 bits, and the receiving gearbox 26 converts the 66 bits of data into 40 bits of data; the second decoding module 22 decodes the received data encapsulated according to the 1000Base-X PCS protocol into 67 bits, and the receiving gearbox 26 converts the 67 bits of data into 40 bits of data.

And the descrambling module 27 is configured to perform descrambling processing with the transmission data output by the transmission case 26 as input, and send received data obtained after descrambling processing to the decoding node.

The PCS protocol multiplexing chip provided by the embodiment of the present invention further includes: an elastic buffer module 28 electrically connected to the decoding selection module 23;

and an elastic buffer module 28, configured to perform frequency offset calibration processing by using the decoded data output by the decoding selection module 23 as an input.

The received data need to be transferred to the subsequent module after being decoded, but because the PCS layer uses the clock recovered by the PMA and the subsequent module uses the local clock, there may exist a certain given frequency offset between the two, and when the data transmission amount is large, the frequency offset is accumulated to be large, thereby causing data overflow.

Specifically, the elastic buffer module 28 adds or deletes an ID L E sequence of the decoded data defined in the RapidIO PCS protocol to implement the frequency offset calibration, and the elastic buffer module 28 adds or deletes an ID L E sequence of the decoded data defined in the 1000Base-X PCS protocol to implement the frequency offset calibration.

The invention can multiplex a large number of modules of 1000Base-X and RapidIO low-speed PCS in the same framework, wherein the coding and decoding modules are completely different and cannot be multiplexed, the operation of specifically adding and deleting an ID L E sequence caused by different protocols of the elastic cache can be only partially multiplexed, and the rest modules can be multiplexed, as shown in the following table 2.

TABLE 2

Name of module	Degree of multiplexing
		Receiver polarity control	Complete multiplexing
Descrambling	Complete multiplexing
		Decoding	Can not be reused
Elastic cache	Partial multiplexing
		Transmit terminal polarity control	Complete multiplexing
Scrambling	Complete multiplexing
		Encoding	Can not be reused
Asynchronous FIFO of sending terminal	Complete multiplexing

Compared with the scheme of completely and independently realizing 1000Base-X and RapidIO low-speed PCS, the method saves a large amount of logic resources, reduces the chip area and reduces the chip power consumption on the two PCS schemes.

In another embodiment of the present invention, a PCS protocol multiplexing method is further provided, and fig. 3 is a flowchart of a PCS protocol multiplexing method according to an embodiment of the present invention, where the method uses a PCS protocol multiplexing chip that encodes data in a transmission path according to the above embodiment, and as shown in fig. 3, the method includes:

step S100, enabling the asynchronous clock selection module to receive a second enable signal transmitted by the second enable signal line, performing clock-crossing processing on the initial data by using the sending-end asynchronous FIFO module under the control of the second enable signal, and sending the obtained sending data to a coding node, or sending the sending data to the coding node;

step S101, enabling the coding selection module to receive a first enable signal transmitted by the first enable signal line, and coding the transmission data by using a first coding module or a second coding module under the control of the first enable signal;

step S102, the scrambling module takes the coded data output by the code selection module as input to carry out scrambling processing;

step S103, the sending gearbox takes the scrambled data output by the scrambling module as input to carry out bit width conversion processing and frequency conversion processing;

and step S104, enabling the sending end polarity control module to perform inversion processing according to the speed change data output by the sending gearbox.

In another embodiment of the present invention, another PCS protocol multiplexing method is further provided, and fig. 4 is a flowchart of another PCS protocol multiplexing method provided in the embodiment of the present invention, where the method applies a PCS protocol multiplexing chip that encodes data in a receive path according to the above embodiment, as shown in fig. 4, the method includes:

step S200, the polarity control module of the receiving end is enabled to perform inversion processing on initial data received by a receiving channel;

step S201, enabling the sync header detection module to perform packet header detection processing by using the inverted data output by the receiving end polarity control module as input;

step S202, the receiving gearbox takes packet head detection data output by the synchronous head detection module as input to carry out bit width conversion processing and frequency conversion processing on the initial data;

step S203, enabling the descrambling module to perform descrambling processing by taking the variable speed data output by the receiving gearbox as input, and sending the received data obtained after descrambling processing to the decoding node;

step S204, enabling the decoding selection module to receive a third enable signal transmitted by the third enable signal line, and decoding the received data by using the first decoding module or the second decoding module under the control of the third enable signal;

step S205, the elastic buffer module performs frequency offset calibration processing with the decoded data output by the decoding selection module as input.

After receiving the first enable signal transmitted by the first enable signal line, the coding selection module according to the embodiment of the present invention codes the transmission data encapsulated according to the RapidIO PCS protocol by using the first coding module under the control of the first enable signal, or codes the transmission data encapsulated according to the 1000Base-X PCS protocol by using the second coding module.

In practical application, the PCS protocol multiplexing method provided by the present invention may include the following steps:

1. after data in a transmission path enters the PCS of the invention, if clocks at two ends are inconsistent, clock domain crossing operation is required, and the data is transmitted to an asynchronous FIFO (first in first out) of a transmitting end to complete clock domain crossing processing; otherwise the data is bypassed directly.

2. The low speed 1000Base-X and RapidIO PCS use 8b/10b coding, but the specific coding modes are different. Therefore, before data enters the encoding module, the corresponding encoding module needs to be selected according to the register value of the implementation protocol in table 1.

3. After encoding, the data may be scrambled to ensure dc balance. Scrambling is necessary for 6.25G RapidIO; the remaining rates may or may not be scrambled, depending on the register configuration. The 1000Base-X does not need to carry out scrambling operation and can be directly bypassed.

4. And the polarity control module of the sending end is used for controlling whether the two protocols are reversed or not, and the two protocols are both required to be realized, so that multiplexing can be realized.

In practical application, another PCS protocol multiplexing method provided by the present invention may include the following steps:

1. after entering the PCS of the present invention, the data in the receive path enters the receive polarity control block to control whether the polarity is inverted.

2. After the data passes through the receiving polarity control module, the data does not know which bit data form a data packet, so that the received data is delimited, and then the data is sent to the descrambling module.

3. If the data in the receiving path is scrambled at the transmitting end, the corresponding descrambling is required to be completed at the receiving side so as to obtain the correct data. The data of 6.25G RapidIO is scrambled when being transmitted, so that the data must be descrambled at the receiving end, and whether the other rates need descrambling or not is determined by the configuration of a register. The 1000Base-X has no scrambling at the transmitting end, has no descrambling at the receiving end, and directly bypasses.

4. Data needs to be decoded after descrambling, although the 1000Base-X and RapidIO adopt 8b/10b coding and decoding, the specific decoding modes of respective protocols are different, so that a corresponding decoding module needs to be selected according to the actually selected protocol.

5. The method includes that a PMA recovered clock is used by a PCS layer, a local clock is used by a subsequent module, and a certain frequency offset may exist between the PMA recovered clock and the local clock, when the data transmission amount is large, the frequency offset is accumulated to be large, so that data overflow is caused.

The invention provides a PCS protocol multiplexing method. Because the transmission rates of 1000Base-X and RapidIO are different, different clocks need to be selected according to different protocols for local clocks, namely a receiving side clock of the elastic cache module and a writing side clock of the asynchronous FIFO of the sending end.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A PCS protocol multiplexing chip, comprising: the device comprises a first coding module used for processing sending data packaged according to a RapidIO PCS protocol, a second coding module used for processing sending data packaged according to a 1000Base-X PCS protocol, and a coding selection module respectively connected with the first coding module and the second coding module, wherein the coding selection module is connected with a first enabling signal line;

2. The PCS protocol multiplexing chip of claim 1 further comprising: the scrambling module is electrically connected with the code selection module, and the transmission gearbox is electrically connected with the scrambling module;

the scrambling module is used for scrambling the encoded data output by the first encoding module or the second encoding module as input;

3. The PCS protocol multiplexing chip of claim 2 further comprising: the system comprises a sending end asynchronous FIFO module, an asynchronous clock selection module and a sending end polarity control module which is electrically connected with the sending gearbox, wherein the asynchronous clock selection module is connected with a second enabling signal line;

and the transmitting end polarity control module is used for carrying out inversion processing on the variable speed data output by the transmitting gearbox.

4. A PCS protocol multiplexing chip, comprising: the decoding device comprises a first decoding module used for processing received data packaged according to a RapidIO PCS protocol, a second decoding module used for processing received data packaged according to a 1000Base-X PCS protocol and a decoding selection module respectively connected with the first decoding module and the second decoding module, wherein the decoding selection module is connected with a third enabling signal line;

5. The PCS protocol multiplexing chip of claim 4, further comprising: the device comprises a receiving end polarity control module, a synchronous head detection module, a receiving gearbox and a descrambling module which is electrically connected between the receiving gearbox and a decoding node;

6. The PCS protocol multiplexing chip of claim 5, further comprising: the elastic cache module is electrically connected with the decoding selection module;

7. A PCS protocol multiplexing method applying the PCS protocol multiplexing chip of claim 3, the method comprising:

8. The PCS protocol multiplexing method of claim 7, said method further comprising:

and enabling the transmitting end polarity control module to perform inversion processing on the variable speed data output by the transmitting gearbox.

9. A PCS protocol multiplexing method applying the PCS protocol multiplexing chip of claim 6, the method comprising:

and enabling the decoding selection module to receive a third enable signal transmitted by the third enable signal line, and decoding the received data in a receiving path by using the first decoding module or the second decoding module under the control of the third enable signal.

10. The PCS protocol multiplexing method of claim 9, further comprising: