CN108563604A - PCS protocol multiplexings chip and method - Google Patents
PCS protocol multiplexings chip and method Download PDFInfo
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- CN108563604A CN108563604A CN201810377350.8A CN201810377350A CN108563604A CN 108563604 A CN108563604 A CN 108563604A CN 201810377350 A CN201810377350 A CN 201810377350A CN 108563604 A CN108563604 A CN 108563604A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The present invention provides a kind of PCS protocol multiplexings chip and method, which includes：First coding module, for being encoded to the transmission data in transmission path；Second coding module, for being encoded to the transmission data in transmission path；Selecting module is encoded, the first enable signal for receiving the first enable signal line transmission encodes transmission data using the first coding module or using the second coding module under the control of the first enable signal.The embodiment of the present invention can be realized the transmission according to RapidIO PCS agreements and the data of 1000Base X PCS protocol encapsulations, save a large amount of logical resources, reduce the use cost of chip under same framework.
Description
Technical field
The present invention relates to computer software technical fields, more particularly, to a kind of PCS protocol multiplexings chip and method.
Background technology
Ethernet is the computer LAN based on data frame transfer.With the continuous development of ethernet technology, Ethernet
The application of technology has had spread over Metropolitan Area Network (MAN) and wide area network by initial LAN, application range and its extensively.
High speed serialization (RapidIO) technology is mainly the interconnected communication towards high performance embedded system, than Ethernet
Efficiency of transmission higher, and due to RapidIO technologies have in routing, exchange, fault-tolerant error correction and ease of use it is more perfect
Consider, hardware based high-performance reliable data transmission may be implemented.
1000Base-X and RapidIO is to have widely applied agreement, under some complex application contexts, it would be desirable to be able to
It enough realizes two kinds of agreements of Ethernet and RapidIO, and switching at runtime can be carried out between the two.Especially transmission rate compared with
In low scene (being less than 10Gbps) application, the PCS structures of both agreements have many similar parts.The prior art is solving
It is to realize both agreements respectively in the application, that is, under same framework, be only capable of being implemented separately when this problem
Ethernet PCS and RapidIO PCS.In this fashion, the design that PCS is implemented separately in two kinds of agreements occupies largely
Logical resource, and increase the use cost of chip.
Invention content
In view of this, the purpose of the present invention is to provide a kind of PCS protocol multiplexings chip and method, to alleviate existing skill
The high technical problem of the waste of logical resource present in art, chip use cost.
In a first aspect, an embodiment of the present invention provides a kind of PCS protocol multiplexings chips, including：For handle according to
First coding module of the transmission data of RapidIO PCS protocol encapsulations is sealed for handling according to 1000Base-X PCS agreements
Second coding module of the transmission data of dress, the coding being connect respectively with first coding module and second coding module
Selecting module, the coding selecting module connect the first enable signal line；
First coding module, for being encoded to the transmission data in transmission path；
Second coding module, for being encoded to the transmission data in transmission path；
The coding selecting module, the first enable signal for receiving the first enable signal line transmission, described
Using first coding module or using second coding module to the transmission number under the control of first enable signal
According to being encoded.
With reference to first aspect, an embodiment of the present invention provides the first possible embodiments of first aspect, wherein institute
Stating chip further includes：It is electrically connected with the scrambling module of the coding selecting module electric connection and with the scrambling module
Send gearbox；
The scrambling module, for being carried out at scrambling as input using the coded data of the coding selecting module output
Reason；
The transmission gearbox, for being carried out at bit width conversion using the scrambled data that the scrambling module exports as input
Reason and frequency conversion process.
With reference to first aspect, an embodiment of the present invention provides second of possible embodiments of first aspect, wherein institute
Stating chip further includes：Transmitting terminal asynchronous FIFO module, asynchronous clock selecting module and with it is described transmission gearbox be electrically connected
Transmitting terminal polarity control module, the asynchronous clock selecting module connect the second enable signal line；
The transmitting terminal asynchronous FIFO module, the primary data for being received to transmission path carry out at cross clock domain
Reason；
The asynchronous clock selecting module, the second enable signal for receiving the second enable signal line transmission,
Cross clock domain is carried out to the primary data using the transmitting terminal asynchronous FIFO module under the control of second enable signal
Processing, and obtained transmission data is sent to coding nodes, alternatively, the transmission data is sent to coding nodes；
The transmitting terminal polarity control module, for being carried out at reversion with the variable rate data of the transmission gearbox output
Reason.
Second aspect, the embodiment of the present invention additionally provide another PCS protocol multiplexings chip, including：For handle according to
First decoder module of the reception data of RapidIO PCS protocol encapsulations is sealed for handling according to 1000Base-X PCS agreements
Second decoder module of the reception data of dress and the solution being connect respectively with first decoder module and second decoder module
Code selecting module, the decoding selecting module connect third enable signal line；
First decoder module, for being decoded to the reception data in receiving path；
Second decoder module, for being decoded to the reception data in receiving path；
The decoding selecting module, the third enable signal for receiving the third enable signal line transmission, described
Using first decoder module or using second decoder module to the reception number under the control of third enable signal
According to being decoded.
In conjunction with second aspect, an embodiment of the present invention provides the first possible embodiments of second aspect, wherein institute
Stating chip further includes：
Receiving terminal polarity control module, synchronous head detection module receive gearbox and are electrically connected at the reception speed change
Descrambling module between case and decoding node；
The receiving terminal polarity control module, for carrying out reversion processing to the primary data for receiving channel reception；
The synchronous head detection module, for using the reversal data that the receiving terminal polarity control module exports as input
Carry out packet header detection process；
The reception gearbox is used for using the packet header detection data that the synchronous head detection module exports as input to institute
It states primary data and carries out bit width conversion processing and frequency conversion process；
The descrambling module, for carrying out scramble process as input using the variable rate data of the reception gearbox output,
The reception data obtained after scramble process are sent to the decoding node.
In conjunction with second aspect, an embodiment of the present invention provides second of possible embodiments of second aspect, wherein institute
Stating chip further includes：The elastic caching module being electrically connected with the decoding selecting module；
The elastic caching module, for using the decoding data of the decoding selecting module output as inputting into line frequency
Deviation calibration processing.
The third aspect, the embodiment of the present invention additionally provide a kind of PCS protocol multiplexings method, appoint using such as above-mentioned first aspect
PCS protocol multiplexing chips described in one, the method includes：
The coding selecting module is set to receive the first enable signal of the first enable signal line transmission, described first
Under the control of enable signal using first coding module or using second coding module to the transmission data into
Row coding.
In conjunction with the third aspect, an embodiment of the present invention provides the first possible embodiments of the third aspect, wherein institute
The method of stating further includes：
The asynchronous clock selecting module is set to receive the second enable signal of the second enable signal line transmission, described
Across clock processing is carried out to the primary data using the transmitting terminal asynchronous FIFO module under the control of second enable signal, and
Obtained transmission data is sent to coding nodes, coding nodes are sent to alternatively, the transmission data is sent to；
The scrambling module is set to carry out scrambling processing as input using the coded data of the coding selecting module output；
The transmission gearbox is set to carry out bit width conversion processing using the scrambled data that the scrambling module exports as input
And frequency conversion process；
The transmitting terminal polarity control module is set to carry out reversion processing with the variable rate data of the transmission gearbox output.
Fourth aspect, the embodiment of the present invention additionally provide another PCS protocol multiplexings method, using such as above-mentioned second aspect
Any PCS protocol multiplexing chips, the method includes：
The decoding selecting module is set to receive the third enable signal of the third enable signal line transmission, in the third
Under the control of enable signal using first decoder module or using second decoder module to the reception data into
Row decoding.
In conjunction with fourth aspect, an embodiment of the present invention provides the first possible embodiments of fourth aspect, wherein institute
The method of stating further includes：
The elastic caching module is set to carry out frequency departure school as input using the decoding data for decoding selecting module output
Quasi- processing；
The receiving terminal polarity control module is set to carry out reversion processing to the primary data for receiving channel reception；
Make the synchronous head detection module using the reversal data that the receiving terminal polarity control module exports as input into
Row packet header detection process；
Make the reception gearbox using the packet header detection data that the synchronous head detection module exports as input to described
Primary data carries out bit width conversion processing and frequency conversion process；
The descrambling module is set to carry out scramble process using the variable rate data of the reception gearbox output as input, and will
The reception data obtained after scramble process are sent to the decoding node.
The embodiment of the present invention brings following advantageous effect：Coding selecting module described in the embodiment of the present invention is receiving
After first enable signal of the first enable signal line transmission, the first coding is utilized under the control of first enable signal
Module to according to the transmission data of RapidIO PCS protocol encapsulations carry out encode or using the second coding module to according to
The transmission data of 1000Base-X PCS protocol encapsulations is encoded.
PCS protocol multiplexings chip provided in an embodiment of the present invention can be realized under same framework according to RapidIO PCS
The transmission of the data of agreement and 1000Base-X PCS protocol encapsulations, saves a large amount of logical resources, reduces the use of chip
Cost.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages are in specification, claims
And specifically noted structure is realized and is obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate
Appended attached drawing, is described in detail below.
Description of the drawings
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, in being described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, other drawings may also be obtained based on these drawings.
Fig. 1 is a kind of structure diagram of PCS protocol multiplexings chip provided in an embodiment of the present invention；
Fig. 2 is the structure diagram of another kind PCS protocol multiplexing chips provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of PCS protocol multiplexings method provided in an embodiment of the present invention；
Fig. 4 is the flow chart of another kind PCS protocol multiplexing methods provided in an embodiment of the present invention.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, shall fall within the protection scope of the present invention.
Currently, under same framework, be only capable of being implemented separately data in 10G backboard Ethernet Physical Coding Sublayers or
The transmission of 10.3125G high speed serialization Physical Coding Sublayers, occupies a large amount of logical resources, increases the use cost of chip, base
In this, a kind of PCS protocol multiplexings chip provided in an embodiment of the present invention and method, can under same framework, realize according to
The transmission of the data of RapidIO PCS agreements and 1000Base-X PCS protocol encapsulations, saves a large amount of logical resources, reduces
The use cost of chip.
For ease of understanding the present embodiment, first to a kind of PCS protocol multiplexings core disclosed in the embodiment of the present invention
Piece describes in detail, and Fig. 1 is a kind of structure diagram of PCS protocol multiplexings chip provided in an embodiment of the present invention, such as Fig. 1 institutes
Show, which includes：For handling the first coding module 11 of the transmission data according to RapidIO PCS protocol encapsulations, being used for
Processing according to 1000Base-X PCS protocol encapsulations transmission data the second coding module 12, respectively with the first coding module 11
With the coding selecting module 13 of the second coding module 12 connection, coding selecting module 13 connects the first enable signal line 10；
First coding module 11, for being encoded to the transmission data in transmission path；
Second coding module 12, for being encoded to the transmission data in transmission path；
Selecting module 13 is encoded, the first enable signal for receiving the transmission of the first enable signal line 10, described first
The transmission data is compiled using the first coding module 11 or using the second coding module 12 under the control of enable signal
Code.
Specifically, after coding selecting module 13 receives the first enable signal of the first enable signal line 10 transmission,
Using the first coding module 11 to the transmission data according to RapidIO PCS protocol encapsulations under the control of first enable signal
It is encoded, or utilizes the second coding module 12 to according to 1000Base-X PCS under the control of first enable signal
The transmission data of protocol encapsulation is encoded.
Illustratively, when it is 1 to encode the first enable signal that selecting module 13 receives, the first coding module 11 is utilized
To being encoded according to the transmission data of RapidIO PCS protocol encapsulations；When coding selecting module 13 receive it is first enabled
When signal is 0, using the second coding module 12 to being encoded according to the transmission data of 1000Base-X PCS protocol encapsulations.
Invention provides a kind of method selecting different rates by register.First pass through the value selection association of protocol register
View, rate, specific correspondence such as the following table 1 are selected in the value of through-rate register.
Table 1
| Rate register value | 1000Base-X | RapidIO |
| 0b000 | 1.25G | 1.25G |
| 0b001 | 1.25G | 2.5G |
| 0b010 | 1.25G | 5G |
| 0b011 | 1.25G | 3.125G |
| 0b100 | 1.25G | 6.25G |
The embodiment of the present invention provides PCS protocol multiplexing chips：The scrambling being electrically connected with coding selecting module 13
Module 14 and the transmission gearbox 15 being electrically connected with scrambling module 14.
Scrambling module 14, for carrying out scrambling processing as input using the coded data for encoding the output of selecting module 13.
Specifically, being scrambled to the coded data, it is ensured that DC balance.Due to RapidIO PCS agreements and
The transmission data scrambling mode of 1000Base-X PCS protocol encapsulations is identical, so two kinds of agreements can be multiplexed same scrambling module
14。
Send gearbox 15, for using the scrambled data that scrambling module 14 export as input progress bit width conversion processing and
Frequency conversion process.
Specifically, RapidIO PCS agreements are different with the bit wide of the transmission data of 1000Base-X PCS protocol encapsulations, the
One coding module 11 is 66 to the coded data after being encoded according to the transmission data of RapidIO PCS protocol encapsulations, hair
Send gearbox 15 by 66 data conversions at 40 data；Second coding module 12 according to 1000Base-X PCS to assisting
Coded data after the transmission data of view encapsulation is encoded is 67, sends gearbox 15 by 67 data conversions at 40
The data of position.
The embodiment of the present invention provides PCS protocol multiplexing chips：Transmitting terminal asynchronous FIFO module 16, asynchronous clock choosing
Select module 17 and with the transmitting terminal polarity control module 18 that sends gearbox 15 and be electrically connected, asynchronous clock selecting module 17 connects the
Two enable signal lines 19.
Transmitting terminal asynchronous FIFO module 16, the primary data for being received to transmission path carry out cross clock domain processing.
Asynchronous clock selecting module 17, the second enable signal for receiving the transmission of the second enable signal line 19, described
Cross clock domain processing is carried out to the primary data using transmitting terminal asynchronous FIFO module 16 under the control of second enable signal, and
Obtained transmission data is sent to coding nodes, coding nodes are sent to alternatively, the transmission data is sent to.
Specifically, when the primary data both ends clock that transmission path receives is inconsistent, asynchronous clock selecting module 17
Under the control of second enable signal, cross clock domain is carried out to the primary data using transmitting terminal asynchronous FIFO module 16
Processing, and obtained transmission data is sent to coding nodes；When the clock one at the primary data both ends that transmission path receives
When cause, asynchronous clock selecting module 17 is sent to coding under the control of second enable signal, by obtained transmission data
Node.
Transmitting terminal polarity control module 18, for carrying out reversion processing with the variable rate data for sending the output of gearbox 15.
In another embodiment of the present invention, a kind of PCS protocol multiplexings chip is also provided, it should know, the present invention
The PCS protocol multiplexings chip provided in PCS protocol multiplexings chip and previous embodiment that embodiment provides is used for due to one
Data are encoded in transmission path, one for being decoded to data in receiving path, being that interrelated cannot divide
It opens and uses.Fig. 2 is the structure diagram of another kind PCS protocol multiplexing chips provided in an embodiment of the present invention, as shown in Fig. 2, should
Chip includes：For handling the first decoder module 21 of the reception data according to RapidIO PCS protocol encapsulations, being pressed for handling
The second decoder module 22 according to the reception data of 1000Base-X PCS protocol encapsulations and respectively with the first decoder module 21 and
The decoding selecting module 23 of two decoder modules 22 connection, decoding selecting module 23 connect third enable signal line 20；
First decoder module 21, for being decoded to the reception data in receiving path；
Second decoder module 22, for being decoded to the reception data in receiving path；
Selecting module 23 is decoded, the third enable signal for receiving the transmission of third enable signal line 20, in the third
It is solved using the first decoder module 21 or using the second decoder module 22 to the reception data under the control of enable signal
Code.
Specifically, after decoding selecting module 23 receives the third enable signal of the transmission of third enable signal line 20,
Using the first decoder module 21 to the reception data according to RapidIO PCS protocol encapsulations under the control of the third enable signal
It is decoded, or utilizes the second decoder module 22 to according to 1000Base-X PCS under the control of the third enable signal
The reception data of protocol encapsulation are decoded.
Illustratively, when it is 1 to decode the third enable signal that selecting module 23 receives, the first decoder module 21 is utilized
To being decoded according to the reception data of RapidIO PCS protocol encapsulations；When the third that decoding selecting module 23 receives is enabled
When signal is 0, using the second decoder module 22 to being decoded according to the reception data of 1000Base-X PCS protocol encapsulations.
PCS protocol multiplexings chip provided in an embodiment of the present invention further includes：Receiving terminal polarity control module 24, synchronous head inspection
Module 25 is surveyed, gearbox 26 is received and is electrically connected at the reception gearbox and decodes the descrambling module 27 between node.
Receiving terminal polarity control module 24, for carrying out reversion processing to the primary data for receiving channel reception.
Synchronous head detection module 25, for being carried out using the reversal data that receiving terminal polarity control module 24 exports as input
Packet header detection process.
Specifically, due to a length of 66 of the packet of the data packet of the reception data of RapidIO PCS protocol encapsulations,
A length of 67 of the packet of the data packet of the reception data of 1000Base-X PCS protocol encapsulations, so synchronous head detection module 25 needs
For different agreements come to detecting packet header.
For the data packet of the reception data according to RapidIO PCS protocol encapsulations, synchronous head detection module 25 is with data
A length of 66 of the packet of packet is foundation, carries out packet header detection to receiving data, and then delimit to receiving data；For according to
The data packet of the reception data of 1000Base-X PCS protocol encapsulations, synchronous head detection module 25 is with a length of 67 of the packet of data packet
For foundation, packet header detection is carried out to receiving data, and then delimit to receiving data.
Gearbox 26 is received, is used for using the packet header detection data that synchronous head detection module 25 exports as input to described first
Beginning data carry out bit width conversion processing and frequency conversion process.
Specifically, RapidIO PCS agreements are different with the bit wide of the reception data of 1000Base-X PCS protocol encapsulations, the
One decoder module 21 is 66 to the decoding data after being decoded according to the reception data of RapidIO PCS protocol encapsulations, is connect
Gearbox 26 is received by 66 data conversions into 40 data；Second decoder module 22 according to 1000Base-X PCS to assisting
Decoding data after the reception data of view encapsulation are decoded is 67, receives gearbox 26 by 67 data conversions at 40
The data of position.
Descrambling module 27 will be solved for carrying out scramble process as input using the variable rate data for receiving the output of gearbox 26
It disturbs the reception data obtained after processing and is sent to the decoding node.
PCS protocol multiplexings chip provided in an embodiment of the present invention further includes：The bullet being electrically connected with decoding selecting module 23
Property cache module 28；
Elastic caching module 28, for carrying out frequency departure as input using the decoding data for decoding the output of selecting module 23
Calibration process.
Receive data after the decoding, need to pass to subsequent module, but due to PCS layer use PMA recoveries when
Clock, and subsequent module uses local clock, there may be the frequency deviations centainly given between the two, when volume of transmitted data is larger
When, frequency deviation accumulate can it is very big, so as to cause data overflow.It is inclined according to frequency therefore, it is necessary to define IDLE sequences in the protocol
Corresponding IDLE sequences are deleted in difference increase appropriate, come data overflow problem caused by solving clock frequency deviation.Although RapidIO
There is this mechanism in PCS agreements and 1000Base-X PCS agreements, but for the definition of IDLE sequences difference, so specific
When increasing or deleting IDLE sequences, need to be operated according to different agreement.
Specifically, elastic caching module 28 carries out the IDLE sequences of the decoding data defined in RapidIO PCS agreements
Increase or delete, to realize to frequency departure calibration process；Elastic caching module 28 is to defined in 1000Base-X PCS agreements
The IDLE sequences of decoding data increased or deleted, to realize to frequency departure calibration process.
The present invention can be multiplexed a large amount of modules of 1000Base-X and RapidIO low speed PCS in same framework.Wherein compile
Code, decoder module is entirely different to be multiplexed, and elastic caching causes specifically to increase the operation for deleting IDLE sequences because of agreement difference
Difference can only fractional reuse, the equal reusable of remaining module, such as the following table 2.
Table 2
| Module name | Extent for multiplexing |
| Receiving terminal polarity controls | Multiplexing completely |
| Descrambling | Multiplexing completely |
| Decoding | It cannot be multiplexed |
| Elastic caching | Fractional reuse |
| Transmitting terminal polarity controls | Multiplexing completely |
| Scrambling | Multiplexing completely |
| Coding | It cannot be multiplexed |
| Transmitting terminal asynchronous FIFO | Multiplexing completely |
Compared to the scheme for realizing 1000Base-X and RapidIO low speed PCS is completely independent, the present invention is realizing two kinds
A large amount of logical resource is saved in PCS schemes, reduces chip area, reduces chip power-consumption.
In another embodiment of the present invention, a kind of PCS protocol multiplexings method is also additionally provided, Fig. 3 is that the present invention is implemented
A kind of flow chart for PCS protocol multiplexings method that example provides, this method is using such as above-described embodiment to data in transmission path
The PCS protocol multiplexing chips encoded, as shown in figure 3, this method includes：
Step S100 makes the asynchronous clock selecting module receive the second enabled letter of the second enable signal line transmission
Number, under the control of second enable signal using the transmitting terminal asynchronous FIFO module to the primary data carry out across when
Clock processing, and obtained transmission data is sent to coding nodes, it is sent to coding section alternatively, the transmission data is sent to
Point；
Step S101 makes the coding selecting module receive the first enable signal of the first enable signal line transmission,
Using the first coding module or using the second coding module to the transmission data under the control of first enable signal
It is encoded；
Step S102 makes the scrambling module be added using the coded data of the coding selecting module output as input
Disturb processing；
Step S103 makes the transmission gearbox carry out bit wide using the scrambled data that the scrambling module exports as input
Conversion process and frequency conversion process；
Step S104 makes the transmitting terminal polarity control module be carried out with the variable rate data of the transmission gearbox output anti-
Turn processing.
In another embodiment of the present invention, another PCS protocol multiplexings method is additionally provided, Fig. 4 is that the present invention is implemented
The flow chart for another PCS protocol multiplexings method that example provides, this method apply such as above-described embodiment logarithm in receiving path
According to the PCS protocol multiplexing chips encoded, as shown in figure 4, this method includes：
Step S200 makes the receiving terminal polarity control module carry out at reversion the primary data for receiving channel reception
Reason；
Step S201 makes the synchronous head detection module make with the reversal data that the receiving terminal polarity control module exports
Packet header detection process is carried out for input；
Step S202 makes the reception gearbox using the packet header detection data that the synchronous head detection module exports as defeated
Enter and bit width conversion processing and frequency conversion process are carried out to the primary data；
Step S203 makes the descrambling module be descrambled using the variable rate data of the reception gearbox output as input
Processing, and the reception data obtained after scramble process are sent to the decoding node；
Step S204 makes the decoding selecting module receive the third enable signal of the third enable signal line transmission,
Using the first decoder module or using the second decoder module to the reception data under the control of the third enable signal
It is decoded；
Step S205 makes the elastic caching module to decode the decoding data of selecting module output as inputting into line frequency
The processing of rate deviation calibration.
Coding selecting module described in the embodiment of the present invention makes in receive the first enable signal line transmission first
After energy signal, using the first coding module to according to RapidIO PCS protocol encapsulations under the control of first enable signal
Transmission data carry out encode or using the second coding module to the transmission data according to 1000Base-X PCS protocol encapsulations
It is encoded.
PCS protocol multiplexings chip provided in an embodiment of the present invention can be realized under same framework according to RapidIO PCS
The transmission of the data of agreement and 1000Base-X PCS protocol encapsulations, saves a large amount of logical resources, reduces the use of chip
Cost.
In practical applications, a kind of PCS protocol multiplexings method provided by the invention may comprise steps of：
1, the data in transmission path need to carry out after the PCS for entering the present invention if both ends clock is inconsistent
Cross clock domain operates, and the asynchronous FIFO that data are sent into transmitting terminal completes cross clock domain processing；Otherwise data directly around.
Although 2, low speed 1000Base-X and RapidIO PCS uses 8b/10b to encode, specific coding mode is not
It is identical.So data before entering coding module, need to select accordingly according to the register value of agreement is realized in table 1
Coding module.
3, data after coding, can be scrambled, to ensure DC balance.It must be into for 6.25G RapidIO
Row scrambling；Remaining rate can scramble, and can not also scramble, be determined by register configuration.1000Base-X need not be added
Operation is disturbed, it can be directly around.
4, transmitting terminal polarity control module is inverted for controlling whether, two kinds of agreements are required to realize, it is possible to multiple
With.
In practical applications, another kind PCS protocol multiplexing methods provided by the invention may comprise steps of：
1, the data in receiving path will enter receiving polarity control module, to control after the PCS for entering the present invention
System whether reversed polarity.
2, data are after by receiving polarity control module, in this case it is not apparent which data form a data packet, institute
To be delimited to receiving data, then send the data to descrambling module.
3, the data in receiving path need to complete in receiving side corresponding if be scrambled in transmitting terminal
Descrambling, can just obtain correct data.The data of 6.25G RapidIO centainly have passed through scrambling when sending, so receiving
End must also be descrambled, and whether other rates need descrambling to be determined by register configuration.1000Base-X does not have in transmitting terminal
There is scrambling, in receiving terminal without descrambling, directly around.
4, data need to be decoded after descrambling, although 1000Base-X and RapidIO are all made of 8b/10b and compile solution
Code, but respectively the specific decoding process of agreement is different, so needing to choose corresponding decoder module according to the agreement of actual selection.
5, data after the decoding, need to pass to subsequent module.But the clock for using PMA recoveries due to PCS layers,
And subsequent module uses local clock, there may be certain frequency deviations between the two.When volume of transmitted data is larger, frequency
Partially accumulate can it is very big, so as to cause data overflow.It is suitable according to frequency departure therefore, it is necessary to define IDLE sequences in the protocol
When increase or delete corresponding IDLE sequences, data overflow problem caused by solve clock frequency deviation.1000Base-X and
There is this mechanism in RapidIO agreements, but for the definition of IDLE sequences difference, so specifically increasing or deleting IDLE sequences
When row, need to be operated according to different agreement.
PCS protocol multiplexings method provided by the invention.Since the transmission rate of 1000Base-X and RapidIO is different, institute
With the write-in side clock of receiving side clock and transmitting terminal asynchronous FIFO for local clock i.e. elastic caching module, need
Different clocks is selected according to different agreements.
Flow chart and block diagram in attached drawing show the system, method and computer journey of multiple embodiments according to the present invention
The architecture, function and operation in the cards of sequence product.In this regard, each box in flowchart or block diagram can generation
A part for a part for one module, section or code of table, the module, section or code includes one or more uses
The executable instruction of the logic function as defined in realization.It should also be noted that in some implementations as replacements, being marked in box
The function of note can also occur in a different order than that indicated in the drawings.For example, two continuous boxes can essentially base
Originally it is performed in parallel, they can also be executed in the opposite order sometimes, this is depended on the functions involved.It is also noted that
It is the combination of each box in block diagram and or flow chart and the box in block diagram and or flow chart, can uses and execute rule
The dedicated hardware based system of fixed function or action is realized, or can use the group of specialized hardware and computer instruction
It closes to realize.
In addition, in the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
Can also be electrical connection to be mechanical connection；It can be directly connected, can also indirectly connected through an intermediary, Ke Yishi
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
In the description of the present invention, it should be noted that term "center", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for the description present invention and simplify description, do not indicate or imply the indicated device or element must have a particular orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for description purposes only, and is not understood to indicate or imply relative importance.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.The apparatus embodiments described above are merely exemplary, for example, the division of the unit,
Only a kind of division of logic function, formula that in actual implementation, there may be another division manner, in another example, multiple units or component can
To combine or be desirably integrated into another system, or some features can be ignored or not executed.Another point, it is shown or beg for
The mutual coupling, direct-coupling or communication connection of opinion can be by some communication interfaces, device or unit it is indirect
Coupling or communication connection can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it can also
It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in the executable non-volatile computer read/write memory medium of a processor.Based on this understanding, of the invention
Technical solution substantially the part of the part that contributes to existing technology or the technical solution can be with software in other words
The form of product embodies, which is stored in a storage medium, including some instructions use so that
One computer equipment (can be personal computer, server or the network equipment etc.) executes each embodiment institute of the present invention
State all or part of step of method.And storage medium above-mentioned includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-
Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can be with
Store the medium of program code.
Finally it should be noted that：Embodiment described above, only specific implementation mode of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, it will be understood by those of ordinary skill in the art that：Any one skilled in the art
In the technical scope disclosed by the present invention, it can still modify to the technical solution recorded in previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover the protection in the present invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of PCS protocol multiplexings chip, which is characterized in that including：For handling the hair according to RapidIO PCS protocol encapsulations
The first coding module, the second coding mould for handling the transmission data according to 1000Base-X PCS protocol encapsulations for sending data
Block, the coding selecting module being connect respectively with first coding module and second coding module, the coding select mould
Block connects the first enable signal line；
First coding module, for being encoded to the transmission data in transmission path；
Second coding module, for being encoded to the transmission data in transmission path；
The coding selecting module, the first enable signal for receiving the first enable signal line transmission, described first
Under the control of enable signal using first coding module or using second coding module to the transmission data into
Row coding.
2. PCS protocol multiplexings chip according to claim 1, which is characterized in that further include：With the coding selecting module
The scrambling module of electric connection and the transmission gearbox being electrically connected with the scrambling module；
The scrambling module, for carrying out scrambling processing as input using the coded data of the coding selecting module output；
The transmission gearbox, for using the scrambled data that the scrambling module export as input progress bit width conversion processing and
Frequency conversion process.
3. PCS protocol multiplexings chip according to claim 2, which is characterized in that further include：Transmitting terminal asynchronous FIFO mould
Block, asynchronous clock selecting module and the transmitting terminal polarity control module being electrically connected with the transmission gearbox, when described asynchronous
Clock selecting module connects the second enable signal line；
The transmitting terminal asynchronous FIFO module, the primary data for being received to transmission path carry out cross clock domain processing；
The asynchronous clock selecting module, the second enable signal for receiving the second enable signal line transmission, described
Cross clock domain processing is carried out to the primary data using the transmitting terminal asynchronous FIFO module under the control of second enable signal,
And obtained transmission data is sent to coding nodes, it is sent to coding nodes alternatively, the transmission data is sent to；
The transmitting terminal polarity control module, for carrying out reversion processing with the variable rate data of the transmission gearbox output.
4. a kind of PCS protocol multiplexings chip, which is characterized in that including：For handling connecing according to RapidIO PCS protocol encapsulations
The first decoder module, the second decoding mould for handling the reception data according to 1000Base-X PCS protocol encapsulations for receiving data
Block and the decoding selecting module being connect respectively with first decoder module and second decoder module, the decoding select mould
Block connects third enable signal line；
First decoder module, for being decoded to the reception data in receiving path；
Second decoder module, for being decoded to the reception data in receiving path；
The decoding selecting module, the third enable signal for receiving the third enable signal line transmission, in the third
Under the control of enable signal using first decoder module or using second decoder module to the reception data into
Row decoding.
5. PCS protocol multiplexings chip according to claim 4, which is characterized in that further include：Receiving terminal polarity controls mould
Block, synchronous head detection module receive gearbox and are electrically connected at the reception gearbox and decode the descrambling mould between node
Block；
The receiving terminal polarity control module, for carrying out reversion processing to the primary data for receiving channel reception；
The synchronous head detection module, for being carried out using the reversal data that the receiving terminal polarity control module exports as input
Packet header detection process；
The reception gearbox is used for using the packet header detection data that the synchronous head detection module exports as input to described first
Beginning data carry out bit width conversion processing and frequency conversion process；
The descrambling module will be solved for carrying out scramble process as input using the variable rate data of the reception gearbox output
It disturbs the reception data obtained after processing and is sent to the decoding node.
6. PCS protocol multiplexings chip according to claim 5, which is characterized in that further include：With the decoding selecting module
The elastic caching module of electric connection；
The elastic caching module, for carrying out frequency departure as input using the decoding data of the decoding selecting module output
Calibration process.
7. a kind of PCS protocol multiplexings method, which is characterized in that apply PCS protocol multiplexings chip as claimed in claim 3, institute
The method of stating includes：
The coding selecting module is set to receive the first enable signal of the first enable signal line transmission, it is enabled described first
The transmission data is compiled using first coding module or using second coding module under the control of signal
Code.
8. PCS protocol multiplexings method according to claim 7, which is characterized in that the method further includes：
The asynchronous clock selecting module is set to receive the second enable signal of the second enable signal line transmission, described second
Using the transmitting terminal asynchronous FIFO module to across the clock processing of primary data progress under the control of enable signal, and will
To transmission data be sent to coding nodes, alternatively, the transmission data is sent to coding nodes；
The scrambling module is set to carry out scrambling processing as input using the coded data of the coding selecting module output；
The transmission gearbox is set to carry out bit width conversion processing and frequency using the scrambled data that the scrambling module exports as input
Rate conversion process；
The transmitting terminal polarity control module is set to carry out reversion processing with the variable rate data of the transmission gearbox output.
9. a kind of PCS protocol multiplexings method, which is characterized in that apply PCS protocol multiplexings chip as claimed in claim 6, institute
The method of stating includes：
The decoding selecting module is set to receive the third enable signal of the third enable signal line transmission, it is enabled in the third
It is solved using first decoder module or using second decoder module to the reception data under the control of signal
Code.
10. PCS protocol multiplexings method according to claim 9, which is characterized in that the method further includes：
The elastic caching module is set to be carried out at frequency departure calibration as input using the decoding data for decoding selecting module output
Reason；
The receiving terminal polarity control module is set to carry out reversion processing to the primary data for receiving channel reception；
The synchronous head detection module is set to be wrapped using the reversal data that the receiving terminal polarity control module exports as input
Head detection process；
Make the reception gearbox using the packet header detection data that the synchronous head detection module exports as input to described initial
Data carry out bit width conversion processing and frequency conversion process；
The descrambling module is set to carry out scramble process using the variable rate data of the reception gearbox output as input, and will descrambling
The reception data obtained after processing are sent to the decoding node.
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