CN108521430A - Double protocol multiplexing chips and double protocol multiplexing methods - Google Patents
Double protocol multiplexing chips and double protocol multiplexing methods Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
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Abstract
The present invention provides a kind of double protocol multiplexing chips and double protocol multiplexing methods, belong to network communication technology field.Wherein, double protocol multiplexing chips include：Support the first coding module of 16G Fiber Channel PCS agreements, support the second coding module of 10.3125G Serial RapidIO PCS agreements, the coding selecting module being connect respectively with the first coding module and the second coding module, support the first decoder module of 16G Fiber Channel PCS agreements, support the second decoder module of 10.3125G Serial RapidIO PCS agreements, the decoding selecting module being connect respectively with the first decoder module and the second decoder module, coding selecting module connects the first enable signal line, decoding selecting module connects the second enable signal line.Double protocol multiplexing chips provided in an embodiment of the present invention and double protocol multiplexing methods, it can be under same framework, realize the transmission according to 16G Fiber Channel PCS agreements and the data of 10.3125G Serial RapidIO PCS protocol encapsulations, a large amount of logical resources are saved, the use cost of chip is reduced.
Description
Technical field
The present invention relates to network communication technology fields, multiple in particular to a kind of double protocol multiplexing chips and double agreements
Use method.
Background technology
Fiber Channel (optical-fibre channel) countings are that one kind can be the applications such as storage device, IP data networks, audio stream
The backbone network technology of high speed data transfer is provided.By development for many years, have become now one it is complete, high speed,
The network technology of high scalability.
RapidIO (high speed interconnection interface) technology is mainly directed towards the interconnected communication of high performance embedded system, compares Ethernet
Efficiency of transmission higher.And due to having more perfect consideration in RapidIO routings, exchange, fault-tolerant error correction, ease of use,
Hardware based high-performance reliable data transmission may be implemented.
Fiber Channel and RapidIO are to have widely applied agreement, under some complex application contexts, are needed
It wants to realize two kinds of agreements of Fiber Channel and RapidIO, and switching at runtime can be carried out between the two.Existing skill
Art is to realize two kinds of agreements respectively, that is, under same framework, be only capable of that 16G is implemented separately when solving the problems, such as this
Fiber Channel PCS (16GBase Fiber Channel Physical Coding Sublayer, 16G optical-fibre channels
Physical Coding Sublayer) agreement or 10.3125G Serial RapidIO PCS (10.3125G Serial are implemented separately
The serial high speed interconnection interface Physical Coding Sublayers of RapidIO Physical Coding Sublayer, 10.3125G) under agreement
Data transmission, occupy a large amount of logical resources, increase the use cost of chip.
Invention content
For the above-mentioned prior art the problem of, the present invention provides a kind of double protocol multiplexing chips and double agreements are multiple
With method, to alleviate the high problem of logical resource waste existing in the prior art, chip use cost.
In a first aspect, an embodiment of the present invention provides a kind of double protocol multiplexing chips, including：Support 16GFiber
First coding module of Channel PCS agreements supports the second coding mould of 10.3125G Serial RapidIO PCS agreements
Block, the coding selecting module being connect respectively with first coding module and second coding module support 16G Fiber
First decoder module of Channel PCS agreements supports the second decoding mould of 10.3125G Serial RapidIO PCS agreements
Block, the decoding selecting module being connect respectively with first decoder module and the second decoder module, the coding selecting module connect
First enable signal line, the decoding selecting module connect the second enable signal line；
First coding module and the second coding module, for being encoded to the transmission data in transmission path；Institute
The first decoder module and the second decoder module are stated, for being decoded to the reception data in receiving path；
The coding selecting module, the first enable signal for receiving the first enable signal line transmission, described
The transmission data is compiled using first coding module or the second coding module under the control of first enable signal
Code；
The decoding selecting module, the second enable signal for receiving the second enable signal line transmission, described
The reception data are solved using first decoder module or the second decoder module under the control of second enable signal
Code.
With reference to first aspect, an embodiment of the present invention provides the first possible embodiments of first aspect, wherein institute
State chip further include the scrambling module being connect with first coding module and the second coding module and with the scrambling module
The transmission gearbox of connection；
The scrambling module, for using the coded data that first coding module or the second coding module export as defeated
Enter to carry out scrambling processing；
The transmission gearbox, for being carried out at bit width conversion using the scrambled data that the scrambling module exports as input
Reason and frequency conversion process.
The possible embodiment of with reference to first aspect the first, an embodiment of the present invention provides second of first aspect
Possible embodiment, wherein the chip further includes：Transmitting terminal asynchronous FIFO module and asynchronous clock selecting module；
The input terminal of the transmitting terminal asynchronous FIFO module is connect with the asynchronous clock selecting module, and the transmitting terminal is different
The output end of step fifo module is connect with the coding selecting module, the progress of primary data for being received to transmission path across
Clock domain processing；
The asynchronous clock selecting module connects third enable signal line, for receiving the third enable signal line transmission
Third enable signal, using the transmitting terminal asynchronous FIFO module to described initial under the control of the third enable signal
Data carry out cross clock domain processing, and obtained transmission data is sent to coding selecting module.
With reference to first aspect, an embodiment of the present invention provides the third possible embodiments of first aspect, wherein institute
It further includes the transmitting terminal polarity control module being connect with the transmission gearbox to state chip；
The transmitting terminal polarity control module, for being carried out at reversion with the variable rate data of the transmission gearbox output
Reason.
With reference to first aspect, an embodiment of the present invention provides the 4th kind of possible embodiments of first aspect, wherein institute
Chip is stated to further include sequentially connected receiving terminal polarity control module, synchronous head detection module, receive gearbox and descrambling module；
The receiving terminal polarity control module, for carrying out reversion processing to the primary data for receiving channel reception；
The synchronous head detection module, for using the reversal data that the receiving terminal polarity control module exports as input
Carry out packet header detection process；
The reception gearbox is used for using the packet header detection data that the synchronous head detection module exports as input to institute
It states primary data and carries out bit width conversion processing and frequency conversion process；
The descrambling module, for carrying out scramble process as input using the variable rate data of the reception gearbox output,
The reception data obtained after scramble process are sent to the decoding selecting module.
The 4th kind of possible embodiment with reference to first aspect, an embodiment of the present invention provides the 5th kind of first aspect
Possible embodiment, wherein the chip further includes：The elasticity being connect with first decoder module and the second decoder module
Cache module；
The elastic caching module, the decoding data for being exported with first decoder module or the second decoder module are made
Frequency departure calibration process is carried out for input.
Second aspect, the embodiment of the present invention additionally provide a kind of double protocol multiplexing methods, and it is multiple to be applied to above-mentioned double agreements
With chip, the method includes：
When there are data to be sent, the coding selecting module is made to receive the first of the first enable signal line transmission
Enable signal, using first coding module or the second coding module to described under the control of first enable signal
Transmission data is encoded；
When data is received, make the decoding selecting module receive the second of the second enable signal line transmission to enable
Signal, using first decoder module or the second decoder module to the reception under the control of second enable signal
Data are decoded.
In conjunction with second aspect, an embodiment of the present invention provides the first possible embodiments of second aspect, wherein institute
The method of stating further includes：
When there are data to be sent, the asynchronous clock selecting module is made to receive the third enable signal line transmission
Third enable signal, using the transmitting terminal asynchronous FIFO module to the initial number under the control of the third enable signal
According to across the clock processing of progress, and obtained transmission data is sent to coding selecting module.
In conjunction with the first possible embodiment of second aspect, an embodiment of the present invention provides second of second aspect
Possible embodiment, wherein after the first coding module or the second coding module encode the transmission data,
The method further includes：
The scrambling module is set to carry out scrambling processing as input using the coded data of the coding selecting module output；
The transmission gearbox is set to carry out bit width conversion processing using the scrambled data that the scrambling module exports as input
And frequency conversion process；
The transmitting terminal polarity control module is set to carry out reversion processing with the variable rate data of the transmission gearbox output.
In conjunction with second aspect, an embodiment of the present invention provides the third possible embodiments of second aspect, wherein institute
The method of stating further includes：
When data is received, the receiving terminal polarity control module is made to carry out the primary data for receiving channel reception anti-
Turn processing；
Make the synchronous head detection module using the reversal data that the receiving terminal polarity control module exports as input into
Row packet header detection process；
Make the reception gearbox using the packet header detection data that the synchronous head detection module exports as input to described
Primary data carries out bit width conversion processing and frequency conversion process；
The descrambling module is set to carry out scramble process using the variable rate data of the reception gearbox output as input, and will
The reception data obtained after scramble process are sent to the decoding selecting module, so that the decoding selecting module utilizes described the
One decoder module or the second decoder module are decoded the reception data；
After the first decoder module or the second decoder module are decoded the reception data, keep the elasticity slow
Storing module carries out frequency departure calibration process using the decoding data for decoding selecting module output as input.
The embodiment of the present invention brings following advantageous effect：
Double protocol multiplexing chips provided in an embodiment of the present invention and double protocol multiplexing methods, can be real under same framework
Now according to the biography of 16G Fiber Channel PCS agreements and the data of 10.3125G Serial RapidIOPCS protocol encapsulations
It is defeated, a large amount of logical resources are saved, the use cost of chip is reduced.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages are in specification, claims
And specifically noted structure is realized and is obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate
Appended attached drawing, is described in detail below.
Description of the drawings
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, in being described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, other drawings may also be obtained based on these drawings.
The structure diagram for double protocol multiplexing chips that Fig. 1 is provided by one embodiment of the invention；
The flow chart of transmission data in double protocol multiplexing methods that Fig. 2 is provided by one embodiment of the invention；
The flow chart of data is received in double protocol multiplexing methods that Fig. 3 is provided by another embodiment of the present invention.
Icon：10- third enable signal lines；11- asynchronous clock selecting modules；12- transmitting terminal asynchronous FIFO modules；13-
First enable signal line；14- encodes selecting module；The first coding modules of 15-；The second coding modules of 16-；17- scrambling modules；
18- sends gearbox；19- transmitting terminal polarity control modules；20- receiving terminal polarity control modules；21- synchronous head detection modules；
22- receives gearbox；23- allays sorrow module；24- decodes selecting module；The first decoder modules of 25-；The second decoder modules of 26-；27-
Elastic caching module；28- the second enable signal lines.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.The component of embodiments of the present invention, which are generally described and illustrated herein in the accompanying drawings can be matched with a variety of different
It sets to arrange and design.Therefore, the detailed description of the embodiment of the present invention to providing in the accompanying drawings is not intended to limit below
The range of claimed invention, but it is merely representative of the selected embodiment of the present invention.Based on the embodiments of the present invention, originally
The every other embodiment that field those of ordinary skill is obtained without making creative work, belongs to the present invention
The range of protection.
Be only capable of under same framework individually supporting for the prior art 16G Fiber Channel PCS agreements or
The problem of 10.3125G Serial RapidIO PCS agreements, an embodiment of the present invention provides a kind of double protocol multiplexing chips and
Double protocol multiplexing methods can be multiplexed 16G Fiber Channel PCS and 10.3125G Serial in same framework
RapidIO PCS.It describes in detail first to double protocol multiplexing chips of the present invention below.
Fig. 1 shows the structure diagram for double protocol multiplexing chips that one embodiment of the invention is provided, as shown in Figure 1, this
Inventive embodiments provide a kind of double protocol multiplexing chips, as shown in Figure 1, double protocol multiplexing chips include：Support 16G
First coding module 15 of Fiber Channel PCS agreements supports the of 10.3125G Serial RapidIO PCS agreements
Two coding modules 16, the coding selecting module 14 being connect respectively with the first coding module 15 and the second coding module 16, for connecting
The asynchronous clock selecting module 11 of third enable signal line 10 is connect, the transmitting terminal being connect with asynchronous clock selecting module 11 is asynchronous
Fifo module 12, the scrambling module 17 being connect with the first coding module 15 and the second coding module 16 and sequentially connected transmission
Gearbox 18 and transmitting terminal polarity control module 19.
Asynchronous clock selecting module 11 connects third enable signal line 10, for receiving the transmission of third enable signal line 10
Third enable signal, under the control of third enable signal using transmitting terminal asynchronous FIFO module 12 to primary data carry out across when
Clock domain is handled, and obtained transmission data is sent to coding selecting module 14.
The input terminal of transmitting terminal asynchronous FIFO module 12 is connect with the asynchronous clock selecting module 11, and transmitting terminal is asynchronous
The output end of fifo module 12 connect with coding selecting module 14, the progress of primary data for being received to transmission path across when
Clock domain is handled.
Coding selecting module 14 is used to receive the first enable signal of the first enable signal line 13 transmission, in the first enabled letter
Number control under transmission data is encoded using the first coding module 15 or the second coding module 16.For example, when coding
When the first enable signal that selecting module 14 receives is 1, transmission data is encoded using the first coding module 15；Work as volume
When the first enable signal that code selecting module 14 receives is 0, transmission data is encoded using the second coding module 16.
First coding module 15 is used for the standard using 16G Fiber Channel PCS agreements to the hair in transmission path
Data are sent to be encoded.16G Fiber Channel PCS agreements are fiber channel agreement.
Second coding module 16 is used for the standard using 10.3125G Serial RapidIO PCS agreements to transmission path
In transmission data encoded.10.3125G Serial RapidIO PCS agreements are that the high speed of high speed serialization transceiver is received
Agreement of the hair device module in Physical Coding Sublayer.
Scrambling module 17 is used for using the coded data that the first coding module 15 or the second coding module 16 export as input
Carry out scrambling processing.
Send gearbox 18 be used for using the scrambled data that scrambling module 17 export as input progress bit width conversion processing and
Frequency conversion process.
Transmitting terminal polarity control module 19 is used to carry out reversion processing with the variable rate data for sending the output of gearbox 18.
The chip further includes：It supports the first decoder module 25 of 16G Fiber Channel PCS agreements, supports
Second decoder module 26 of 10.3125G Serial RapidIO PCS agreements and the control of sequentially connected receiving terminal polarity
Module 20, synchronous head detection module 21 receive gearbox 22, descrambling module 23 and decoding selecting module 24, with the first decoding mould
The elastic caching module 27 of block 25 and the connection of the second decoder module 26.
Receiving terminal polarity control module 20 is used to carry out reversion processing to the primary data for receiving channel reception.
Synchronous head detection module 21 is used to be wrapped using the reversal data that receiving terminal polarity control module exports as input
Head detection process.
Gearbox 22 is received to be used for using the packet header detection data that synchronous head detection module 21 exports as input to initial number
According to progress bit width conversion processing and frequency conversion process.
Descrambling module 23 is used to carry out scramble process as input using the variable rate data for receiving gearbox output, at descrambling
The reception data obtained after reason are sent to decoding selecting module 24.
Decoding selecting module 24 is connect with the first decoder module 25 and the second decoder module 26 respectively, and connects the second enabled letter
Number line 28, the second enable signal for receiving the transmission of the second enable signal line 28, the profit under the control of the second enable signal 28
It is decoded with the first decoder module 25 or the second decoder module 26 to receiving data.
First decoder module 25 is used for the standard according to 16G Fiber Channel PCS agreements to connecing in receiving path
Data are received to be decoded.
Second decoder module 26 is used for the standard according to 10.3125G Serial RapidIO PCS agreements to receiving path
In reception data be decoded.
Elastic caching module 27 be used for using the decoding data that the first decoder module 25 or the second decoder module 26 export as
Input carries out frequency departure calibration process.
Process using double protocol multiplexing chip transmission datas provided in an embodiment of the present invention is：
1, the data of transmission path, after the PCS for entering the present invention, if clock inconsistent needs in both ends are across clock
Domain is put into transmitting terminal asynchronous FIFO and carrys out cross clock domain；Otherwise it is directly entered and bypasses.
2, due to the coding mode of 16G Fiber Channel and 10.3125G Serial RapidIO difference, 16G
Fiber Channel use 64/66b coding modes, 10.3125G Serial RapidIO to use 64/67b coding modes.Institute
With data before entering coding module, the value according to the register of characterization realization agreement is needed to select to encode mould accordingly
Block.
3, data after coding, are scrambled, to ensure DC balance.Due to 16G Fiber Channel and
The scrambling mode of 10.3125G Serial RapidIO is identical, it is possible to be multiplexed the same scrambling module.
4, data after scrambling, need, by gearbox, to come change data bit wide and clock frequency, so that PMA is carried out
Subsequent processing.Since the data bit width after 16G Fiber Channel codings is 66, and 16G Fiber Channel are compiled
Data bit width after code is 67, sends gearbox to need the data for being 40 at bit wide by corresponding data conversion.
5, transmitting terminal polarity control module is inverted for controlling whether, two kinds of agreements are required to realize, it is possible to multiple
With.
The process that data are received using double protocol multiplexing chips provided in an embodiment of the present invention is：
1, the data of receiving path will enter receiving polarity control module, to control into after the PCS of the present invention
Whether reversed polarity.
2, data are after by receiving polarity control module, in this case it is not apparent which data form a data packet, institute
To need, by detecting packet header, to delimit to receiving data, and to be adjusted clock and bit wide.Due to 16G Fiber
The coding mode of Channel PCS and 10.3125G Serial RapidIO two kinds of agreements of PCS is inconsistent, i.e. two kinds of agreements
The packet length of each data packet it is different (a length of 67 of the packet of 10.3125G Serial RapidIO, 16G Fiber Channel's
Wrap a length of 66).So receiving gearbox and synchronous head detection module, need to detect packet header for different agreements, and turn
The data for changing corresponding bit wide into are sent to descrambling module.
3, the data of receiving path need, by descrambling, real data can be just obtained, due to 16G Fiber
The descrambling mode of Channel with 10.3125G Serial RapidIO is identical, it is possible to be multiplexed the same descrambling module.
4, data need to be decoded after descrambling, due to 16G Fiber Channel and 10.3125G Serial
The decoding process of RapidIO is different, and 16G Fiber Channel use 64/66b decoding processes, 10.3125G Serial
RapidIO uses 64/67b decoding processes, so according to the corresponding decoder module of difference selection for realizing agreement.
5, data after the decoding, need to pass to subsequent module.But the clock for using PMA recoveries due to PCS layers,
And subsequent module uses local clock, there may be the frequency deviations centainly given between the two.When volume of transmitted data is larger,
Frequency deviation accumulate can it is very big, so as to cause data overflow.It, can be according to frequency therefore, it is necessary to define IDLE sequences in the protocol
Corresponding IDLE sequences are deleted in deviation increase appropriate, come data overflow problem caused by solving clock frequency deviation.16G Fiber
There is this mechanism in Channel and 10.3125G Serial RapidIO agreements, but different for the definition of IDLE sequences,
So when specifically increasing or deleting IDLE sequences, need to be operated according to different agreement.
The embodiment of the present invention can be multiplexed 16G Fiber Channel PCS and 10.3125G in same framework
A large amount of modules of Serial RapidIO PCS.Except coding, coding/decoding module is entirely different to be multiplexed, and sends gearbox and connects
Receive gearbox and synchronous head detection module because two kinds of PCS bit wides differences can only fractional reuse, elastic caching causes because of agreement difference
It is specific increase delete IDLE sequences operation difference can only fractional reuse, the equal reusable of remaining module, as shown in the table.
| Module name | Extent for multiplexing |
| Receiving terminal polarity controls | Multiplexing completely |
| Receive gearbox and synchronous head detection | Fractional reuse |
| Descrambling | Multiplexing completely |
| Decoding | It cannot be multiplexed |
| Elastic caching | Fractional reuse |
| Transmitting terminal polarity controls | Multiplexing completely |
| Send gearbox | Fractional reuse |
| Scrambling | Multiplexing completely |
| Coding | It cannot be multiplexed |
| Transmitting terminal asynchronous FIFO | Multiplexing completely |
The embodiment of the present invention additionally provides a kind of double protocol multiplexing methods, as shown in Figures 2 and 3.This method includes：
Step S201 makes asynchronous clock selecting module receive the transmission of third enable signal line when there are data to be sent
Third enable signal, under the control of third enable signal using the transmitting terminal asynchronous FIFO module to primary data carry out
Across clock processing, and obtained transmission data is sent to coding selecting module；
Step S202 makes coding selecting module receive the first enable signal of the first enable signal line transmission, in institute
It states and the transmission data is encoded using the first coding module or the second coding module under the control of the first enable signal；
Step S203 makes scrambling module carry out scrambling processing as input using the coded data for encoding selecting module output；
Step S204 makes transmission gearbox carry out bit width conversion processing using the scrambled data that scrambling module exports as input
And frequency conversion process；
Step S205 makes transmitting terminal polarity control module with the variable rate data for sending gearbox output and carries out reversion processing；
Step S301 makes primary data of the receiving terminal polarity control module to reception channel reception when data is received
Carry out reversion processing；
Step S302, make synchronous head detection module using the reversal data that receiving terminal polarity control module exports as input into
Row packet header detection process；
Step S303 makes reception gearbox using the packet header detection data that synchronous head detection module exports as input to initial
Data carry out bit width conversion processing and frequency conversion process；
Step S304 makes descrambling module carry out scramble process as input using the variable rate data for receiving gearbox output, and
The reception data obtained after scramble process are sent to decoding selecting module；
Step S305 makes decoding selecting module receive the second enable signal of the second enable signal line transmission, described the
It is decoded using the first decoder module or the second decoder module to receiving data under the control of two enable signals；
Step S306 makes elasticity after the first decoder module or the second decoder module are decoded reception data
Cache module carries out frequency departure calibration process using the decoding data for decoding selecting module output as input.
The embodiment of the present invention can indicate to realize specified agreement, 16G realized in same frame by register configuration
Fiber Channel PCS and 10.3125G Serial RapidIO PCS；By selecting different codings, decoder module, with
The coding of agreement, decoding needed for realizing；It is controlled by register, realizes and send gearbox and reception gearbox and synchronous head detection
Module adapts to the bit wide of respective protocol；Enable elastic caching module to 16G Fiber Channel PCS and 10.3125G
The support of Serial RapidIO two kinds of agreements of PCS.
Double protocol multiplexing chips provided in an embodiment of the present invention and double protocol multiplexing methods technical characteristic having the same, institute
Can also solve identical technical problem, reach identical technique effect.
It should be noted that in embodiment provided by the present invention, it should be understood that disclosed system and method, it can
To realize by another way.The apparatus embodiments described above are merely exemplary, for example, the unit is drawn
Point, only a kind of division of logic function, formula that in actual implementation, there may be another division manner, in another example, multiple units or group
Part can be combined or can be integrated into another system, or some features can be ignored or not executed.It is described to be used as separation unit
The unit that part illustrates may or may not be physically separated, and the component shown as unit can be or also may be used
Not to be physical unit, you can be located at a place, or may be distributed over multiple network units.It can be according to reality
Needs some or all of the units may be selected to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in embodiment provided by the invention can be integrated in a processing unit, also may be used
It, can also be during two or more units be integrated in one unit to be that each unit physically exists alone.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer read/write memory medium.Based on this understanding, technical scheme of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be expressed in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-OnlyMemory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic disc or CD.
In addition, term " first ", " second ", " third " are used for description purposes only, it is not understood to indicate or imply phase
To importance.
Finally it should be noted that：Embodiment described above, only specific implementation mode of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, it will be understood by those of ordinary skill in the art that：Any one skilled in the art
In the technical scope disclosed by the present invention, it can still modify to the technical solution recorded in previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover the protection in the present invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of double protocol multiplexing chips, which is characterized in that including：Support the first of 16G Fiber Channel PCS agreements
Coding module supports the second coding module of 10.3125G Serial RapidIO PCS agreements, is encoded respectively with described first
The coding selecting module that module is connected with second coding module supports the first of 16G Fiber Channel PCS agreements
Decoder module supports the second decoder module of 10.3125G Serial RapidIO PCS agreements, is decoded respectively with described first
The decoding selecting module that module is connected with the second decoder module, the coding selecting module connect the first enable signal line, the solution
Code selecting module connects the second enable signal line；
First coding module and the second coding module, for being encoded to the transmission data in transmission path；Described
One decoder module and the second decoder module, for being decoded to the reception data in receiving path；
The coding selecting module, the first enable signal for receiving the first enable signal line transmission, described first
The transmission data is encoded using first coding module or the second coding module under the control of enable signal；
The decoding selecting module, the second enable signal for receiving the second enable signal line transmission, described second
The reception data are decoded using first decoder module or the second decoder module under the control of enable signal.
2. double protocol multiplexing chips according to claim 1, which is characterized in that the chip further includes being compiled with described first
Code module and the second coding module scrambling module connected and the transmission gearbox being connect with the scrambling module；
The scrambling module, for using first coding module or the second coding module output coded data as input into
Row scrambling is handled；
The transmission gearbox, for using the scrambled data that the scrambling module export as input progress bit width conversion processing and
Frequency conversion process.
3. double protocol multiplexing chips according to claim 2, which is characterized in that the chip further includes：Transmitting terminal is asynchronous
Fifo module and asynchronous clock selecting module；
The input terminal of the transmitting terminal asynchronous FIFO module is connect with the asynchronous clock selecting module, and the transmitting terminal is asynchronous
The output end of fifo module is connect with the coding selecting module, primary data for being received to transmission path carry out across when
Clock domain is handled；
The asynchronous clock selecting module connects third enable signal line, and for receiving the third enable signal line transmission
Three enable signals, using the transmitting terminal asynchronous FIFO module to the primary data under the control of the third enable signal
Cross clock domain processing is carried out, and obtained transmission data is sent to coding selecting module.
4. double protocol multiplexing chips according to claim 1, which is characterized in that the chip further includes becoming with the transmission
The transmitting terminal polarity control module of fast case connection；
The transmitting terminal polarity control module, for carrying out reversion processing with the variable rate data of the transmission gearbox output.
5. double protocol multiplexing chips according to claim 1, which is characterized in that the chip further includes sequentially connected connects
Receiving end polarity control module, receives gearbox and descrambling module at synchronous head detection module；
The receiving terminal polarity control module, for carrying out reversion processing to the primary data for receiving channel reception；
The synchronous head detection module, for being carried out using the reversal data that the receiving terminal polarity control module exports as input
Packet header detection process；
The reception gearbox is used for using the packet header detection data that the synchronous head detection module exports as input to described first
Beginning data carry out bit width conversion processing and frequency conversion process；
The descrambling module will be solved for carrying out scramble process as input using the variable rate data of the reception gearbox output
It disturbs the reception data obtained after processing and is sent to the decoding selecting module.
6. double protocol multiplexing chips according to claim 5, which is characterized in that the chip further includes：With described first
The elastic caching module of decoder module and the connection of the second decoder module；
The elastic caching module, for using the decoding data that first decoder module or the second decoder module export as defeated
Enter to carry out frequency departure calibration process.
7. a kind of double protocol multiplexing methods are applied to double protocol multiplexing chips according to any one of claims 1 to 6, special
Sign is, the method includes：
When there are data to be sent, so that the coding selecting module is received the first of the first enable signal line transmission and enable
Signal, using first coding module or the second coding module to the transmission under the control of first enable signal
Data are encoded；
When data is received, the decoding selecting module is made to receive the second enabled letter of the second enable signal line transmission
Number, using first decoder module or the second decoder module to the reception number under the control of second enable signal
According to being decoded.
8. the method according to the description of claim 7 is characterized in that the method further includes：
When there are data to be sent, the asynchronous clock selecting module is made to receive the third of the third enable signal line transmission
Enable signal, under the control of the third enable signal using the transmitting terminal asynchronous FIFO module to the primary data into
Across the clock processing of row, and obtained transmission data is sent to coding selecting module.
9. according to the method described in claim 8, it is characterized in that, in the first coding module or the second coding module to described
After transmission data is encoded, the method further includes：
The scrambling module is set to carry out scrambling processing as input using the coded data of the coding selecting module output；
The transmission gearbox is set to carry out bit width conversion processing and frequency using the scrambled data that the scrambling module exports as input
Rate conversion process；
The transmitting terminal polarity control module is set to carry out reversion processing with the variable rate data of the transmission gearbox output.
10. the method according to the description of claim 7 is characterized in that the method further includes：
When data is received, the receiving terminal polarity control module is made to carry out at reversion the primary data for receiving channel reception
Reason；
The synchronous head detection module is set to be wrapped using the reversal data that the receiving terminal polarity control module exports as input
Head detection process；
Make the reception gearbox using the packet header detection data that the synchronous head detection module exports as input to described initial
Data carry out bit width conversion processing and frequency conversion process；
The descrambling module is set to carry out scramble process using the variable rate data of the reception gearbox output as input, and will descrambling
The reception data obtained after processing are sent to the decoding selecting module, so that the decoding selecting module is solved using described first
Code module or the second decoder module are decoded the reception data；
After the first decoder module or the second decoder module are decoded the reception data, make the elastic caching mould
Block carries out frequency departure calibration process using the decoding data for decoding selecting module output as input.
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Application publication date: 20180911 |