BR112015029869A2 - gerenciamento de energia em conjuntos de matrizes múltiplas - Google Patents

gerenciamento de energia em conjuntos de matrizes múltiplas

Info

Publication number
BR112015029869A2
BR112015029869A2 BR112015029869A BR112015029869A BR112015029869A2 BR 112015029869 A2 BR112015029869 A2 BR 112015029869A2 BR 112015029869 A BR112015029869 A BR 112015029869A BR 112015029869 A BR112015029869 A BR 112015029869A BR 112015029869 A2 BR112015029869 A2 BR 112015029869A2
Authority
BR
Brazil
Prior art keywords
matrix
inductive element
voltage
power management
control circuitry
Prior art date
Application number
BR112015029869A
Other languages
English (en)
Other versions
BR112015029869B1 (pt
Inventor
Schaefer Andre
Droege Guido
Zillmann Uwe
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015029869A2 publication Critical patent/BR112015029869A2/pt
Publication of BR112015029869B1 publication Critical patent/BR112015029869B1/pt

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00Adaptations of transformers or inductances for specific applications or functions
    • H01F38/14Inductive couplings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/618Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series and in parallel with the load as final control devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19102Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
  • Semiconductor Memories (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)

Abstract

resumo patente de invenção: "gerenciamento de energia em conjuntos de matrizes múltiplas". a presente invenção refere-se a um aparelho tal como um dispositivo heterogêneo que inclui pelo menos uma primeira matriz e uma segunda matriz. o aparelho inclui adicionalmente um primeiro elemento indutivo, um segundo elemento indutivo e conjunto de circuitos de controle de comutador. o conjunto de circuitos de controle de comutador é disposto na primeira matriz. o conjunto de circuitos de controle de comutador controla a corrente através do primeiro elemento indutivo para produzir uma primeira tensão. a primeira tensão energiza a primeira matriz. o segundo elemento indutivo é acoplado ao primeiro elemento indutivo. o segundo elemento indutivo produz uma segunda tensão para energizar a segunda matriz. a primeira matriz e a segunda matriz podem ser fabricadas em concordância com tecnologias diferentes e nas quais a primeira matriz e a segunda matriz resistem a tensões máximas diferentes. uma magnitude da primeira tensão pode ser maior do que uma magnitude da segunda tensão.
BR112015029869-9A 2013-06-26 2014-06-18 Aparelho e método para gerenciamento de energia em um conjunto de múltiplas matrizes e sistema de computador BR112015029869B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/927,227 2013-06-26
US13/927,227 US9391453B2 (en) 2013-06-26 2013-06-26 Power management in multi-die assemblies
PCT/US2014/042830 WO2014209693A1 (en) 2013-06-26 2014-06-18 Power management in multi-die assemblies

Publications (2)

Publication Number Publication Date
BR112015029869A2 true BR112015029869A2 (pt) 2017-07-25
BR112015029869B1 BR112015029869B1 (pt) 2022-05-31

Family

ID=52115475

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015029869-9A BR112015029869B1 (pt) 2013-06-26 2014-06-18 Aparelho e método para gerenciamento de energia em um conjunto de múltiplas matrizes e sistema de computador

Country Status (8)

Country Link
US (2) US9391453B2 (pt)
EP (1) EP3014742B1 (pt)
JP (2) JP6195985B2 (pt)
KR (1) KR101860624B1 (pt)
CN (1) CN105264743B (pt)
BR (1) BR112015029869B1 (pt)
RU (1) RU2639302C2 (pt)
WO (1) WO2014209693A1 (pt)

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Also Published As

Publication number Publication date
JP6430600B2 (ja) 2018-11-28
KR101860624B1 (ko) 2018-05-23
RU2015150798A (ru) 2017-05-31
CN105264743B (zh) 2018-11-16
US20150003181A1 (en) 2015-01-01
KR20150138349A (ko) 2015-12-09
JP6195985B2 (ja) 2017-09-13
US10079489B2 (en) 2018-09-18
JP2018032855A (ja) 2018-03-01
BR112015029869B1 (pt) 2022-05-31
EP3014742A1 (en) 2016-05-04
EP3014742B1 (en) 2020-08-05
WO2014209693A1 (en) 2014-12-31
US20170011779A1 (en) 2017-01-12
JP2016528719A (ja) 2016-09-15
CN105264743A (zh) 2016-01-20
RU2639302C2 (ru) 2017-12-21
US9391453B2 (en) 2016-07-12
EP3014742A4 (en) 2017-03-22

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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