AU2003220198A1 - Ion implantation of silicon oxid liner to prevent dopant out-diffusion from so urce/drain extensions - Google Patents

Ion implantation of silicon oxid liner to prevent dopant out-diffusion from so urce/drain extensions

Info

Publication number
AU2003220198A1
AU2003220198A1 AU2003220198A AU2003220198A AU2003220198A1 AU 2003220198 A1 AU2003220198 A1 AU 2003220198A1 AU 2003220198 A AU2003220198 A AU 2003220198A AU 2003220198 A AU2003220198 A AU 2003220198A AU 2003220198 A1 AU2003220198 A1 AU 2003220198A1
Authority
AU
Australia
Prior art keywords
urce
liner
diffusion
ion implantation
drain extensions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003220198A
Other languages
English (en)
Inventor
Mark B. Fuselier
Andy C. Wei
Ping-Chin Yeh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2003220198A1 publication Critical patent/AU2003220198A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H10P30/212—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane
AU2003220198A 2002-03-26 2003-03-13 Ion implantation of silicon oxid liner to prevent dopant out-diffusion from so urce/drain extensions Abandoned AU2003220198A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/105,522 2002-03-26
US10/105,522 US6583016B1 (en) 2002-03-26 2002-03-26 Doped spacer liner for improved transistor performance
PCT/US2003/007559 WO2003083929A1 (en) 2002-03-26 2003-03-13 Ion implantation of silicon oxid liner to prevent dopant out-diffusion from so urce/drain extensions

Publications (1)

Publication Number Publication Date
AU2003220198A1 true AU2003220198A1 (en) 2003-10-13

Family

ID=22306307

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003220198A Abandoned AU2003220198A1 (en) 2002-03-26 2003-03-13 Ion implantation of silicon oxid liner to prevent dopant out-diffusion from so urce/drain extensions

Country Status (8)

Country Link
US (1) US6583016B1 (https=)
EP (1) EP1488453A1 (https=)
JP (1) JP4514023B2 (https=)
KR (1) KR100948939B1 (https=)
CN (1) CN100355046C (https=)
AU (1) AU2003220198A1 (https=)
TW (1) TWI270933B (https=)
WO (1) WO2003083929A1 (https=)

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US6777298B2 (en) * 2002-06-14 2004-08-17 International Business Machines Corporation Elevated source drain disposable spacer CMOS
JP4112330B2 (ja) * 2002-10-02 2008-07-02 富士通株式会社 半導体装置の製造方法
JP2004363443A (ja) * 2003-06-06 2004-12-24 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6812105B1 (en) 2003-07-16 2004-11-02 International Business Machines Corporation Ultra-thin channel device with raised source and drain and solid source extension doping
CN1296987C (zh) * 2003-09-23 2007-01-24 茂德科技股份有限公司 接触孔的制造方法以及半导体元件的制造方法
WO2005067035A1 (en) * 2003-12-04 2005-07-21 International Business Machines Corporation Method for forming non-amorphous, ultra-thin semiconductor devices using sacrificial implantation layer
US20070029608A1 (en) * 2005-08-08 2007-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Offset spacers for CMOS transistors
KR100649311B1 (ko) * 2005-12-15 2006-11-24 동부일렉트로닉스 주식회사 게이트 스페이서를 이용한 피모스 소자의 변형된 채널층형성 방법 및 이 방법에 의해 형성된 피모스 소자
JP6087672B2 (ja) * 2012-03-16 2017-03-01 株式会社半導体エネルギー研究所 半導体装置
US9093554B2 (en) * 2012-05-14 2015-07-28 Globalfoundries Inc. Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers
US10141417B2 (en) 2015-10-20 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure, semiconductor device and the method of forming semiconductor device
US10770354B2 (en) * 2017-11-15 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming integrated circuit with low-k sidewall spacers for gate stacks
CN110265481B (zh) * 2018-08-10 2023-01-17 友达光电股份有限公司 晶体管装置

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US165659A (en) * 1875-07-20 Improvement in registering board-rules
US619098A (en) * 1899-02-07 Steam-boiler
JPH0834313B2 (ja) * 1989-10-09 1996-03-29 株式会社東芝 半導体装置及びその製造方法
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
JPH05267327A (ja) * 1992-03-18 1993-10-15 Fujitsu Ltd Ｍｉｓｆｅｔ及びその製造方法
JPH0823031A (ja) * 1994-07-05 1996-01-23 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JPH0897173A (ja) * 1994-09-22 1996-04-12 Sony Corp 半導体装置の製造方法
JPH08288504A (ja) * 1995-04-14 1996-11-01 Sony Corp 半導体装置の製造方法
CN1057867C (zh) * 1995-12-20 2000-10-25 台湾茂矽电子股份有限公司 注入磷形成补偿的器件沟道区的半导体器件的制造方法
US5756383A (en) * 1996-12-23 1998-05-26 Advanced Micro Devices Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer
US6117719A (en) * 1997-12-18 2000-09-12 Advanced Micro Devices, Inc. Oxide spacers as solid sources for gallium dopant introduction
JPH11238882A (ja) * 1998-02-23 1999-08-31 Sony Corp 半導体装置の製造方法
JP3425079B2 (ja) * 1998-04-24 2003-07-07 三菱電機株式会社 半導体装置の製造方法
US6162692A (en) * 1998-06-26 2000-12-19 Advanced Micro Devices, Inc. Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6190982B1 (en) * 2000-01-28 2001-02-20 United Microelectronics Corp. Method of fabricating a MOS transistor on a semiconductor wafer
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JP2001291861A (ja) * 2000-04-05 2001-10-19 Nec Corp Ｍｏｓトランジスタ、トランジスタ製造方法
JP2002076336A (ja) * 2000-09-01 2002-03-15 Mitsubishi Electric Corp 半導体装置およびｓｏｉ基板
WO2003054951A1 (en) * 2001-12-19 2003-07-03 Advanced Micro Devices, Inc. Semiconductor device comprising a thin oxide liner and method of manufacturing the same
JP3966243B2 (ja) * 2003-07-09 2007-08-29 トヨタ自動車株式会社 内燃機関

Also Published As

Publication number Publication date
KR20040093183A (ko) 2004-11-04
KR100948939B1 (ko) 2010-03-23
CN1643672A (zh) 2005-07-20
WO2003083929A1 (en) 2003-10-09
EP1488453A1 (en) 2004-12-22
TWI270933B (en) 2007-01-11
JP4514023B2 (ja) 2010-07-28
JP2005522033A (ja) 2005-07-21
TW200305940A (en) 2003-11-01
CN100355046C (zh) 2007-12-12
US6583016B1 (en) 2003-06-24

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Legal Events

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MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase