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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
  • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P10/00—Bonding of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
  • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
  • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
  • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
  • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
  • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
  • H10P30/212—Through-implantation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane

Definitions

• the present invention relates to a semiconductor device having improved transistor performance and enabling methodology.
• the present invention has particular applicability in fabricating high density semiconductor devices with high speed integrated circuits having submicron design features and shallow junction depths.
• a gate electrode 11 is typically formed over a semiconductor substrate 10 with a gate dielectric layer 12, e.g., gate oxide layer, therebetween.
• Ion implantation is then conducted to implant shallow source/drain extensions 13.
• An oxide liner 14 is then formed on side surfaces of gate electrode 1 1 and the upper surface of substrate 10, as at a thickness of about 50 A to about 200 A to protect the substrate surface during subsequent etching to form sidewall spacers 15, typically formed of silicon nitride.
• Reference character 14 illustrates a moderate or heavy doped source/drain region typically implanted subsequent to forming sidewall spacers 16.
• Difficulties are encountered in implementing conventional semiconductor fabrication techniques, such as those used to form the structure illustrated in Fig. 1.
• dopant impurities implanted into the source/drain extensions 13, such as P-type impurities, e.g., boron (B) and boron difluoride (BF 2 ) impurities diffuse and segregate in the oxide liner 15.
• P-type impurities e.g., boron (B) and boron difluoride (BF 2 ) impurities
• a lower-temperature 400°C CVD liner oxide can be used to prevent such out diffusion and dopant loss.
• dopant loss occurs during high temperature activation appealing, as at a temperature greater than 100°C for 5 to 10 seconds.
• Such diffusion loss from the source/drain extensions are manifestly disadvantageous, as by increasing the resistance of the source/drain extensions.
• a prior attempt to resolve this problem comprises ion implanting the dopant impurity, e.g., B or BF 2 , at a higher implantation dosage than necessary in order to compensate for dopant diffusion loss.
• this approach disadvantageously results in a deeper junction depth (X j ), which is inconsistent with the continuous drive toward miniaturization.
• An advantage of the present invention is a method of fabricating a high density semiconductor device having transistors with improved performance. Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
• a method of manufacturing a semiconductor device comprising: forming a gate electrode, having side surfaces, over an upper surface of a substrate with a gate dielectric layer therebetween; ion-implanting a dopant into the substrate, using the gate electrode as a mask; to form shallow source/drain extensions; forming an oxide liner on the side surfaces of the gate electrode and upper surface of the substrate; and ion-implanting the dopant into the oxide liner.
• Embodiments of the present invention include ion-implanting B or BF 2 into the substrate to form shallow source/drain extensions having a first impurity concentration, depositing a conformal oxide liner on the upper surface and side surfaces of the gate electrode and on the upper surface of the substrate, ion-implanting B or BF 2 into the oxide liner at the substantially same impurity concentration as in the source/drain extensions, e.g., about 1 x 10 20 to about 6 x 10 20 atoms/cm 3 , depositing a spacer layer, such as silicon nitride or silicon oxynitride, and etching to form sidewall spacers. The portion of the silicon oxide liner on the upper surface of the gate electrode may then be removed. Ion-implantation is conducted to form the deep moderate or heavy doped source/drain regions, either before or subsequent to removing the portion of the oxide liner from the upper surface of the gate electrode. Activation annealing may then be conducted.
• Fig. 1 schematically illustrates dopant out-diffusion attendant upon conventional transistor fabrication techniques.
• FIGs. 2 though 4 schematically illustrate sequential steps of a method in accordance with an embodiment of the present invention.
• FIGs. 5 through 8 schematically illustrate sequential phases of another inventive aspect.
• Figs. 2 through 4 and in Figs. 5 through 8, similar features or elements are denoted by similar reference characters.
• the present invention addresses the continuing demand for high density, miniaturized highly reliable semiconductor devices.
• the present invention provides semiconductor devices with enhanced transistor performance, and enabling methodology, by strategically creating a barrier to out-diffusion of impurities from the shallow source/drain extensions into the oxide liner.
• Embodiments of the present invention achieve this objective by ion implanting the impurities into the oxide liner.
• the present invention therefore, provides methodology which avoids or significantly reduces out- diffusion of impurities, such as P-type impurities, e.g., B and BF 2 , while maintaining a shallow junction depth (X j ) of about 200 A to about 300 A.
• Embodiments of the present invention comprise forming a gate electrode over a semiconductor substrate with a gate dielectric layer therebetween and ion implanting a dopant impurity, such as BF 2 , into the substrate, using the gate electrode as a mask, to form shallow source/drain regions.
• a dopant impurity such as BF 2
• Such ion implantation can be conducted in a conventional manner, as by ion- implanting BF 2 at an implantation dosage of about 5 x lO 14 to about 2 x 10 15 ions/cm 2 and an implantation energy of about 1 to about 3 KeV, typically resulting in an impurity concentration of about 1 x 10 20 to about 6 x 10 20 atoms/cm 3 .
• a silicon oxide liner is then deposited, as at a thickness of about 50 A to about 200 A, on the upper surface and side surfaces of the gate electrode and the upper surface of the substrate.
• Ion implantation is then conducted to implant BF 2 impurities into the oxide liner, substantially under the same conditions as employed in forming the shallow source/drain extensions, e.g., at an implantation energy of about 5 x 10 14 to about 2 x 10 15 ions/cm 2 and implantation energy of about 1 to about 3 KeV, thereby forming an impurity concentration in the oxide liner of about 1 x 10 20 to about 6 x 10 20 atoms/cm 3 .
• a spacer layer such as a silicon nitride or a silicon oxynitride, may then be deposited, as at a thickness of about 600 A to about 1200 A.
• Anisotropic etching is then conducted to form the sidewall spacers.
• Ion-implantation of BF 2 is then implemented to form the relatively deep moderate or heavy source/drain implants.
• the portion of the silicon oxide liner on the upper surface of the gate electrode may be removed, either before or after ion-implantation to form the relatively deep moderate or heavily doped source/drain implants, as with hydrofluoric acid. Activation annealing may then be conducted.
• the strategic implantation of dopant impurities into the silicon oxide liner to create a diffusion barrier prevents or significantly reduces out-diffusion of the impurities from the shallow source/drain regions during subsequent processing, as during deposition of the spacer layer and activation annealing.
• a gate electrode 21, typically doped polycrystalline, is formed over substrate 20, typically doped monocrystalline silicon, an epitaxial layer formed on a semiconductor substrate or a well region.
• impurities are ion implanted into substrate 20, such as BF 2 , for forming shallow source/drain extensions 23.
• a silicon oxide liner 30 is deposited, as at a thickness of about 50 A to about 200 A, on the upper and side surfaces of gate electrode 21 and on the upper surface of substrate 20.
• Ion implantation is then conducted, as illustrated by arrows 31 in Fig. 3, to implant BF 2 into oxide liner 31, substantially at the same concentration as implanted into shallow source/drain extensions 23, thereby creating a barrier to out-diffusion of BF 2 atoms from shallow source/drain extensions 23.
• a layer of spacer material is deposited and anisotropic etching is conducted to form sidewall spacers 40, typically at a thickness at the substrate surface of about 600 A to about 1,200 A, as illustrated in Fig. 4.
• Silicon oxide layer 30 serves as an etch stop layer during etching to form sidewall spacers 40, thereby avoiding damage to substrate 20.
• Subsequent processing includes removal of silicon oxide liner 30, as with hydrofluoric acid, from the upper surface of gate electrode 21 and substrate 20. Ion implantation is conducted to form deep moderate or heavy doped source/drain regions 41 , prior or subsequent to removing the portions of silicon of silicon oxide layer 40 from the upper surface of gate electrode 21 and substrate, resulting in the structure schematically illustrated in Fig. 4.
• a dual BOX structure comprises a substrate formed of silicon 50, BOX 51 , silicon layer 52, BOX 53 and silicon layer 54.
• a gate electrode 55 is formed over the dual BOX substrate with a gate dielectric layer 56 therebetween, and sidewall spacers 57 are formed on side surfaces of gate electrode 55.
• a photoresist mask 60 is then formed over the source-side of the structure as illustrated in
• Fig. 6 Etching is then conducted to remove the top silicon layer 54 and upper BOX layer 53 from the drain-side, as shown in Fig. 7. Subsequently, as illustrated in Fig. 8, silicon is expitaxially grown 54A from the lower silicon layer 52. In this way, a deeper drain region 54A can be formed independently of the source region 54B.
• the present invention enables the fabrication of semiconductor devices exhibiting improved transistor performance and shallow junction depths (X j ), e.g., of about 200 A to about 300 A. Impurities of the same type and at substantially the same concentration as in the shallow source/drain extensions are implanted into the oxide liner, thereby preventing or substantially reducing out-diffusion of the impurities from the shallow source/drain extensions with an attendant improvement in source/drain extension resistance and significant improvement in transistor performance, consistent with the continuous drive for miniaturization.
• the present invention enjoys industrial utility in fabricating any of various types of semiconductor devices.
• the present invention enjoys particular industrial in fabricating high density semiconductor devices with a design rule of about 0.12 micron.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Thin Film Transistor (AREA)

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• 2002
  • 2002-03-26 US US10/105,522 patent/US6583016B1/en not_active Expired - Lifetime
• 2003
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