ATE549741T1 - Innerlich verstärkte anschlussflächen - Google Patents

Innerlich verstärkte anschlussflächen

Info

Publication number
ATE549741T1
ATE549741T1 AT04723639T AT04723639T ATE549741T1 AT E549741 T1 ATE549741 T1 AT E549741T1 AT 04723639 T AT04723639 T AT 04723639T AT 04723639 T AT04723639 T AT 04723639T AT E549741 T1 ATE549741 T1 AT E549741T1
Authority
AT
Austria
Prior art keywords
nonplanar
structures
metallic
connection surface
bond pad
Prior art date
Application number
AT04723639T
Other languages
English (en)
Inventor
David Angell
Frederic Beaulieu
Takashi Hisada
Adreanne Kelly
Samuel Mcknight
Hiromitsu Miyai
Kevin Petrarca
Wolfgang Sauter
Richard Volant
Caitlin Weinstein
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE549741T1 publication Critical patent/ATE549741T1/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
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    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/14—Integrated circuits
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    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Inorganic Insulating Materials (AREA)
  • Laminated Bodies (AREA)
  • Wire Bonding (AREA)
AT04723639T 2003-04-03 2004-03-26 Innerlich verstärkte anschlussflächen ATE549741T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/249,381 US6864578B2 (en) 2003-04-03 2003-04-03 Internally reinforced bond pads
PCT/GB2004/001313 WO2004088736A1 (en) 2003-04-03 2004-03-26 Internally reinforced bond pads

Publications (1)

Publication Number Publication Date
ATE549741T1 true ATE549741T1 (de) 2012-03-15

Family

ID=33096530

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04723639T ATE549741T1 (de) 2003-04-03 2004-03-26 Innerlich verstärkte anschlussflächen

Country Status (7)

Country Link
US (2) US6864578B2 (de)
EP (1) EP1609179B1 (de)
KR (1) KR100800357B1 (de)
CN (1) CN100373569C (de)
AT (1) ATE549741T1 (de)
TW (1) TWI267966B (de)
WO (1) WO2004088736A1 (de)

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US20070287279A1 (en) * 2006-06-08 2007-12-13 Daubenspeck Timothy H Methods of forming solder connections and structure thereof
WO2008015500A1 (en) * 2006-08-01 2008-02-07 Freescale Semiconductor, Inc. Method and apparatus for improvements in chip manufacture and design
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DE102006052202B3 (de) * 2006-11-06 2008-02-21 Infineon Technologies Ag Halbleiterbauelement sowie Verfahren zur Herstellung eines Halbleiterbauelements
US20090079082A1 (en) * 2007-09-24 2009-03-26 Yong Liu Bonding pad structure allowing wire bonding over an active area in a semiconductor die and method of manufacturing same
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
EP2568498A3 (de) * 2007-10-31 2013-04-24 Agere Systems Inc. Bondkontaktstellen-Haltestruktur für eine Halbleiteranordnung
JP5291917B2 (ja) 2007-11-09 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100933685B1 (ko) * 2007-12-18 2009-12-23 주식회사 하이닉스반도체 필링 방지를 위한 본딩패드 및 그 형성 방법
KR101051551B1 (ko) * 2009-10-30 2011-07-22 삼성전기주식회사 요철 패턴을 갖는 비아 패드를 포함하는 인쇄회로기판 및 그 제조방법
JP5582879B2 (ja) * 2010-06-09 2014-09-03 株式会社東芝 半導体装置及びその製造方法
JP2012124452A (ja) * 2010-12-06 2012-06-28 Samsung Electro-Mechanics Co Ltd プリント基板およびその製造方法
US8466560B2 (en) * 2010-12-30 2013-06-18 Stmicroelectronics, Inc. Dummy structures having a golden ratio and method for forming the same
US8314026B2 (en) 2011-02-17 2012-11-20 Freescale Semiconductor, Inc. Anchored conductive via and method for forming
US10217644B2 (en) 2012-07-24 2019-02-26 Infineon Technologies Ag Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures
US9832887B2 (en) * 2013-08-07 2017-11-28 Invensas Corporation Micro mechanical anchor for 3D architecture
CN106542492A (zh) * 2015-09-23 2017-03-29 中芯国际集成电路制造(北京)有限公司 焊盘结构、焊环结构和mems器件的封装方法
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN107887285A (zh) * 2016-09-30 2018-04-06 中芯国际集成电路制造(北京)有限公司 焊垫结构及其制造方法、及图像传感器
DE102017116574A1 (de) * 2017-07-21 2019-01-24 Infineon Technologies Ag Halbleiterbauelement
CN110223922B (zh) * 2019-06-10 2020-12-11 武汉新芯集成电路制造有限公司 一种晶圆结构及其制造方法、芯片结构

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US6864578B2 (en) 2005-03-08
US7273804B2 (en) 2007-09-25
KR100800357B1 (ko) 2008-02-04
CN100373569C (zh) 2008-03-05
EP1609179B1 (de) 2012-03-14
TW200503223A (en) 2005-01-16
EP1609179A1 (de) 2005-12-28
US20040195642A1 (en) 2004-10-07
WO2004088736A1 (en) 2004-10-14
US20050121803A1 (en) 2005-06-09
TWI267966B (en) 2006-12-01
CN1701428A (zh) 2005-11-23

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