ATE504080T1 - Herstellungsmethode eines keramik- mehrlagensubstrates - Google Patents

Herstellungsmethode eines keramik- mehrlagensubstrates

Info

Publication number
ATE504080T1
ATE504080T1 AT99951184T AT99951184T ATE504080T1 AT E504080 T1 ATE504080 T1 AT E504080T1 AT 99951184 T AT99951184 T AT 99951184T AT 99951184 T AT99951184 T AT 99951184T AT E504080 T1 ATE504080 T1 AT E504080T1
Authority
AT
Austria
Prior art keywords
cavity
green sheets
production method
layer substrate
ceramic substrate
Prior art date
Application number
AT99951184T
Other languages
English (en)
Inventor
Jun Shigemi
Shigetoshi Segawa
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Application granted granted Critical
Publication of ATE504080T1 publication Critical patent/ATE504080T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807—Ceramic parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056—Perforating lamina
    • Y10T156/1057—Subsequent to assembly of laminae
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
AT99951184T 1998-11-02 1999-11-01 Herstellungsmethode eines keramik- mehrlagensubstrates ATE504080T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31252898A JP3547327B2 (ja) 1998-11-02 1998-11-02 セラミック多層基板の製造方法
PCT/JP1999/006072 WO2000026957A1 (en) 1998-11-02 1999-11-01 Method of manufacturing a multi-layered ceramic substrate

Publications (1)

Publication Number Publication Date
ATE504080T1 true ATE504080T1 (de) 2011-04-15

Family

ID=18030321

Family Applications (1)

Application Number Title Priority Date Filing Date
AT99951184T ATE504080T1 (de) 1998-11-02 1999-11-01 Herstellungsmethode eines keramik- mehrlagensubstrates

Country Status (9)

Country Link
US (1) US6350334B1 (de)
EP (1) EP1042803B1 (de)
JP (1) JP3547327B2 (de)
KR (1) KR100521941B1 (de)
CN (1) CN1146974C (de)
AT (1) ATE504080T1 (de)
DE (1) DE69943313D1 (de)
TW (1) TWI232076B (de)
WO (1) WO2000026957A1 (de)

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* Cited by examiner, † Cited by third party
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JP3656484B2 (ja) * 1999-03-03 2005-06-08 株式会社村田製作所 セラミック多層基板の製造方法
ATE236788T1 (de) * 1999-07-27 2003-04-15 Univ North Carolina State Strukturierte trennfolie zwischen zwei laminierten oberflächen
JP3511982B2 (ja) * 2000-06-14 2004-03-29 株式会社村田製作所 多層配線基板の製造方法
US7506438B1 (en) * 2000-11-14 2009-03-24 Freescale Semiconductor, Inc. Low profile integrated module interconnects and method of fabrication
US6917461B2 (en) * 2000-12-29 2005-07-12 Texas Instruments Incorporated Laminated package
JP2003031948A (ja) * 2001-07-12 2003-01-31 Matsushita Electric Ind Co Ltd セラミック多層基板の製造方法
US6835260B2 (en) * 2002-10-04 2004-12-28 International Business Machines Corporation Method to produce pedestal features in constrained sintered substrates
US7332805B2 (en) * 2004-01-06 2008-02-19 International Business Machines Corporation Electronic package with improved current carrying capability and method of forming the same
TW200644757A (en) * 2005-04-19 2006-12-16 Tdk Corp Multilayer ceramic substrate and production method thereof
JP4867276B2 (ja) * 2005-10-14 2012-02-01 株式会社村田製作所 セラミック基板の製造方法
KR100659510B1 (ko) * 2006-02-16 2006-12-20 삼성전기주식회사 캐비티가 형성된 기판 제조 방법
US7638988B2 (en) * 2006-02-21 2009-12-29 Virginia Tech Intellectual Properties, Inc. Co-fired ceramic inductors with variable inductance, and voltage regulator having same
KR100898977B1 (ko) * 2007-11-07 2009-05-25 삼성전기주식회사 인쇄회로기판 제조방법
KR101004942B1 (ko) * 2008-08-29 2010-12-28 삼성전기주식회사 다층 세라믹 기판 제조방법
KR101046006B1 (ko) * 2008-10-23 2011-07-01 삼성전기주식회사 무수축 다층 세라믹 기판의 제조방법
FR2944646B1 (fr) 2009-04-21 2012-03-23 Commissariat Energie Atomique Procede de realisation d'une cavite dans l'epaisseur d'un substrat pouvant former un site d'accueil de composant
AT13229U1 (de) * 2011-12-05 2013-08-15 Austria Tech & System Tech Verfahren zum herstellen einer leiterplatte unter entfernung eines teilbereichs derselben sowie verwendung eines derartigen verfahrens
CN102838354B (zh) * 2012-09-11 2013-10-02 中国兵器工业集团第二一四研究所苏州研发中心 一种具有内置空腔的多层陶瓷元件的工艺加工方法
CN103077912B (zh) * 2013-01-15 2015-04-15 宜兴市环洲微电子有限公司 一种多芯片烧结用石墨模具
US20180277395A1 (en) * 2015-10-09 2018-09-27 Hitachi Metals ,Ltd. Method for manufacturing multilayer ceramic substrate
CN108012404A (zh) * 2017-11-29 2018-05-08 生益电子股份有限公司 一种设有台阶槽的pcb
DE102020205043B4 (de) * 2020-04-21 2024-07-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein Verfahren zur Herstellung einer Leistungshalbleiterbauelementanordnung oder Leistungshalbleiterbauelementeinhausung

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Publication number Priority date Publication date Assignee Title
US5250130A (en) * 1988-01-27 1993-10-05 W. R. Grace & Co.-Conn. Replica hot pressing technique
US5176771A (en) * 1991-12-23 1993-01-05 Hughes Aircraft Company Multilayer ceramic tape substrate having cavities formed in the upper layer thereof and method of fabricating the same by printing and delamination
DE4392791T1 (de) * 1992-06-12 1995-06-01 Aluminum Co Of America Verfahren zur Herstellung mehrlagiger Strukturen mit nichtebenen Oberflächen
JP3225666B2 (ja) * 1993-01-27 2001-11-05 株式会社村田製作所 キャビティ付きセラミック多層ブロックの製造方法
US5478420A (en) * 1994-07-28 1995-12-26 International Business Machines Corporation Process for forming open-centered multilayer ceramic substrates
US5538582A (en) * 1994-09-14 1996-07-23 International Business Machines Corporation Method for forming cavities without using an insert
US5601673A (en) * 1995-01-03 1997-02-11 Ferro Corporation Method of making ceramic article with cavity using LTCC tape
US5645673A (en) * 1995-06-02 1997-07-08 International Business Machines Corporation Lamination process for producing non-planar substrates
JPH09266264A (ja) * 1996-03-28 1997-10-07 Sumitomo Kinzoku Electro Device:Kk グリーンシート積層体の切断方法
US5785800A (en) * 1996-06-21 1998-07-28 International Business Machines Corporation Apparatus for forming cavity structures using thermally decomposable surface layer
US5800761A (en) * 1996-10-08 1998-09-01 International Business Machines Corporation Method of making an interface layer for stacked lamination sizing and sintering
US5858145A (en) * 1996-10-15 1999-01-12 Sarnoff Corporation Method to control cavity dimensions of fired multilayer circuit boards on a support
US5788808A (en) * 1997-04-15 1998-08-04 International Business Machines Corporation Apparatus for forming cavity substrates using compressive pads
US5885803A (en) * 1997-06-19 1999-03-23 Incyte Pharmaceuticals, Inc. Disease associated protein kinases

Also Published As

Publication number Publication date
DE69943313D1 (de) 2011-05-12
TWI232076B (en) 2005-05-01
JP3547327B2 (ja) 2004-07-28
EP1042803B1 (de) 2011-03-30
KR20010033828A (ko) 2001-04-25
JP2000138455A (ja) 2000-05-16
KR100521941B1 (ko) 2005-10-13
CN1287686A (zh) 2001-03-14
WO2000026957A1 (en) 2000-05-11
EP1042803A1 (de) 2000-10-11
US6350334B1 (en) 2002-02-26
CN1146974C (zh) 2004-04-21

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