ATE476741T1 - Testvorrichtung und testverfahren - Google Patents

Testvorrichtung und testverfahren

Info

Publication number
ATE476741T1
ATE476741T1 AT07739322T AT07739322T ATE476741T1 AT E476741 T1 ATE476741 T1 AT E476741T1 AT 07739322 T AT07739322 T AT 07739322T AT 07739322 T AT07739322 T AT 07739322T AT E476741 T1 ATE476741 T1 AT E476741T1
Authority
AT
Austria
Prior art keywords
page
dut
grade
failure information
pass
Prior art date
Application number
AT07739322T
Other languages
English (en)
Inventor
Taiki Ozawa
Shinya Sato
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Application granted granted Critical
Publication of ATE476741T1 publication Critical patent/ATE476741T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31932—Comparators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56008—Error analysis, representation of errors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
AT07739322T 2006-04-06 2007-03-22 Testvorrichtung und testverfahren ATE476741T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006105394 2006-04-06
PCT/JP2007/055879 WO2007119485A1 (ja) 2006-04-06 2007-03-22 試験装置および試験方法

Publications (1)

Publication Number Publication Date
ATE476741T1 true ATE476741T1 (de) 2010-08-15

Family

ID=38609270

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07739322T ATE476741T1 (de) 2006-04-06 2007-03-22 Testvorrichtung und testverfahren

Country Status (9)

Country Link
US (1) US7984345B2 (de)
EP (1) EP2003653B1 (de)
JP (1) JP4864006B2 (de)
KR (2) KR20080007544A (de)
CN (1) CN101310342A (de)
AT (1) ATE476741T1 (de)
DE (1) DE602007008216D1 (de)
TW (1) TW200739593A (de)
WO (1) WO2007119485A1 (de)

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JP5038256B2 (ja) * 2008-08-14 2012-10-03 株式会社アドバンテスト 試験モジュールおよび試験方法
US8149730B1 (en) 2009-05-12 2012-04-03 Juniper Networks, Inc. Methods and apparatus related to packet generation and analysis
US8174991B1 (en) * 2009-06-29 2012-05-08 Juniper Networks, Inc. Methods and apparatus related to analysis of test packets
JP2011170950A (ja) * 2010-01-21 2011-09-01 Renesas Electronics Corp 情報記憶装置及びそのテスト方法
US8258803B2 (en) * 2010-01-26 2012-09-04 Advantest Corporation Test apparatus and test method
US8201024B2 (en) * 2010-05-17 2012-06-12 Microsoft Corporation Managing memory faults
JP2012069180A (ja) * 2010-09-21 2012-04-05 Toshiba Corp 半導体記憶装置
US8798077B2 (en) 2010-12-29 2014-08-05 Juniper Networks, Inc. Methods and apparatus for standard protocol validation mechanisms deployed over a switch fabric system
US8780896B2 (en) 2010-12-29 2014-07-15 Juniper Networks, Inc. Methods and apparatus for validation of equal cost multi path (ECMP) paths in a switch fabric system
TWI459393B (zh) * 2011-01-19 2014-11-01 Phison Electronics Corp 用於非揮發性記憶體的資料寫入方法、控制器與儲存裝置
KR101824068B1 (ko) * 2011-07-28 2018-03-15 삼성전자주식회사 메모리 컨트롤러 구동방법, 및 메모리 컨트롤러를 포함하는 메모리 시스템, 메모리 카드 및 휴대용 전자장치
US8995196B2 (en) 2011-08-15 2015-03-31 Skymedi Corporation Method of sorting a multi-bit per cell non-volatile memory and a multi-mode configuration method
KR101944793B1 (ko) * 2012-09-04 2019-02-08 삼성전자주식회사 플래시 메모리를 포함하는 플래시 메모리 시스템 및 그것의 비정상 워드 라인 검출 방법
CN102788951B (zh) * 2012-09-05 2015-02-11 无锡江南计算技术研究所 Ate测试结果判断方法及ate测试方法
US9032244B2 (en) 2012-11-16 2015-05-12 Microsoft Technology Licensing, Llc Memory segment remapping to address fragmentation
US9911509B2 (en) * 2013-12-06 2018-03-06 Intel Corporation Counter to locate faulty die in a distributed codeword storage system
US9600385B2 (en) * 2014-02-25 2017-03-21 Arrow Devices Pvt Ltd Analyzing behavior of a device under test
CN104979017B (zh) * 2014-04-03 2020-10-27 皇虎科技(加拿大)有限公司 用于测试及组装存储器模块的系统及方法
US20150363330A1 (en) * 2014-06-17 2015-12-17 Daniel Robert Watkins Flash NAND device bad page replacement
KR101527690B1 (ko) * 2014-10-10 2015-06-11 (주) 에이블리 낸드 플래시 메모리 테스트 인터페이스 장치 및 그 운용방법
KR102238706B1 (ko) * 2014-11-28 2021-04-09 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
KR20160121230A (ko) * 2015-04-10 2016-10-19 에스케이하이닉스 주식회사 반도체 메모리 장치, 이를 위한 리페어 시스템 및 장치 특성 관리 방법
US11025478B2 (en) * 2015-05-27 2021-06-01 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for analysing performance of a network by managing network data relating to operation of the network
KR20160146332A (ko) * 2015-06-12 2016-12-21 에스케이하이닉스 주식회사 복수의 저장 영역들을 포함하는 메모리 시스템 및 그것의 동작 방법
CN105139893B (zh) * 2015-09-27 2018-10-16 上海华力微电子有限公司 一种存储器测试装置及一种存储器芯片测试方法
TWI581093B (zh) 2016-06-24 2017-05-01 慧榮科技股份有限公司 資料儲存媒體之損壞資料行的篩選方法
KR102545698B1 (ko) * 2016-09-27 2023-06-19 삼성전자주식회사 데이터 저장 시스템
KR102458563B1 (ko) * 2018-02-12 2022-10-28 한국전자통신연구원 백스캐터 통신을 사용한 통신 방법 및 통신 장치
KR102507774B1 (ko) * 2018-03-08 2023-03-09 에스케이하이닉스 주식회사 메모리 칩 및 그것을 포함하는 테스트 시스템
JP7058759B2 (ja) 2019-01-22 2022-04-22 株式会社アドバンテスト １または複数の被テストデバイスをテストするための自動試験装置、１または複数の被テストデバイスの自動試験のための方法、および、コマンドエラーを処理するためのコンピュータプログラム
US11342044B2 (en) * 2019-05-28 2022-05-24 Nuvoton Technology Corporation System and method for prioritization of bit error correction attempts
KR20210004135A (ko) * 2019-07-03 2021-01-13 에스케이하이닉스 주식회사 패일 정보 제어회로, 이를 포함하는 반도체 장치 및 반도체 장치의 패일 정보 제어방법
TWI764297B (zh) * 2019-11-20 2022-05-11 大陸商珠海南北極科技有限公司 累加電路

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JP2000173289A (ja) * 1998-12-10 2000-06-23 Toshiba Corp エラー訂正可能なフラッシュメモリシステム
JP4323707B2 (ja) * 2000-10-25 2009-09-02 富士通マイクロエレクトロニクス株式会社 フラッシュメモリの欠陥管理方法
JP4250325B2 (ja) * 2000-11-01 2009-04-08 株式会社東芝 半導体記憶装置
JP4296092B2 (ja) * 2001-12-18 2009-07-15 株式会社アドバンテスト 半導体試験装置
JP4158526B2 (ja) * 2003-01-09 2008-10-01 松下電器産業株式会社 メモリカード及びメモリへのデータ書き込み方法
JP2005056394A (ja) * 2003-07-18 2005-03-03 Toshiba Corp 記憶装置及びメモリカード
US7493534B2 (en) * 2003-08-29 2009-02-17 Hewlett-Packard Development Company, L.P. Memory error ranking
JP4041076B2 (ja) * 2004-02-27 2008-01-30 株式会社東芝 データ記憶システム
JP2006012367A (ja) * 2004-06-29 2006-01-12 Toshiba Corp 不揮発性半導体記憶装置
JP4261462B2 (ja) * 2004-11-05 2009-04-30 株式会社東芝 不揮発性メモリシステム
US7447955B2 (en) * 2005-11-30 2008-11-04 Advantest Corporation Test apparatus and test method

Also Published As

Publication number Publication date
KR20090053960A (ko) 2009-05-28
JPWO2007119485A1 (ja) 2009-08-27
EP2003653A1 (de) 2008-12-17
EP2003653A4 (de) 2009-10-28
EP2003653B1 (de) 2010-08-04
DE602007008216D1 (de) 2010-09-16
US7984345B2 (en) 2011-07-19
JP4864006B2 (ja) 2012-01-25
CN101310342A (zh) 2008-11-19
US20080052015A1 (en) 2008-02-28
TW200739593A (en) 2007-10-16
KR20080007544A (ko) 2008-01-22
WO2007119485A1 (ja) 2007-10-25

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