ATE445230T1 - Verfahren zum planarisieren der oberfläche eines halbleiterwafers - Google Patents

Verfahren zum planarisieren der oberfläche eines halbleiterwafers

Info

Publication number
ATE445230T1
ATE445230T1 AT98918864T AT98918864T ATE445230T1 AT E445230 T1 ATE445230 T1 AT E445230T1 AT 98918864 T AT98918864 T AT 98918864T AT 98918864 T AT98918864 T AT 98918864T AT E445230 T1 ATE445230 T1 AT E445230T1
Authority
AT
Austria
Prior art keywords
wafer
exposed surface
exposed
abrasive
area
Prior art date
Application number
AT98918864T
Other languages
English (en)
Inventor
David Kaisaki
Heather Kranz
Thomas Wood
L Hardy
Original Assignee
Minnesota Mining & Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minnesota Mining & Mfg filed Critical Minnesota Mining & Mfg
Application granted granted Critical
Publication of ATE445230T1 publication Critical patent/ATE445230T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/22—Lapping pads for working plane surfaces characterised by a multi-layered structure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B24B37/24—Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • B24B37/245—Pads with fixed abrasives
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24D—TOOLS FOR GRINDING, BUFFING OR SHARPENING
    • B24D11/00—Constructional features of flexible abrasive materials; Special features in the manufacture of such materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Polishing Bodies And Polishing Tools (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
AT98918864T 1997-04-30 1998-04-30 Verfahren zum planarisieren der oberfläche eines halbleiterwafers ATE445230T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US84672697A 1997-04-30 1997-04-30
PCT/US1998/008693 WO1998049723A1 (en) 1997-04-30 1998-04-30 Method of planarizing the upper surface of a semiconductor wafer

Publications (1)

Publication Number Publication Date
ATE445230T1 true ATE445230T1 (de) 2009-10-15

Family

ID=25298766

Family Applications (1)

Application Number Title Priority Date Filing Date
AT98918864T ATE445230T1 (de) 1997-04-30 1998-04-30 Verfahren zum planarisieren der oberfläche eines halbleiterwafers

Country Status (12)

Country Link
EP (1) EP1016133B1 (de)
JP (1) JP2001523395A (de)
KR (1) KR100571892B1 (de)
CN (1) CN1165975C (de)
AT (1) ATE445230T1 (de)
AU (1) AU734883B2 (de)
BR (1) BR9809311A (de)
CA (1) CA2287404C (de)
DE (1) DE69841220D1 (de)
MY (1) MY125856A (de)
TW (1) TW479285B (de)
WO (1) WO1998049723A1 (de)

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MY125856A (en) 2006-08-30
AU7170698A (en) 1998-11-24
CA2287404C (en) 2007-10-16
KR100571892B1 (ko) 2006-04-18
BR9809311A (pt) 2000-07-04
AU734883B2 (en) 2001-06-21
KR20010020384A (ko) 2001-03-15
CA2287404A1 (en) 1998-11-05
TW479285B (en) 2002-03-11
DE69841220D1 (de) 2009-11-19
WO1998049723A1 (en) 1998-11-05
EP1016133A1 (de) 2000-07-05
EP1016133B1 (de) 2009-10-07
CN1165975C (zh) 2004-09-08
CN1254441A (zh) 2000-05-24
JP2001523395A (ja) 2001-11-20

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