ATE321362T1 - Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren - Google Patents

Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren

Info

Publication number
ATE321362T1
ATE321362T1 AT02761321T AT02761321T ATE321362T1 AT E321362 T1 ATE321362 T1 AT E321362T1 AT 02761321 T AT02761321 T AT 02761321T AT 02761321 T AT02761321 T AT 02761321T AT E321362 T1 ATE321362 T1 AT E321362T1
Authority
AT
Austria
Prior art keywords
compliant
dielectric layer
bumps
electrically conductive
semiconductor device
Prior art date
Application number
AT02761321T
Other languages
English (en)
Inventor
Michael A Lutz
Original Assignee
Dow Corning
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dow Corning filed Critical Dow Corning
Application granted granted Critical
Publication of ATE321362T1 publication Critical patent/ATE321362T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/0554—External layer
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
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    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
AT02761321T 2001-09-12 2002-08-12 Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren ATE321362T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/952,337 US20030047339A1 (en) 2001-09-12 2001-09-12 Semiconductor device with compliant electrical terminals, apparatus including the semiconductor device, and methods for forming same

Publications (1)

Publication Number Publication Date
ATE321362T1 true ATE321362T1 (de) 2006-04-15

Family

ID=25492801

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02761321T ATE321362T1 (de) 2001-09-12 2002-08-12 Halbleiteranordnung mit weichen elektrischen anschlüssen, bauteil damit und seine herstellungsverfahren

Country Status (10)

Country Link
US (1) US20030047339A1 (de)
EP (1) EP1428256B1 (de)
JP (1) JP4771658B2 (de)
KR (1) KR100888712B1 (de)
AT (1) ATE321362T1 (de)
AU (1) AU2002326597A1 (de)
CA (1) CA2459386A1 (de)
DE (1) DE60210109T2 (de)
TW (1) TW569413B (de)
WO (1) WO2003023855A2 (de)

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US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
US20090256256A1 (en) * 2008-04-11 2009-10-15 Infineon Technologies Ag Electronic Device and Method of Manufacturing Same
TWI462676B (zh) * 2009-02-13 2014-11-21 Senju Metal Industry Co The solder bumps for the circuit substrate are formed using the transfer sheet
JP5128712B1 (ja) * 2012-04-13 2013-01-23 ラピスセミコンダクタ株式会社 半導体装置
US9293402B2 (en) 2012-04-13 2016-03-22 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
JP2016184620A (ja) * 2015-03-25 2016-10-20 大日本印刷株式会社 多層配線構造体
JP2016184619A (ja) * 2015-03-25 2016-10-20 大日本印刷株式会社 多層配線構造体
JP2015167254A (ja) * 2015-05-21 2015-09-24 株式会社テラプローブ 半導体装置、その実装構造及びその製造方法
KR101897653B1 (ko) * 2017-03-06 2018-09-12 엘비세미콘 주식회사 컴플라이언트 범프의 제조방법
US10748850B2 (en) * 2018-03-15 2020-08-18 Semiconductor Components Industries, Llc Thinned semiconductor package and related methods
US11749616B2 (en) 2017-10-05 2023-09-05 Texas Instruments Incorporated Industrial chip scale package for microelectronic device
US10923365B2 (en) * 2018-10-28 2021-02-16 Richwave Technology Corp. Connection structure and method for forming the same

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US6114187A (en) * 1997-01-11 2000-09-05 Microfab Technologies, Inc. Method for preparing a chip scale package and product produced by the method
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
JP2000208664A (ja) * 1999-01-13 2000-07-28 Matsushita Electric Ind Co Ltd 半導体パッケ―ジおよびその製造方法、並びに、半導体チップ実装体およびその製造方法
JP2000228417A (ja) * 1999-02-04 2000-08-15 Sony Corp 半導体装置、電子モジュール及び電子機器、並びに半導体装置の製造方法
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JP4526651B2 (ja) * 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
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Publication number Publication date
JP2005503020A (ja) 2005-01-27
AU2002326597A1 (en) 2003-03-24
KR20040047822A (ko) 2004-06-05
EP1428256A2 (de) 2004-06-16
EP1428256B1 (de) 2006-03-22
US20030047339A1 (en) 2003-03-13
WO2003023855A3 (en) 2003-12-11
DE60210109D1 (de) 2006-05-11
WO2003023855A2 (en) 2003-03-20
JP4771658B2 (ja) 2011-09-14
KR100888712B1 (ko) 2009-03-17
TW569413B (en) 2004-01-01
CA2459386A1 (en) 2003-03-20
DE60210109T2 (de) 2006-11-09

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