ATE278217T1 - Spaltenredundanzschaltung mit reduzierter signalwegverzögerung - Google Patents

Spaltenredundanzschaltung mit reduzierter signalwegverzögerung

Info

Publication number
ATE278217T1
ATE278217T1 AT99953491T AT99953491T ATE278217T1 AT E278217 T1 ATE278217 T1 AT E278217T1 AT 99953491 T AT99953491 T AT 99953491T AT 99953491 T AT99953491 T AT 99953491T AT E278217 T1 ATE278217 T1 AT E278217T1
Authority
AT
Austria
Prior art keywords
column
defective
signal path
memory
path delay
Prior art date
Application number
AT99953491T
Other languages
German (de)
English (en)
Inventor
Fangxing Wei
Hirohito Kikukawa
Cynthia Mar
Original Assignee
Mosaid Technologies Inc
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc, Matsushita Electric Industrial Co Ltd filed Critical Mosaid Technologies Inc
Application granted granted Critical
Publication of ATE278217T1 publication Critical patent/ATE278217T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT99953491T 1998-10-30 1999-10-29 Spaltenredundanzschaltung mit reduzierter signalwegverzögerung ATE278217T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/182,495 US6137735A (en) 1998-10-30 1998-10-30 Column redundancy circuit with reduced signal path delay
PCT/CA1999/001054 WO2000026784A1 (en) 1998-10-30 1999-10-29 Column redundancy circuit with reduced signal path delay

Publications (1)

Publication Number Publication Date
ATE278217T1 true ATE278217T1 (de) 2004-10-15

Family

ID=22668727

Family Applications (1)

Application Number Title Priority Date Filing Date
AT99953491T ATE278217T1 (de) 1998-10-30 1999-10-29 Spaltenredundanzschaltung mit reduzierter signalwegverzögerung

Country Status (10)

Country Link
US (1) US6137735A (https=)
EP (2) EP1526458B8 (https=)
JP (1) JP4965025B2 (https=)
KR (1) KR100724816B1 (https=)
CN (1) CN1186725C (https=)
AT (1) ATE278217T1 (https=)
AU (1) AU1024500A (https=)
CA (1) CA2347765C (https=)
DE (2) DE69939716D1 (https=)
WO (1) WO2000026784A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363085B1 (ko) * 1999-11-05 2002-12-05 삼성전자 주식회사 리던던시 효율을 향상시키는 로우 리던던시 스킴을 갖는반도체장치
JP2002050191A (ja) * 2000-08-02 2002-02-15 Fujitsu Ltd 半導体記憶装置
US6775759B2 (en) * 2001-12-07 2004-08-10 Micron Technology, Inc. Sequential nibble burst ordering for data
US20040015645A1 (en) * 2002-07-19 2004-01-22 Dodd James M. System, apparatus, and method for a flexible DRAM architecture
US6674673B1 (en) 2002-08-26 2004-01-06 International Business Machines Corporation Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture
WO2005081257A1 (ja) * 2004-02-20 2005-09-01 Spansion Llc 半導体記憶装置および半導体記憶装置の制御方法
US7035152B1 (en) * 2004-10-14 2006-04-25 Micron Technology, Inc. System and method for redundancy memory decoding
US7251173B2 (en) * 2005-08-02 2007-07-31 Micron Technology, Inc. Combination column redundancy system for a memory array
CN105355233B (zh) * 2015-11-23 2018-04-10 清华大学 基于pcm反转纠错算法的高效数据写入方法
CN107389211B (zh) * 2017-06-29 2019-03-12 西安邮电大学 一种二进制码转温度计码电路

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4598388A (en) * 1985-01-22 1986-07-01 Texas Instruments Incorporated Semiconductor memory with redundant column circuitry
JP2564507B2 (ja) * 1985-04-16 1996-12-18 富士通株式会社 半導体記憶装置
JPH01125799A (ja) * 1987-11-11 1989-05-18 Fujitsu Ltd 半導体記憶装置
US5270975A (en) * 1990-03-29 1993-12-14 Texas Instruments Incorporated Memory device having a non-uniform redundancy decoder arrangement
DE69132951T2 (de) * 1991-08-28 2002-09-12 Oki Electric Industry Co., Ltd. Halbleiter-speicher-vorrichtung
US5257229A (en) * 1992-01-31 1993-10-26 Sgs-Thomson Microelectronics, Inc. Column redundancy architecture for a read/write memory
US5268866A (en) * 1992-03-02 1993-12-07 Motorola, Inc. Memory with column redundancy and localized column redundancy control signals
EP0697659B1 (de) * 1994-08-12 1999-12-15 Siemens Aktiengesellschaft Redundanz-Schaltungsanordnung für einen integrierten Halbleiterspeicher
KR0130030B1 (ko) * 1994-08-25 1998-10-01 김광호 반도체 메모리 장치의 컬럼 리던던시 회로 및 그 방법
US5572470A (en) * 1995-05-10 1996-11-05 Sgs-Thomson Microelectronics, Inc. Apparatus and method for mapping a redundant memory column to a defective memory column
JPH0955080A (ja) * 1995-08-08 1997-02-25 Fujitsu Ltd 半導体記憶装置及び半導体記憶装置のセル情報の書き込み及び読み出し方法
ATE220228T1 (de) * 1995-08-09 2002-07-15 Infineon Technologies Ag Integrierte halbleiter-speichervorrichtung mit redundanzschaltungsanordnung
US5646896A (en) * 1995-10-31 1997-07-08 Hyundai Electronics America Memory device with reduced number of fuses
US5732030A (en) * 1996-06-25 1998-03-24 Texas Instruments Incorporated Method and system for reduced column redundancy using a dual column select
JPH10275493A (ja) * 1997-03-31 1998-10-13 Nec Corp 半導体記憶装置
CA2202692C (en) * 1997-04-14 2006-06-13 Mosaid Technologies Incorporated Column redundancy in semiconductor memories
KR100281284B1 (ko) * 1998-06-29 2001-02-01 김영환 컬럼 리던던시 회로

Also Published As

Publication number Publication date
US6137735A (en) 2000-10-24
CA2347765C (en) 2008-07-29
AU1024500A (en) 2000-05-22
EP1526458B8 (en) 2008-12-24
KR20010085983A (ko) 2001-09-07
DE69920735T2 (de) 2005-02-10
EP1125203B1 (en) 2004-09-29
CN1331818A (zh) 2002-01-16
EP1125203A1 (en) 2001-08-22
EP1526458A3 (en) 2006-03-29
KR100724816B1 (ko) 2007-06-04
JP4965025B2 (ja) 2012-07-04
DE69920735D1 (de) 2004-11-04
WO2000026784A1 (en) 2000-05-11
JP2002529874A (ja) 2002-09-10
EP1526458B1 (en) 2008-10-08
CN1186725C (zh) 2005-01-26
CA2347765A1 (en) 2000-05-11
EP1526458A2 (en) 2005-04-27
DE69939716D1 (de) 2008-11-20

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