ATE24617T1 - Direktzugriffsspeicher-anordnungen. - Google Patents

Direktzugriffsspeicher-anordnungen.

Info

Publication number
ATE24617T1
ATE24617T1 AT81304220T AT81304220T ATE24617T1 AT E24617 T1 ATE24617 T1 AT E24617T1 AT 81304220 T AT81304220 T AT 81304220T AT 81304220 T AT81304220 T AT 81304220T AT E24617 T1 ATE24617 T1 AT E24617T1
Authority
AT
Austria
Prior art keywords
latch circuit
read
write
data
random access
Prior art date
Application number
AT81304220T
Other languages
English (en)
Inventor
John Goodwin Spencer Ive
Alan Clive Thirlwall
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of ATE24617T1 publication Critical patent/ATE24617T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Television Signal Processing For Recording (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Holo Graphy (AREA)
  • Memory System (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
AT81304220T 1980-09-19 1981-09-15 Direktzugriffsspeicher-anordnungen. ATE24617T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8030300A GB2084361B (en) 1980-09-19 1980-09-19 Random access memory arrangements
EP81304220A EP0048586B1 (de) 1980-09-19 1981-09-15 Direktzugriffsspeicher-Anordnungen

Publications (1)

Publication Number Publication Date
ATE24617T1 true ATE24617T1 (de) 1987-01-15

Family

ID=10516165

Family Applications (1)

Application Number Title Priority Date Filing Date
AT81304220T ATE24617T1 (de) 1980-09-19 1981-09-15 Direktzugriffsspeicher-anordnungen.

Country Status (7)

Country Link
US (1) US4415994A (de)
EP (1) EP0048586B1 (de)
JP (1) JPS5786179A (de)
AT (1) ATE24617T1 (de)
CA (1) CA1164563A (de)
DE (1) DE3175775D1 (de)
GB (1) GB2084361B (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839357A (ja) * 1981-08-31 1983-03-08 Sanyo Electric Co Ltd Ｒａｍのアドレス方法
JPS58203694A (ja) * 1982-05-21 1983-11-28 Nec Corp メモリ回路
FR2536200B1 (fr) * 1982-11-15 1987-01-16 Helen Andre Unite de stockage temporaire de donnees organisee en file d'attente
FR2549995B1 (fr) * 1983-07-27 1985-09-27 Trt Telecom Radio Electr Dispositif permettant d'emmagasiner des donnees a un premier rythme et de les restituer a un deuxieme rythme
US4549283A (en) * 1983-09-06 1985-10-22 Rockwell International Corporation Digital time delay circuit with high speed and large delay capacity
DE3333225A1 (de) * 1983-09-14 1985-03-28 Siemens AG, 1000 Berlin und 8000 München Verfahren zur taktratenkonversion
JPS60175293A (ja) * 1984-02-21 1985-09-09 Toshiba Corp 半導体メモリ
US4766572A (en) * 1984-12-27 1988-08-23 Nec Corporation Semiconductor memory having a bypassable data output latch
JPH07118187B2 (ja) * 1985-05-27 1995-12-18 松下電器産業株式会社 先入れ先出し記憶装置
US5179692A (en) * 1985-08-07 1993-01-12 Seiko Epson Corporation Emulation device for driving a LCD with signals formatted for a CRT display
JPH084340B2 (ja) * 1985-08-07 1996-01-17 セイコーエプソン株式会社 インタ−フエイス装置
US4860246A (en) * 1985-08-07 1989-08-22 Seiko Epson Corporation Emulation device for driving a LCD with a CRT display
US4907070A (en) * 1985-10-17 1990-03-06 Ampex Corporation Time base corrector with memory mapped system control
US4763203A (en) * 1985-10-17 1988-08-09 Ampex Corporation Time base corrector with accurate timing corrector control
US5019906A (en) * 1985-10-17 1991-05-28 Ampex Corporation Time base corrector memory arrangement and memory control
US4733294A (en) * 1985-10-17 1988-03-22 Ampex Corporation Time base corrector memory arrangement and memory control
JPS6292991A (ja) * 1985-10-19 1987-04-28 富士通テン株式会社 画像表示方式
JPS62202537A (ja) * 1986-02-19 1987-09-07 Hitachi Ltd 半導体集積回路装置
IT1197273B (it) * 1986-09-25 1988-11-30 Telettra Lab Telefon Sistema e dispositivi per interfacciare macchine asincrone tra loro
US4789960A (en) * 1987-01-30 1988-12-06 Rca Licensing Corporation Dual port video memory system having semi-synchronous data input and data output
US4823302A (en) * 1987-01-30 1989-04-18 Rca Licensing Corporation Block oriented random access memory able to perform a data read, a data write and a data refresh operation in one block-access time
US4821226A (en) * 1987-01-30 1989-04-11 Rca Licensing Corporation Dual port video memory system having a bit-serial address input port
US5587962A (en) * 1987-12-23 1996-12-24 Texas Instruments Incorporated Memory circuit accommodating both serial and random access including an alternate address buffer register
US5093807A (en) 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
GB2215098B (en) * 1988-02-13 1992-09-09 Allan Mcintosh Memory mapping device
US4951143A (en) * 1989-05-24 1990-08-21 American Dynamics Corporation Memory configuration for unsynchronized input and output data streams
JPH0778989B2 (ja) * 1989-06-21 1995-08-23 株式会社東芝 半導体メモリ装置
US5107465A (en) * 1989-09-13 1992-04-21 Advanced Micro Devices, Inc. Asynchronous/synchronous pipeline dual mode memory access circuit and method
DE69032757T2 (de) * 1989-10-03 1999-06-24 Advanced Micro Devices, Inc., Sunnyvale, Calif. Speichervorrichtung
JP2560124B2 (ja) * 1990-03-16 1996-12-04 株式会社セガ・エンタープライゼス ビデオゲームシステム及び情報処理装置
GB9008932D0 (en) * 1990-04-20 1990-06-20 British Broadcasting Corp Synchronisation of digital audio signals
US5278957A (en) * 1991-04-16 1994-01-11 Zilog, Inc. Data transfer circuit for interfacing two bus systems that operate asynchronously with respect to each other
JPH07130166A (ja) * 1993-09-13 1995-05-19 Mitsubishi Electric Corp 半導体記憶装置および同期型半導体記憶装置
KR100816915B1 (ko) 2000-07-07 2008-03-26 모사이드 테크놀로지스, 인코포레이티드 일정한 액세스 레이턴시를 지닌 고속 ｄｒａｍ 및 메모리 소자

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3402398A (en) * 1964-08-31 1968-09-17 Bunker Ramo Plural content addressed memories with a common sensing circuit
US3560940A (en) * 1968-07-15 1971-02-02 Ibm Time shared interconnection apparatus
US4044335A (en) * 1974-09-23 1977-08-23 Rockwell International Corporation Memory cell output driver
GB1568379A (en) * 1976-02-19 1980-05-29 Micro Consultants Ltd Video store

Also Published As

Publication number Publication date
JPS5786179A (en) 1982-05-29
EP0048586A3 (en) 1983-07-20
US4415994A (en) 1983-11-15
DE3175775D1 (en) 1987-02-05
GB2084361B (en) 1984-11-21
EP0048586A2 (de) 1982-03-31
CA1164563A (en) 1984-03-27
JPH0217867B2 (de) 1990-04-23
EP0048586B1 (de) 1986-12-30
GB2084361A (en) 1982-04-07

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
EELA Cancelled due to lapse of time