DE69032757T2 - Speichervorrichtung - Google Patents

Speichervorrichtung

Info

Publication number
DE69032757T2
DE69032757T2 DE69032757T DE69032757T DE69032757T2 DE 69032757 T2 DE69032757 T2 DE 69032757T2 DE 69032757 T DE69032757 T DE 69032757T DE 69032757 T DE69032757 T DE 69032757T DE 69032757 T2 DE69032757 T2 DE 69032757T2
Authority
DE
Germany
Prior art keywords
port
bam
high speed
burst
random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032757T
Other languages
English (en)
Other versions
DE69032757D1 (de
Inventor
David C Wyland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69032757D1 publication Critical patent/DE69032757D1/de
Application granted granted Critical
Publication of DE69032757T2 publication Critical patent/DE69032757T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/62—Performing operations exclusively by counting total number of pulses ; Multiplication, division or derived operations using combined denominational and incremental processing by counters, i.e. without column shift

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Valve Device For Special Equipments (AREA)
  • Vehicle Body Suspensions (AREA)
  • Iron Core Of Rotating Electric Machines (AREA)
DE69032757T 1989-10-03 1990-09-17 Speichervorrichtung Expired - Fee Related DE69032757T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US41668089A 1989-10-03 1989-10-03

Publications (2)

Publication Number Publication Date
DE69032757D1 DE69032757D1 (de) 1998-12-17
DE69032757T2 true DE69032757T2 (de) 1999-06-24

Family

ID=23650876

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032757T Expired - Fee Related DE69032757T2 (de) 1989-10-03 1990-09-17 Speichervorrichtung

Country Status (4)

Country Link
EP (1) EP0421627B1 (de)
JP (1) JP3113916B2 (de)
AT (1) ATE173348T1 (de)
DE (1) DE69032757T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287486A (en) * 1989-10-05 1994-02-15 Mitsubishi Denki Kabushiki Kaisha DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts
JPH03122746A (ja) * 1989-10-05 1991-05-24 Mitsubishi Electric Corp Ｄｍａ制御方式
US5469398A (en) * 1991-09-10 1995-11-21 Silicon Systems, Inc. Selectable width, brustable FIFO
KR940009733B1 (ko) * 1992-09-21 1994-10-17 삼성전자 주식회사 디지탈 신호 처리장치
JPH07182863A (ja) * 1993-12-22 1995-07-21 Nec Corp 内部アドレス生成回路
CA2150151A1 (en) * 1994-08-05 1996-02-06 John H. Baldwin First-in first-out memory
FR2728379A1 (fr) * 1994-12-15 1996-06-21 Matra Mhs Dispositif de gestion d'une memoire fifo
KR100528450B1 (ko) * 1997-12-26 2006-02-10 삼성전자주식회사 동기형 메모리 장치
KR100306966B1 (ko) * 1998-08-04 2001-11-30 윤종용 동기형버스트반도체메모리장치
US7082071B2 (en) 2001-08-23 2006-07-25 Integrated Device Technology, Inc. Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes
US6795360B2 (en) 2001-08-23 2004-09-21 Integrated Device Technology, Inc. Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes
US7120075B1 (en) 2003-08-18 2006-10-10 Integrated Device Technology, Inc. Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2084361B (en) * 1980-09-19 1984-11-21 Sony Corp Random access memory arrangements
US4674032A (en) * 1984-04-02 1987-06-16 Unisys Corporation High-performance pipelined stack with over-write protection
US4875196A (en) * 1987-09-08 1989-10-17 Sharp Microelectronic Technology, Inc. Method of operating data buffer apparatus
GB8824373D0 (en) * 1988-10-18 1988-11-23 Hewlett Packard Ltd Buffer memory arrangement

Also Published As

Publication number Publication date
JPH03156789A (ja) 1991-07-04
ATE173348T1 (de) 1998-11-15
EP0421627B1 (de) 1998-11-11
EP0421627A2 (de) 1991-04-10
DE69032757D1 (de) 1998-12-17
EP0421627A3 (en) 1993-12-29
JP3113916B2 (ja) 2000-12-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee