DE60142044D1 - Ram-zellenarchitektur mit transparenter ununterbrochener auffrischung - Google Patents

Ram-zellenarchitektur mit transparenter ununterbrochener auffrischung

Info

Publication number
DE60142044D1
DE60142044D1 DE60142044T DE60142044T DE60142044D1 DE 60142044 D1 DE60142044 D1 DE 60142044D1 DE 60142044 T DE60142044 T DE 60142044T DE 60142044 T DE60142044 T DE 60142044T DE 60142044 D1 DE60142044 D1 DE 60142044D1
Authority
DE
Germany
Prior art keywords
transparent
memory cell
refresh
write
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60142044T
Other languages
English (en)
Inventor
Cyrus Afghahi
Sami Issa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of DE60142044D1 publication Critical patent/DE60142044D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE60142044T 2000-05-16 2001-05-14 Ram-zellenarchitektur mit transparenter ununterbrochener auffrischung Expired - Lifetime DE60142044D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US20452200P 2000-05-16 2000-05-16
US09/627,757 US6430098B1 (en) 2000-05-16 2000-07-28 Transparent continuous refresh RAM cell architecture
PCT/US2001/015486 WO2001088924A1 (en) 2000-05-16 2001-05-14 Transparent continuous refresh ram cell architecture

Publications (1)

Publication Number Publication Date
DE60142044D1 true DE60142044D1 (de) 2010-06-17

Family

ID=26899557

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60142044T Expired - Lifetime DE60142044D1 (de) 2000-05-16 2001-05-14 Ram-zellenarchitektur mit transparenter ununterbrochener auffrischung

Country Status (6)

Country Link
US (4) US6430098B1 (de)
EP (1) EP1287531B1 (de)
AT (1) ATE467215T1 (de)
AU (1) AU2001261549A1 (de)
DE (1) DE60142044D1 (de)
WO (1) WO2001088924A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002140890A (ja) * 2000-10-31 2002-05-17 Hitachi Ltd 半導体装置
JP2002298574A (ja) * 2001-03-29 2002-10-11 Internatl Business Mach Corp <Ibm> Ｄｒａｍ及びｄｒａｍのリフレッシュ方法
EP1376348A3 (de) * 2002-06-27 2007-08-22 Fujitsu Limited Verfahren und Vorrichtung zur Erzeugung eines Lademoduls
US7002867B2 (en) 2002-09-25 2006-02-21 Infineon Technologies Aktiengesellschaft Refresh control circuit for ICs with a memory array
US7099179B2 (en) * 2003-12-22 2006-08-29 Unity Semiconductor Corporation Conductive memory array having page mode and burst mode write capability
US20060054977A1 (en) * 2004-09-16 2006-03-16 Intel Corporation Charge storage memory cell
US7129749B1 (en) 2004-10-27 2006-10-31 Lattice Semiconductor Corporation Programmable logic device having a configurable DRAM with transparent refresh
US7275131B2 (en) * 2004-12-22 2007-09-25 International Business Machines Corporation Cache refresh algorithm and method
US7797511B2 (en) * 2007-01-05 2010-09-14 Qimonda North America Corp. Memory refresh system and method
US20110093763A1 (en) * 2008-06-17 2011-04-21 Nxp B.V. Electrical circuit comprising a dynamic random access memory (dram) with concurrent refresh and read or write, and method to perform concurent
US9104581B2 (en) 2010-06-24 2015-08-11 International Business Machines Corporation eDRAM refresh in a high performance cache architecture
US8244972B2 (en) 2010-06-24 2012-08-14 International Business Machines Corporation Optimizing EDRAM refresh rates in a high performance cache architecture
TWI463432B (zh) * 2012-10-05 2014-12-01 Genesys Logic Inc 圖像資料處理方法
US9911485B2 (en) * 2013-11-11 2018-03-06 Qualcomm Incorporated Method and apparatus for refreshing a memory cell
US9947386B2 (en) * 2014-09-21 2018-04-17 Advanced Micro Devices, Inc. Thermal aware data placement and compute dispatch in a memory system
JP6180450B2 (ja) * 2015-02-02 2017-08-16 キヤノン株式会社 制御装置、制御装置の制御方法及びプログラム
US10468087B2 (en) * 2016-07-28 2019-11-05 Micron Technology, Inc. Apparatuses and methods for operations in a self-refresh state
US10818359B2 (en) 2018-12-21 2020-10-27 Micron Technology, Inc. Apparatuses and methods for organizing data in a memory device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599180A (en) 1968-11-29 1971-08-10 Gen Instrument Corp Random access read-write memory system having data refreshing capabilities and memory cell therefor
US3699544A (en) 1971-05-26 1972-10-17 Gen Electric Three transistor memory cell
JPS5760586A (en) * 1980-09-26 1982-04-12 Matsushita Electric Ind Co Ltd Random access memory
JPS6211977A (ja) 1985-07-10 1987-01-20 Toshiba Corp 画像メモリ
US5007022A (en) 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
US5315130A (en) * 1990-03-30 1994-05-24 Tactical Fabs, Inc. Very high density wafer scale device architecture
US5291443A (en) * 1991-06-26 1994-03-01 Micron Technology, Inc. Simultaneous read and refresh of different rows in a dram
US5596545A (en) 1995-12-04 1997-01-21 Ramax, Inc. Semiconductor memory device with internal self-refreshing
US5808932A (en) * 1996-12-23 1998-09-15 Lsi Logic Corporation Memory system which enables storage and retrieval of more than two states in a memory cell
US5963497A (en) * 1998-05-18 1999-10-05 Silicon Aquarius, Inc. Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same
US5995433A (en) * 1998-05-22 1999-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Three-transistor type DRAM with a refresh circuit
US5999474A (en) * 1998-10-01 1999-12-07 Monolithic System Tech Inc Method and apparatus for complete hiding of the refresh of a semiconductor memory
JP2000163956A (ja) * 1998-11-24 2000-06-16 Sharp Corp 半導体記憶装置

Also Published As

Publication number Publication date
US6717863B2 (en) 2004-04-06
US6600677B2 (en) 2003-07-29
US20030202384A1 (en) 2003-10-30
AU2001261549A1 (en) 2001-11-26
ATE467215T1 (de) 2010-05-15
US6430098B1 (en) 2002-08-06
WO2001088924A1 (en) 2001-11-22
US20040184335A1 (en) 2004-09-23
US6888761B2 (en) 2005-05-03
EP1287531B1 (de) 2010-05-05
US20020057617A1 (en) 2002-05-16
EP1287531A1 (de) 2003-03-05

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