AT518350A3 - Halbleiterwafer und Verfahren zum Prüfen eines Halbleiterwafers - Google Patents
Halbleiterwafer und Verfahren zum Prüfen eines Halbleiterwafers Download PDFInfo
- Publication number
- AT518350A3 AT518350A3 ATA9400/2015A AT94002015A AT518350A3 AT 518350 A3 AT518350 A3 AT 518350A3 AT 94002015 A AT94002015 A AT 94002015A AT 518350 A3 AT518350 A3 AT 518350A3
- Authority
- AT
- Austria
- Prior art keywords
- layer
- semiconductor wafer
- wafer
- crystal
- group iii
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 7
- 239000013078 crystal Substances 0.000 abstract 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 3
- 150000004767 nitrides Chemical class 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 230000001629 suppression Effects 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 2
- 230000000704 physical effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
- G01N23/20008—Constructional details of analysers, e.g. characterised by X-ray source, detector or optical system; Accessories therefor; Preparing specimens therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02527—Carbon, e.g. diamond-like carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/205—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2223/00—Investigating materials by wave or particle radiation
- G01N2223/60—Specific applications or type of materials
- G01N2223/611—Specific applications or type of materials patterned objects; electronic devices
- G01N2223/6116—Specific applications or type of materials patterned objects; electronic devices semiconductor wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Abstract
Durch die vorliegende Erfindung wird ein Halbleiterwafer (100) bereitgestellt, der durch Ausbilden einer Gruppe-III-Nitridhalbleiterschicht durch epitaktisches Wachstum auf einem Si-Wafer (102) erhalten wird, wobei die Gruppe-III-Nitrid-Halbleiterschicht zufriedenstellende Eigenschaften erzielen kann, wie beispielsweise die erforderliche Spannungsfestigkeit, die physikalischen Eigenschaften, wie beispielsweise der Schichtwiderstand zum zuverlässigen Erzielen einer geeigneten Gleichmäßigkeit innerhalb der Ebene, und der Halbleiterwafer (100) sich nur wenig verzieht. Es wird ein Halbleiterwafer (100) bereitgestellt, bei dem eine Nitridkristallschicht auf einem Siliziumwafer (102) eine Reaktionsunterdrückungsschicht (104), die konfiguriert ist, die Reaktion zwischen einem Siliziumatom und einem Gruppe-lIl-Atom zu unterdrücken, eine spannungserzeugende Schicht (106), die konfiguriert ist, eine Druckspannung zu erzeugen, und eine aktive Schicht (108) aufweist, in der ein elektronisches Element ausgebildet werden soll, wobei die Reaktionsunterdrückungsschicht (104), die spannungserzeugende Schicht (106) und die aktive Schicht (108) in dieser Reihenfolge derart angeordnet sind, dass die Reaktionsunterdrückungsschicht (104) am nächsten zum Siliziumwafer (102) angeordnet ist, und wobei die spannungserzeugende Schicht (106) eine erste Kristallschicht (106a) mit einer Volumenkristallgitterkonstante a1 und eine zweite Kristallschicht (106b) aufweist, die mit einer der aktiven Schicht zugewandten Oberfläche der ersten Kristallschicht (106a) in Kontakt steht, wobei die zweite Kristallschicht (106b) eine Volumenkristallgitterkonstante a2 (a1 < a2) aufweist.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014227596 | 2014-11-07 | ||
JP2014227595 | 2014-11-07 | ||
JP2014227593 | 2014-11-07 | ||
JP2014227594 | 2014-11-07 | ||
PCT/JP2015/081411 WO2016072521A1 (ja) | 2014-11-07 | 2015-11-06 | 半導体基板および半導体基板の検査方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
AT518350A2 AT518350A2 (de) | 2017-09-15 |
AT518350A3 true AT518350A3 (de) | 2019-06-15 |
Family
ID=55909244
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ATA9400/2015A AT518350A3 (de) | 2014-11-07 | 2015-11-06 | Halbleiterwafer und Verfahren zum Prüfen eines Halbleiterwafers |
Country Status (8)
Country | Link |
---|---|
US (1) | US10763332B2 (de) |
JP (1) | JP6656160B2 (de) |
KR (1) | KR102416870B1 (de) |
CN (1) | CN107078034B (de) |
AT (1) | AT518350A3 (de) |
DE (1) | DE112015005069T5 (de) |
TW (1) | TWI657578B (de) |
WO (1) | WO2016072521A1 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6796467B2 (ja) | 2016-11-30 | 2020-12-09 | 住友化学株式会社 | 半導体基板 |
JP6859084B2 (ja) * | 2016-11-30 | 2021-04-14 | 住友化学株式会社 | 半導体基板 |
JP6868389B2 (ja) * | 2016-12-27 | 2021-05-12 | 住友化学株式会社 | 半導体基板および電子デバイス |
JP6717267B2 (ja) * | 2017-07-10 | 2020-07-01 | 株式会社Sumco | シリコンウェーハの製造方法 |
JP2021027297A (ja) * | 2019-08-08 | 2021-02-22 | 住友化学株式会社 | エピタキシャル基板およびその製造方法 |
KR20210045835A (ko) * | 2019-10-17 | 2021-04-27 | 삼성전자주식회사 | 반도체 박막 구조체 및 이를 포함하는 전자 소자 |
CN110783176B (zh) * | 2019-10-30 | 2022-07-12 | 广西大学 | 一种低应力半导体材料制备方法 |
US20220029007A1 (en) * | 2020-07-24 | 2022-01-27 | Vanguard International Semiconductor Corporation | Semiconductor structure and semiconductor device |
JP2023096570A (ja) * | 2021-12-27 | 2023-07-07 | 国立研究開発法人産業技術総合研究所 | 化合物半導体基板 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013069939A (ja) * | 2011-09-23 | 2013-04-18 | Sumitomo Chemical Co Ltd | 半導体基板および半導体基板の製造方法 |
JP2013145782A (ja) * | 2012-01-13 | 2013-07-25 | Sharp Corp | ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ |
US20140015608A1 (en) * | 2012-07-10 | 2014-01-16 | Fujitsu Limited | Compound semiconductor device, method for producing the same, power-supply unit, and high-frequency amplifier |
US20140209862A1 (en) * | 2011-07-11 | 2014-07-31 | Dowa Electronics Materials Co., Ltd. | Group iii nitride epitaxial substrate and method for manufacturing the same |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6777253B2 (en) * | 2000-12-20 | 2004-08-17 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor, method for fabricating semiconductor substrate, and semiconductor light emitting device |
US7112830B2 (en) * | 2002-11-25 | 2006-09-26 | Apa Enterprises, Inc. | Super lattice modification of overlying transistor |
JP5194334B2 (ja) | 2004-05-18 | 2013-05-08 | 住友電気工業株式会社 | Iii族窒化物半導体デバイスの製造方法 |
JP5136765B2 (ja) | 2005-05-02 | 2013-02-06 | 日亜化学工業株式会社 | 窒化物系半導体素子及びその製造方法 |
JP5224311B2 (ja) | 2007-01-05 | 2013-07-03 | 古河電気工業株式会社 | 半導体電子デバイス |
JP5133927B2 (ja) | 2009-03-26 | 2013-01-30 | コバレントマテリアル株式会社 | 化合物半導体基板 |
EP2432005A4 (de) * | 2009-05-11 | 2015-05-27 | Dowa Electronics Materials Co | Epitaktisches substrat für elektronische geräte und verfahren zu seiner herstellung |
JP5188545B2 (ja) * | 2009-09-14 | 2013-04-24 | コバレントマテリアル株式会社 | 化合物半導体基板 |
JP5804768B2 (ja) * | 2011-05-17 | 2015-11-04 | 古河電気工業株式会社 | 半導体素子及びその製造方法 |
JP5362085B1 (ja) * | 2012-09-05 | 2013-12-11 | 株式会社東芝 | 窒化物半導体ウェーハ、窒化物半導体素子及び窒化物半導体ウェーハの製造方法 |
JP6120204B2 (ja) * | 2012-09-06 | 2017-04-26 | パナソニック株式会社 | エピタキシャルウェハ及びその製造方法、紫外発光デバイス |
JP6090899B2 (ja) * | 2012-09-06 | 2017-03-08 | パナソニック株式会社 | エピタキシャルウェハの製造方法 |
JP2015070064A (ja) * | 2013-09-27 | 2015-04-13 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
-
2015
- 2015-11-06 TW TW104136661A patent/TWI657578B/zh active
- 2015-11-06 AT ATA9400/2015A patent/AT518350A3/de not_active Application Discontinuation
- 2015-11-06 CN CN201580059596.5A patent/CN107078034B/zh active Active
- 2015-11-06 DE DE112015005069.8T patent/DE112015005069T5/de not_active Ceased
- 2015-11-06 JP JP2016557840A patent/JP6656160B2/ja active Active
- 2015-11-06 KR KR1020177014968A patent/KR102416870B1/ko active IP Right Grant
- 2015-11-06 WO PCT/JP2015/081411 patent/WO2016072521A1/ja active Application Filing
-
2017
- 2017-05-04 US US15/586,526 patent/US10763332B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140209862A1 (en) * | 2011-07-11 | 2014-07-31 | Dowa Electronics Materials Co., Ltd. | Group iii nitride epitaxial substrate and method for manufacturing the same |
JP2013069939A (ja) * | 2011-09-23 | 2013-04-18 | Sumitomo Chemical Co Ltd | 半導体基板および半導体基板の製造方法 |
JP2013145782A (ja) * | 2012-01-13 | 2013-07-25 | Sharp Corp | ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ |
US20140015608A1 (en) * | 2012-07-10 | 2014-01-16 | Fujitsu Limited | Compound semiconductor device, method for producing the same, power-supply unit, and high-frequency amplifier |
Also Published As
Publication number | Publication date |
---|---|
CN107078034A (zh) | 2017-08-18 |
JPWO2016072521A1 (ja) | 2017-09-21 |
KR20170077227A (ko) | 2017-07-05 |
KR102416870B1 (ko) | 2022-07-05 |
WO2016072521A1 (ja) | 2016-05-12 |
AT518350A2 (de) | 2017-09-15 |
DE112015005069T5 (de) | 2017-07-20 |
TWI657578B (zh) | 2019-04-21 |
US20170236906A1 (en) | 2017-08-17 |
JP6656160B2 (ja) | 2020-03-04 |
US10763332B2 (en) | 2020-09-01 |
TW201624695A (zh) | 2016-07-01 |
CN107078034B (zh) | 2020-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AT518350A3 (de) | Halbleiterwafer und Verfahren zum Prüfen eines Halbleiterwafers | |
DE102012202643B4 (de) | Hohlraumstrukturen für mems-bauelemente | |
DE102011076845B4 (de) | Niedrigtemperaturbindeverfahren und Heterostruktur | |
EP4269996A3 (de) | Abscheidung einer passivierungsschicht auf eine graphenfolie | |
DE102005053767A1 (de) | MEMS-Mikrofon, Verfahren zur Herstellung und Verfahren zum Einbau | |
EP2806283A3 (de) | Dreidimensionaler hallsensor zum detektieren eines räumlichen magnetfeldes | |
EP3442031A3 (de) | Halbleiterbauelement und herstellungsverfahren dafür | |
DE112014006413T5 (de) | Herstellungsverfahren für epitaktischen Siliciumwafer und epitaktischer Siliciumwafer | |
EP2348295A3 (de) | Druckkraftmesseinrichtung | |
EP3069821A3 (de) | Verfahren zur fertigung eines bauteils | |
CN109863259A8 (zh) | 母板、母板的制造方法、掩模的制造方法及oled像素蒸镀方法 | |
GB2541146A (en) | Method of manufacturing a germanium-on-insulator substrate | |
DE102017121055A1 (de) | Verfahren und system einer dehnungsmessstreifenherstellung | |
SG11201903703WA (en) | Method for manufacturing electronic apparatus, adhesive film for manufacturing electronic apparatus, and electronic component testing apparatus | |
DE102010029709A1 (de) | Mikromechanisches Bauelement | |
DE102019101142B4 (de) | Verfahren zum Herstellen einer mehrschichtigen monokristallinen Siliziumfolie | |
EP1837907A2 (de) | Leistungshalbleiterbauelement mit Passivierungsschicht und zugehöriges Herstellungsverfahren | |
AT525618A5 (de) | Verfahren zum Beschichten und Bonden von Substraten | |
EP3016485A3 (de) | Elektrisches gerät für den einsatz in einem kontaminierenden medium und verfahren zur herstellung eines solchen | |
EP2803635A3 (de) | Vorrichtung mit einer Feder und einem daran aufgehängten Element und Verfahren zum Herstellen desselben | |
AT517646A5 (de) | Substratverbund, Verfahren und Vorrichtung zum Bonden von Substraten | |
EP3226269A3 (de) | Leistungshalbleitereinrichtung | |
WO2018049076A3 (en) | Silicon carbide electromechanical structure, devices and method | |
AT520249A5 (de) | Verfahren zur Herstellung eines leitenden Mehrfachsubstratstapels | |
EP2644740A3 (de) | Verfahren zum Herstellen einer Dünnschicht auf einem Substrat |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
REJ | Rejection |
Effective date: 20221115 |