ZA85181B - Refresh generator system for a dynamic memory - Google Patents

Refresh generator system for a dynamic memory

Info

Publication number
ZA85181B
ZA85181B ZA85181A ZA85181A ZA85181B ZA 85181 B ZA85181 B ZA 85181B ZA 85181 A ZA85181 A ZA 85181A ZA 85181 A ZA85181 A ZA 85181A ZA 85181 B ZA85181 B ZA 85181B
Authority
ZA
South Africa
Prior art keywords
signal
refresh
circuit
memory
hold
Prior art date
Application number
ZA85181A
Other languages
English (en)
Inventor
Mark Edward Dean
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of ZA85181B publication Critical patent/ZA85181B/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Air Bags (AREA)
  • Control Of Eletrric Generators (AREA)
  • Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
  • Superstructure Of Vehicle (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transmitters (AREA)
ZA85181A 1984-02-27 1985-01-08 Refresh generator system for a dynamic memory ZA85181B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/584,032 US4575826A (en) 1984-02-27 1984-02-27 Refresh generator system for a dynamic memory

Publications (1)

Publication Number Publication Date
ZA85181B true ZA85181B (en) 1985-10-30

Family

ID=24335623

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA85181A ZA85181B (en) 1984-02-27 1985-01-08 Refresh generator system for a dynamic memory

Country Status (14)

Country Link
US (1) US4575826A (xx)
EP (1) EP0153469B1 (xx)
JP (1) JPS60182598A (xx)
KR (1) KR890001311B1 (xx)
AT (1) ATE43194T1 (xx)
BR (1) BR8500629A (xx)
CA (1) CA1211857A (xx)
DE (1) DE3478258D1 (xx)
ES (1) ES538881A0 (xx)
GB (1) GB8431255D0 (xx)
HK (1) HK102489A (xx)
MX (1) MX158687A (xx)
PH (1) PH23949A (xx)
ZA (1) ZA85181B (xx)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4723204A (en) * 1982-07-07 1988-02-02 Gte Automatic Electric Incorporated Dynamic RAM refresh circuit
JPS621187A (ja) * 1985-06-26 1987-01-07 Toshiba Corp ダイナミツクメモリのアクセス制御方式
US4754425A (en) * 1985-10-18 1988-06-28 Gte Communication Systems Corporation Dynamic random access memory refresh circuit selectively adapted to different clock frequencies
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
JPH02166692A (ja) * 1988-12-20 1990-06-27 Sanyo Electric Co Ltd ダイナミツクメモリのリフレツシユ方法
US5060138A (en) * 1990-08-31 1991-10-22 Advanced Micro Devices, Inc. Apparatus for use with a computing device for generating a substitute acknowledgement to an input when the computing device is in an operational hiatus
US5940851A (en) * 1996-11-27 1999-08-17 Monolithic Systems, Inc. Method and apparatus for DRAM refresh using master, slave and self-refresh modes
US6262936B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Random access memory having independent read port and write port and process for writing to and reading from the same
US6262937B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
US6069839A (en) * 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4332008A (en) * 1976-03-09 1982-05-25 Zilog, Inc. Microprocessor apparatus and method
JPS5694580A (en) * 1979-12-27 1981-07-31 Fujitsu Ltd Direct memory access control device
JPS5760588A (en) * 1980-09-26 1982-04-12 Toshiba Corp Memory controller
US4556952A (en) * 1981-08-12 1985-12-03 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
JPS58215789A (ja) * 1982-06-07 1983-12-15 Hitachi Ltd ダイナミツクｒａｍのリフレツシユ回路
JPS60151894A (ja) * 1984-01-20 1985-08-09 Hitachi Ltd ダイナミツクｒａｍのリフレツシユ回路

Also Published As

Publication number Publication date
JPS60182598A (ja) 1985-09-18
CA1211857A (en) 1986-09-23
KR890001311B1 (ko) 1989-04-29
ATE43194T1 (de) 1989-06-15
ES8602321A1 (es) 1985-11-01
EP0153469A3 (en) 1986-12-03
ES538881A0 (es) 1985-11-01
US4575826B1 (xx) 1990-02-06
EP0153469B1 (en) 1989-05-17
KR860002251A (ko) 1986-04-24
EP0153469A2 (en) 1985-09-04
US4575826A (en) 1986-03-11
MX158687A (es) 1989-02-27
GB8431255D0 (en) 1985-01-23
HK102489A (en) 1990-01-05
BR8500629A (pt) 1985-10-01
PH23949A (en) 1990-01-23
DE3478258D1 (en) 1989-06-22

Similar Documents

Publication Publication Date Title
US4575826B1 (xx)
GB1493818A (en) Information processor input/output
JPS5580164A (en) Main memory constitution control system
KR840001369A (ko) 동적 메모리의 리프 레시회로
EP0285329A3 (en) Dual-port timing controller
EP0307945A3 (en) Memory control apparatus for use in a data processing system
JPS5592953A (en) Information processor
KR830010423A (ko) 데이터 처리 시스템의 데이터 교환방식
JPS5661087A (en) Control system for dynamic memory
JPS6478362A (en) One connection preparation of several data processors for central clock control multi-line system
JPS57117056A (en) Microcomputer device
JPS57196334A (en) Memory interface
JPS6465617A (en) Logic circuit and computer
GB2016757A (en) Display Terminal
JP2617132B2 (ja) ダイレクトメモリアクセス方式
ES8103407A1 (es) Perfeccionamientos introducidos en un aparato de tratamien- to de datos de informacion.
JPS55139691A (en) Memory circuit control system
JPS55120252A (en) Error control system
JPS56108158A (en) Memory device
JPS57147749A (en) Picture data transfer device
JPS5720996A (en) Memory diagnostic control system
JPS559278A (en) Constitution system of bus line for information processor
JPS6488668A (en) Bus control system
JPS5721146A (en) Data transmission system
JPS56159745A (en) Information processor