KR860002251A - 다이나믹 메모리용 리프레시 생성기 시스템 - Google Patents

다이나믹 메모리용 리프레시 생성기 시스템

Info

Publication number
KR860002251A
KR860002251A KR1019840006748A KR840006748A KR860002251A KR 860002251 A KR860002251 A KR 860002251A KR 1019840006748 A KR1019840006748 A KR 1019840006748A KR 840006748 A KR840006748 A KR 840006748A KR 860002251 A KR860002251 A KR 860002251A
Authority
KR
South Korea
Prior art keywords
signal
refresh
circuit
memory
hold
Prior art date
Application number
KR1019840006748A
Other languages
English (en)
Other versions
KR890001311B1 (ko
Inventor
에드워드 딘 마크
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR860002251A publication Critical patent/KR860002251A/ko
Application granted granted Critical
Publication of KR890001311B1 publication Critical patent/KR890001311B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Transmitters (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
  • Superstructure Of Vehicle (AREA)
  • Air Bags (AREA)
  • Control Of Eletrric Generators (AREA)
KR1019840006748A 1984-02-27 1984-10-30 다이나믹 메모리용 리프레시 생성기 시스템 KR890001311B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/584,032 US4575826A (en) 1984-02-27 1984-02-27 Refresh generator system for a dynamic memory
US584,032 1984-02-27

Publications (2)

Publication Number Publication Date
KR860002251A true KR860002251A (ko) 1986-04-24
KR890001311B1 KR890001311B1 (ko) 1989-04-29

Family

ID=24335623

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840006748A KR890001311B1 (ko) 1984-02-27 1984-10-30 다이나믹 메모리용 리프레시 생성기 시스템

Country Status (14)

Country Link
US (1) US4575826A (ko)
EP (1) EP0153469B1 (ko)
JP (1) JPS60182598A (ko)
KR (1) KR890001311B1 (ko)
AT (1) ATE43194T1 (ko)
BR (1) BR8500629A (ko)
CA (1) CA1211857A (ko)
DE (1) DE3478258D1 (ko)
ES (1) ES8602321A1 (ko)
GB (1) GB8431255D0 (ko)
HK (1) HK102489A (ko)
MX (1) MX158687A (ko)
PH (1) PH23949A (ko)
ZA (1) ZA85181B (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4723204A (en) * 1982-07-07 1988-02-02 Gte Automatic Electric Incorporated Dynamic RAM refresh circuit
JPS621187A (ja) * 1985-06-26 1987-01-07 Toshiba Corp ダイナミツクメモリのアクセス制御方式
US4754425A (en) * 1985-10-18 1988-06-28 Gte Communication Systems Corporation Dynamic random access memory refresh circuit selectively adapted to different clock frequencies
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
US5193193A (en) * 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
JPH02166692A (ja) * 1988-12-20 1990-06-27 Sanyo Electric Co Ltd ダイナミツクメモリのリフレツシユ方法
US5060138A (en) * 1990-08-31 1991-10-22 Advanced Micro Devices, Inc. Apparatus for use with a computing device for generating a substitute acknowledgement to an input when the computing device is in an operational hiatus
US5940851A (en) * 1996-11-27 1999-08-17 Monolithic Systems, Inc. Method and apparatus for DRAM refresh using master, slave and self-refresh modes
US6262936B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Random access memory having independent read port and write port and process for writing to and reading from the same
US6262937B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
US6069839A (en) * 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4332008A (en) * 1976-03-09 1982-05-25 Zilog, Inc. Microprocessor apparatus and method
JPS5694580A (en) * 1979-12-27 1981-07-31 Fujitsu Ltd Direct memory access control device
JPS5760588A (en) * 1980-09-26 1982-04-12 Toshiba Corp Memory controller
US4556952A (en) * 1981-08-12 1985-12-03 International Business Machines Corporation Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
JPS58215789A (ja) * 1982-06-07 1983-12-15 Hitachi Ltd ダイナミツクｒａｍのリフレツシユ回路
JPS60151894A (ja) * 1984-01-20 1985-08-09 Hitachi Ltd ダイナミツクｒａｍのリフレツシユ回路

Also Published As

Publication number Publication date
ES538881A0 (es) 1985-11-01
DE3478258D1 (en) 1989-06-22
ZA85181B (en) 1985-10-30
HK102489A (en) 1990-01-05
US4575826B1 (ko) 1990-02-06
EP0153469A3 (en) 1986-12-03
MX158687A (es) 1989-02-27
EP0153469B1 (en) 1989-05-17
KR890001311B1 (ko) 1989-04-29
JPS60182598A (ja) 1985-09-18
PH23949A (en) 1990-01-23
GB8431255D0 (en) 1985-01-23
BR8500629A (pt) 1985-10-01
EP0153469A2 (en) 1985-09-04
US4575826A (en) 1986-03-11
CA1211857A (en) 1986-09-23
ES8602321A1 (es) 1985-11-01
ATE43194T1 (de) 1989-06-15

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Legal Events

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G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
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Payment date: 20040216

Year of fee payment: 16

EXPY Expiration of term