JPS56159745A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS56159745A JPS56159745A JP6363980A JP6363980A JPS56159745A JP S56159745 A JPS56159745 A JP S56159745A JP 6363980 A JP6363980 A JP 6363980A JP 6363980 A JP6363980 A JP 6363980A JP S56159745 A JPS56159745 A JP S56159745A
- Authority
- JP
- Japan
- Prior art keywords
- refresh
- returned
- contents
- memory
- modules
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To diagnose a memory bus, etc., in a refresh operation period, by providing a CPU with a priority processing circuit. CONSTITUTION:A refresh control circuit 26 outputs a refresh operation request signal REF to a main memory 22, composed of elements DRAM, at constant intervals. This signal has higher priority than memory access request signals outputted from active modules 241-24n. Once the signal REF is accepted by a priority processing circuit 27, a memory access control circuit 28 outputs a refresh start signal to the main memory 22, which is returned by modules 241-24n via a refresh acceptance signal line 29. In a CPU21, on the other hand, the contents of an address register are held and also sent out to modules 241-24n via a memory bus 25 to be returned there. The CPU compares the returned contents with the previoulsy held contents of the register to diagnose a bus.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6363980A JPS56159745A (en) | 1980-05-14 | 1980-05-14 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6363980A JPS56159745A (en) | 1980-05-14 | 1980-05-14 | Information processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56159745A true JPS56159745A (en) | 1981-12-09 |
JPS6238741B2 JPS6238741B2 (en) | 1987-08-19 |
Family
ID=13235120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6363980A Granted JPS56159745A (en) | 1980-05-14 | 1980-05-14 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56159745A (en) |
-
1980
- 1980-05-14 JP JP6363980A patent/JPS56159745A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6238741B2 (en) | 1987-08-19 |
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