WO2024210103A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

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Publication number
WO2024210103A1
WO2024210103A1 PCT/JP2024/013497 JP2024013497W WO2024210103A1 WO 2024210103 A1 WO2024210103 A1 WO 2024210103A1 JP 2024013497 W JP2024013497 W JP 2024013497W WO 2024210103 A1 WO2024210103 A1 WO 2024210103A1
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WIPO (PCT)
Prior art keywords
dummy electrode
electrode
dummy
multilayer ceramic
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/013497
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English (en)
French (fr)
Japanese (ja)
Inventor
悟 直川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to CN202480024435.1A priority Critical patent/CN120937097A/zh
Priority to KR1020257033047A priority patent/KR20250161590A/ko
Priority to JP2024553847A priority patent/JP7675293B2/ja
Publication of WO2024210103A1 publication Critical patent/WO2024210103A1/ja
Priority to JP2025072860A priority patent/JP2025108748A/ja
Priority to US19/191,004 priority patent/US12537140B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor

Definitions

  • This disclosure relates to multilayer ceramic capacitors.
  • Patent Document 1 Conventional technology for multilayer ceramic capacitors is described, for example, in Patent Document 1.
  • the multilayer ceramic capacitor of the present disclosure is a substantially rectangular parallelepiped laminate including an active portion formed by alternately stacking dielectric layers and internal electrode layers, and a first covering portion and a second covering portion located at both ends of the active portion in a stacking direction of the dielectric layers and the internal electrode layers, the laminate having a first surface and a second surface opposed to each other in the stacking direction, a first end surface and a second end surface opposed to each other, and a first side surface and a second side surface opposed to each other; a first external electrode located from the first end surface to the first surface, the second surface, the first side surface, and the second side surface; a second external electrode located from the second end surface to the first surface, the second surface, the first side surface, and the second side surface; the first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layer; the first covering portion has a first dielectric portion, and a first dummy electrode and a second dummy electrode located at both ends of the first dielectric portion in a
  • FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention.
  • FIG. 2 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 1 .
  • 3 is a cross-sectional view taken along line III-III in FIG. 1.
  • 4 is a cross-sectional view taken along line IV-IV in FIG. 3.
  • 1 is a cross-sectional view showing a multilayer ceramic capacitor according to an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing another example of the multilayer ceramic capacitor according to the present embodiment.
  • FIG. 4 is a cross-sectional view showing another example of the multilayer ceramic capacitor according to the present embodiment.
  • FIG. 4 is a cross-sectional view showing another example of the multilayer ceramic capacitor according to the present embodiment.
  • FIG. 4 is a cross-sectional view showing another example of the multilayer ceramic capacitor according to the present embodiment.
  • FIG. 2 is a perspective view illustrating an example of a process for producing a base laminate.
  • FIG. 2 is a perspective view showing an example of a base laminate.
  • FIG. 2 is a perspective view showing an example of a laminate obtained by cutting a base laminate.
  • FIG. 11 is a perspective view illustrating another example of the process for producing the base laminate.
  • FIG. 11 is a perspective view showing another example of the base laminate.
  • FIG. 4 is a perspective view showing another example of a laminate obtained by cutting the base laminate.
  • FIG. 11 is a perspective view showing a multilayer ceramic capacitor according to another embodiment.
  • FIG. 16 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 15 .
  • FIG. 16 is a cross-sectional view taken along the line XVII-XVII in FIG. 15.
  • 18 is a cross-sectional view taken along the line XVIIIA-XVIIIA in FIG. 17.
  • 18 is a cross-sectional view taken along the line XVIIIB-XVIIIB in FIG. 17.
  • FIG. 11 is a perspective view showing a multilayer ceramic capacitor according to still another embodiment.
  • FIG. 20 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 19 .
  • 20 is a cross-sectional view taken along the line XXI-XXI in FIG. 19.
  • 22 is a cross-sectional view taken along the line XXIIA-XXIIA in FIG. 21 .
  • FIG. 11 is a perspective view showing a multilayer ceramic capacitor according to still another embodiment.
  • FIG. 24 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 23 .
  • This is a cross-sectional view taken along the cutting line XXV-XXV in Figure 23.
  • 26 is a cross-sectional view taken along the line XXVIA-XXVIA in FIG. 25.
  • 26 is a cross-sectional view taken along the line XXVIB-XXVIB in FIG. 25.
  • 26 is a cross-sectional view taken along the section line XXVIC-XXVIC of FIG. 25.
  • FIG. 11 is a cross-sectional view showing a multilayer ceramic capacitor according to still another embodiment.
  • FIG. 11 is a cross-sectional view showing a multilayer ceramic capacitor according to still another embodiment.
  • FIG. 11 is a perspective view showing a laminate of a multilayer ceramic capacitor according to still another embodiment.
  • a multilayer ceramic capacitor is composed of a laminate in which dielectric layers and internal electrode layers are alternately stacked, and an external electrode formed on the surface of the laminate and connected to the internal electrode layer.
  • a plating film as the external electrode, the multilayer ceramic capacitor can be made smaller.
  • the bonding strength between the laminate and the plating film is weak, the plating film may peel off.
  • the aforementioned Patent Document 1 discloses providing the laminate with multiple dummy electrode layers that are bonded to the plating film in order to increase the bonding strength between the laminate and the plating film.
  • the manufacturing process for multilayer ceramic capacitors using conventional technology includes a process of firing an unfired laminate and then barrel polishing the laminate to fully expose the internal electrode layers on the surface of the laminate.
  • the multilayer ceramic capacitor described in Patent Document 1 has many interfaces of different materials between the dielectric layers and dummy electrode layers at the corners of the laminate, so that when the collision force between the polishing medium and other laminates applied to the corners of the laminate becomes excessive, delamination between the dielectric layers and the dummy electrode layers can occur. As a result, the reliability of the multilayer ceramic capacitor can be degraded.
  • any direction may be considered to be up or down, but in this specification, for convenience, a Cartesian coordinate system xyz is defined in some drawings.
  • the positive side in the z-axis direction is considered to be up, and terms such as top surface and bottom surface may be used.
  • the x-axis direction is also referred to as the first direction or length direction.
  • the y-axis direction is also referred to as the second direction or width direction.
  • the z-axis direction is also referred to as the third direction, height direction, or stacking direction.
  • FIG. 1 is a perspective view showing a multilayer ceramic capacitor of this embodiment
  • FIG. 2 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 1.
  • FIG. 3 is a cross-sectional view taken along the cutting line III-III in FIG. 1
  • FIG. 4 is a cross-sectional view taken along the cutting line IV-IV in FIG. 3. Note that in FIG. 2, for ease of illustration, the exposed portions of the internal electrode layers and the first to fourth dummy electrodes on the surface of the laminate are shown hatched.
  • the multilayer ceramic capacitor 1 of this embodiment includes a laminate 2, a first external electrode 10a, and a second external electrode 10b.
  • the first external electrode 10a and the second external electrode 10b may be collectively referred to as the external electrodes 10a, 10b.
  • the laminate 2 is substantially rectangular.
  • the laminate 2 has a first surface 7a and a second surface 7b that face each other, a first end surface 8a and a second end surface 8b that face each other, and a first side surface 9a and a second side surface 9b that face each other.
  • the first end surface 8a and the second end surface 8b may be perpendicular to the first direction (x-axis direction).
  • the first side surface 9a and the second side surface 9b may be perpendicular to the second direction (y-axis direction).
  • the first surface 7a and the second surface 7b may be perpendicular to the third direction (z-axis direction).
  • first surface 7a and the second surface 7b may be collectively referred to as the main surfaces 7a and 7b
  • the first end surface 8a and the second end surface 8b may be collectively referred to as the end surfaces 8a and 8b
  • first side surface 9a and the second side surface 9b may be collectively referred to as the side surfaces 9a and 9b.
  • the laminate 2 includes an active portion 3, a first covering portion 61, and a second covering portion 62.
  • the active portion 3 is formed by alternately stacking dielectric layers 4 and internal electrode layers 5.
  • the dielectric layers 4 and the internal electrode layers 5 are stacked in the third direction (z-axis direction).
  • the active portion 3 forms a capacitance.
  • the boundaries between the active portion 3 and each of the first covering portion 61 and the second covering portion 62 are shown by two-dot chain lines, but the actual boundaries are not clearly visible.
  • the dielectric layer 4 is made of a dielectric material.
  • the dielectric layer 4 may be made of a ceramic material mainly composed of barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), barium zirconate (BaZrO 3 ), or the like.
  • the dielectric layer 4 may have a thickness of, for example, 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the term "main component” refers to the component having the highest content in the material or member of interest.
  • the internal electrode layer 5 is made of a conductive material.
  • the internal electrode layer 5 may be made of a metal material mainly composed of metals such as Ni (nickel), Cu (copper), Sn (tin), Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or alloys thereof.
  • the internal electrode layer 5 may have a thickness of, for example, 1.5 ⁇ m or less. In this case, internal defects caused by internal stresses during firing of the laminate 2 or during application of voltage can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.
  • the internal electrode layer 5 includes a first internal electrode layer 5a and a second internal electrode layer 5b, which have opposite polarities.
  • the active section 3 is formed by stacking the first internal electrode layer 5a and the second internal electrode layer 5b alternately with the dielectric layer 4 sandwiched between them.
  • the first internal electrode layer 5a has a capacitance forming portion 5aa and a lead-out portion 5ab, as shown in FIG. 4.
  • the lead-out portion 5ab is exposed to the first end face 8a and the side faces 9a and 9b. It can also be said that the lead-out portion 5ab constitutes a part of the first end face 8a and the side faces 9a and 9b.
  • the second internal electrode layer 5b has a capacitance forming portion 5ba and a lead-out portion 5bb, as shown in FIG. 4.
  • the lead-out portion 5bb is exposed to the second end face 8b and the side faces 9a and 9b.
  • the lead-out portion 5bb constitutes a part of the second end face 8b and the side faces 9a and 9b.
  • the capacitance forming portion 5aa and the capacitance forming portion 5ba overlap each other in a plan view (i.e., when viewed from the third direction).
  • the first covering portion 61 and the second covering portion 62 are located at both ends of the active portion 3 in the third direction (z-axis direction).
  • the first covering portion 61 and the second covering portion 62 may be collectively referred to as covering portions 61, 62.
  • the first covering portion 61 includes a first dummy electrode 61a, a second dummy electrode 61b, and a first dielectric portion 61c.
  • the first dummy electrode 61a and the second dummy electrode 61b are located at both ends of the first dielectric portion 61c in the first direction (x-axis direction).
  • the first dummy electrode 61a is exposed at the first end surface 8a as shown in FIG. 3. It can be said that the first dummy electrode 61a constitutes a part of the first end surface 8a.
  • the first dummy electrode 61a may have the same shape as the lead-out portion 5ab of the first internal electrode layer 5a in a plan view, or may have a different shape from the lead-out portion 5ab.
  • the first dummy electrode 61a may be longer than the lead-out portion 5ab in the first direction (x-axis direction), or may be shorter than the lead-out portion 5ab.
  • the second dummy electrode 61b is exposed at the second end surface 8b as shown in FIG. 3.
  • the second dummy electrode 61b constitutes a part of the second end surface 8b.
  • the second dummy electrode 61b may have the same shape as the lead-out portion 5bb of the second internal electrode layer 5b in a plan view, or may have a different shape from the lead-out portion 5bb.
  • the second dummy electrode 61b may be longer than the lead-out portion 5bb in the first direction, or may be shorter than the lead-out portion 5bb.
  • the first dielectric portion 61c is made of a dielectric material and electrically insulates the first dummy electrode 61a and the second dummy electrode 61b.
  • the first dielectric portion 61c may be made of the ceramic material that constitutes the dielectric layer 4.
  • the second covering portion 62 includes a third dummy electrode 62a, a fourth dummy electrode 62b, and a second dielectric portion 62c.
  • the third dummy electrode 62a and the fourth dummy electrode 62b are located at both ends of the second dielectric portion 62c in the first direction (X-axis direction).
  • the first dielectric portion 61c and the second dielectric portion 62c may be collectively referred to as the dielectric portions 61c, 62c.
  • the third dummy electrode 62a is exposed at the first end surface 8a as shown in Figures 2 and 3. It can also be said that the third dummy electrode 62a constitutes a part of the first end surface 8a.
  • the third dummy electrode 62a may have the same shape as the lead-out portion 5ab of the first internal electrode layer 5a in a plan view, or may have a different shape from the lead-out portion 5ab.
  • the third dummy electrode 62a may be longer than the lead-out portion 5ab in the first direction (x-axis direction), or may be shorter than the lead-out portion 5ab.
  • the fourth dummy electrode 62b is exposed at the second end surface 8b as shown in Figure 3.
  • the fourth dummy electrode 62b constitutes a part of the second end surface 8b.
  • the fourth dummy electrode 62b may have the same shape as the lead-out portion 5bb of the second internal electrode layer 5b in a plan view, or may have a different shape from the lead-out portion 5bb.
  • the fourth dummy electrode 62b may be longer than the lead-out portion 5bb in the first direction, or may be shorter than the lead-out portion 5bb.
  • the second dielectric portion 62c is made of a dielectric material and electrically insulates the third dummy electrode 62a and the fourth dummy electrode 62b.
  • the second dielectric portion 62c may be made of the ceramic material that constitutes the dielectric layer 4.
  • the first dummy electrode 61a, the second dummy electrode 61b, the third dummy electrode 62a and the fourth dummy electrode 62b may be collectively referred to as dummy electrodes 61a to 62b.
  • At least one of the dummy electrodes 61a to 62b has a thickness in the third direction (z-axis direction) greater than that of one internal electrode layer 5, as shown in Figures 2 and 3.
  • the thickness of the dummy electrodes 61a to 62b may be three times or more, five times or more, or ten times or more, the thickness of one internal electrode layer 5.
  • the dummy electrodes 61a to 62b may have approximately the same dimensions. In the following, unless otherwise specified, it is assumed that all of the dummy electrodes 61a to 62b have a thickness in the third direction greater than that of the internal electrode layer 5, as shown in Figures 2 and 3.
  • the first external electrode 10a is located from the first end surface 8a to the first surface 7a, the second surface 7b, the first side surface 9a, and the second side surface 9b.
  • the first external electrode 10a is connected to a portion of the lead-out portion 5ab that is exposed on the surface of the laminate 2.
  • the first external electrode 10a may completely cover the exposed portion of the lead-out portion 5ab.
  • the first internal electrode layer 5a and the first external electrode 10a can be electrically connected well, and the active portion 3 can be protected from the external environment (e.g., moisture, etc.).
  • the first external electrode 10a is connected to a portion of the first dummy electrode 61a and the third dummy electrode 62a that is exposed on the surface of the laminate 2.
  • the first external electrode 10a may completely cover the exposed portions of the first dummy electrode 61a and the third dummy electrode 62a. In this case, the contact area between the laminate 2 and the first external electrode 10a can be increased, and the bonding strength between the laminate 2 and the first external electrode 10a can be improved.
  • the second external electrode 10b is located from the second end face 8b to the first face 7a, the second face 7b, the first side face 9a, and the second side face 9b.
  • the second external electrode 10b is connected to a portion of the lead-out portion 5bb that is exposed on the surface of the laminate 2.
  • the second external electrode 10b may completely cover the exposed portion of the lead-out portion 5bb.
  • the second internal electrode layer 5b and the second external electrode 10b can be electrically connected well, and the active portion 3 can be protected from the external environment (e.g., moisture, etc.).
  • the second external electrode 10b is connected to a portion of the second dummy electrode 61b and the fourth dummy electrode 62b that is exposed on the surface of the laminate 2.
  • the second external electrode 10b may completely cover the exposed portions of the second dummy electrode 61b and the fourth dummy electrode 62b. In this case, the contact area between the laminate 2 and the second external electrode 10b can be increased, and the bonding strength between the laminate 2 and the second external electrode 10b can be improved.
  • the external electrodes 10a and 10b may be configured to include a first layer 11 that contacts the surface of the laminate 2 and a second layer 12 that covers the first layer 11.
  • the first layer 11 is also called a base layer.
  • the second layer 12 is also called an outer layer.
  • the underlayer 11 may be composed of a metal material mainly composed of metals such as Ni, Cu, Sn, Pt, Pd, Ag, Au, etc., or alloys thereof.
  • the underlayer 11 may be formed using a thin-film formation technique such as plating, sputtering, vapor deposition, etc. In this case, the volume of the underlayer 11 can be reduced, so that the multilayer ceramic capacitor 1 can be made smaller and the effective volume contributing to the capacitance can be increased.
  • the technique for forming the underlayer 11 is not limited to a thin-film formation technique.
  • the underlayer 11 may be formed using a thick-film formation technique such as dipping, screen printing, gravure printing, etc.
  • the underlayer 11 may completely cover the exposed portions of the lead-out portions 5ab, 5bb and the dummy electrodes 61a to 62b, as shown in FIGS. 3 and 4.
  • the outer layer 12 may be composed of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, or an alloy thereof.
  • the outer layer 12 may be formed using a thin film formation technique such as electroless plating or electrolytic plating.
  • the outer layer 12 may completely cover the base layer 11 (the surface thereof), as shown in Figures 3 and 4.
  • the outer layer 12 may extend beyond the end of the base layer 11 toward the center of the laminate 2 toward the center of the laminate 2.
  • the inner end 10t of the external electrodes 10a and 10b toward the center of the laminate 2 may be composed only of the outer layer 12.
  • the multilayer ceramic capacitor 1 of this embodiment has a configuration in which dummy electrodes 61a-62b, which are thicker than the internal electrode layer 5, are exposed at the end faces 8a, 8b, and the external electrodes 10a, 10b are connected to the exposed portions of the dummy electrodes 61a-62b. This increases the bonding strength between the laminate 2 and the external electrodes 10a, 10b, and as a result, improves the reliability of the multilayer ceramic capacitor 1.
  • the coating portion (corresponding to coating portions 61 and 62) includes a dummy electrode portion in which multiple dielectric layers and multiple dummy electrode layers are alternately stacked.
  • the multilayer ceramic capacitor 1 of this embodiment has fewer interfaces of different materials in the coating portions 61 and 62, which reduces the occurrence of delamination in the coating portions 61 and 62 when the laminate 2 is (barrel) polished. This improves the reliability of the multilayer ceramic capacitor 1.
  • the area of the exposed portions of the dummy electrodes 61a to 62b at the end faces 8a and 8b can be increased without increasing the number of interfaces between different materials in the coatings 61 and 62. Therefore, the reliability of the multilayer ceramic capacitor 1 can be effectively improved.
  • the first dummy electrode 61a and the second dummy electrode 61b may be further exposed to the first surface 7a, and the third dummy electrode 62a and the fourth dummy electrode 62b may be further exposed to the second surface 7b.
  • the first dummy electrode 61a and the second dummy electrode 61b may constitute a part of the first surface 7a
  • the third dummy electrode 62a and the fourth dummy electrode 62b may constitute a part of the second surface 7b.
  • the contact area between the dummy electrodes 61a to 62b and the external electrodes 10a and 10b can be increased by exposing the dummy electrodes 61a to 62b to the main surfaces 7a and 7b.
  • the bonding strength between the laminate 2 and the external electrodes 10a, 10b can be further increased, and the reliability of the multilayer ceramic capacitor 1 can be further improved.
  • the upper surfaces of the first dummy electrode 61a and the second dummy electrode 61b may be flush with the upper surface of the first dielectric portion 61c, and the lower surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may be flush with the lower surface of the second dielectric portion 62c.
  • the thickness of the external electrodes 10a, 10b on the main surfaces 7a, 7b can be easily and precisely controlled, making it easier to manufacture a multilayer ceramic capacitor 1 with the designed dimensions.
  • the upper surfaces of the first dummy electrode 61a and the second dummy electrode 61b may protrude slightly upward from the upper surface of the first dielectric portion 61c, and the lower surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may protrude slightly downward from the lower surface of the second dielectric portion 62c.
  • the external electrodes 10a, 10b so as to wrap around the ends of the dummy electrodes 61a to 62b on the central side of the laminate 2, the contact area between the laminate 2 and the external electrodes 10a, 10b is increased, making it difficult for the laminate 2 and the external electrodes 10a, 10b to peel off. As a result, the reliability of the multilayer ceramic capacitor 1 can be improved.
  • the dummy electrodes 61a to 62b may be further exposed on the first side surface 9a and the second side surface 9b.
  • the dummy electrodes 61a to 62b may constitute a part of the first side surface 9a and the second side surface 9b.
  • the first external electrode 10a is located from the first end surface 8a to the side surfaces 9a and 9b
  • the second external electrode 10b is located from the second end surface 8b to the side surfaces 9a and 9b
  • the dummy electrodes 61a to 62b are exposed on the side surfaces 9a and 9b, so that the dummy electrodes 61a to 62b
  • the bonding strength between the laminate 2 and the external electrodes 10a, 10b can be further increased, and the reliability of the multilayer ceramic capacitor 1 can be further improved.
  • the side surfaces of the first dummy electrode 61a and the second dummy electrode 61b may be flush with the side surfaces of the first dielectric portion 61c, and the side surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may be flush with the side surfaces of the second dielectric portion 62c.
  • the thickness of the external electrodes 10a, 10b on the side surfaces 9a, 9b can be easily and precisely controlled, making it easier to manufacture a multilayer ceramic capacitor 1 with the dimensions as designed.
  • the side surfaces of the first dummy electrode 61a and the second dummy electrode 61b may protrude slightly in the second direction (y-axis direction) from the side surface of the first dielectric portion 61c, and the side surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may protrude slightly in the second direction from the side surface of the second dielectric portion 62c.
  • the side surface of the first dielectric portion 61c may be recessed from the side surfaces of the first dummy electrode 61a and the second dummy electrode 61b, and the side surface of the second dielectric portion 62c may be recessed from the side surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b.
  • the contact area between the laminate 2 and the external electrodes 10a, 10b is increased, and the laminate 2 and the external electrodes 10a, 10b are less likely to peel off from each other. As a result, the reliability of the multilayer ceramic capacitor 1 can be improved.
  • the multilayer ceramic capacitor 1 of this embodiment may be configured such that at least one of the dummy electrodes 61a to 62b is thicker than the internal electrode layer 5. As shown in FIG. 5, the multilayer ceramic capacitor 1 may be configured such that the first dummy electrode 61a is thicker than the internal electrode layer 5, and the second dummy electrode 61b, the third dummy electrode 62a, and the fourth dummy electrode 62b are either the same thickness as the internal electrode layer 5 or thinner than the internal electrode layer 5.
  • the multilayer ceramic capacitor 1 can reduce the number of interfaces between different materials in the coating portions 61 and 62, thereby reducing the occurrence of delamination in the coating portions 61 and 62 when the laminate 2 is barrel polished. This can improve the reliability of the multilayer ceramic capacitor 1.
  • the laminate 2 may have an auxiliary electrode portion 61ba located inside (below) the second dummy electrode 61b in the third direction (z-axis direction) and formed by alternately stacking dielectric layers 65 and electrode layers 66.
  • the electrode layer 66 may be exposed on the second end surface 8b and the side surfaces 9a, 9b. In this case, the bonding strength between the laminate 2 and the second external electrode 10b can be increased.
  • the electrode layer 66 may have the same shape as the second dummy electrode 61b in a plan view, or may have a different shape from the second dummy electrode 61b.
  • the laminate 2 may have an auxiliary electrode portion 62aa located inside (above) the third dummy electrode 62a in the third direction (z-axis direction), and an auxiliary electrode portion 62ba located inside (above) the fourth dummy electrode 62b in the third direction.
  • the auxiliary electrode portions 62aa, 62ba may be configured by alternately stacking dielectric layers 65 and electrode layers 66, similar to the auxiliary electrode portion 61ba.
  • the electrode layer 66 of the auxiliary electrode portion 62aa may be exposed to the first end face 8a and the side faces 9a, 9b, and the electrode layer 66 of the auxiliary electrode portion 62ba may be exposed to the second end face 8b and the side faces 9a, 9b.
  • the electrode layer 66 of the auxiliary electrode portion 62aa may have the same shape as the third dummy electrode 62a in a plan view, or may have a different shape from the third dummy electrode 62a.
  • the electrode layer 66 of the auxiliary electrode portion 62ba may have the same shape as the fourth dummy electrode 62b in a plan view, or may have a different shape from the fourth dummy electrode 62b.
  • the multilayer ceramic capacitor 1 may be configured such that two of the dummy electrodes 61a-62b are thicker than the internal electrode layer 5, or may be configured such that three of the dummy electrodes 61a-62b are thicker than the internal electrode layer 5.
  • Figures 6 to 8 are cross-sectional views showing another example of the multilayer ceramic capacitor of this embodiment.
  • the cross-sectional views shown in Figures 6 to 8 correspond to the cross-sectional view shown in Figure 3.
  • the dummy electrodes 61a to 62b may be formed by stacking a plurality of dummy electrode layers 63 as shown in FIG. 6.
  • the plurality of dummy electrode layers 63 may be stacked in the third direction (z-axis direction).
  • the thin dummy electrode layers 63 by stacking the thin dummy electrode layers 63, the thick dummy electrodes 61a to 62b can be formed.
  • the thin thickness of the dummy electrode layers 63 allows the dimensions of the dummy electrode layers 63 to be controlled with precision. Therefore, compared to forming a single sheet of dummy electrodes 61a to 62b, the dimensions of the dummy electrodes 61a to 62b can be controlled with precision.
  • the dummy electrodes 61a to 62b can be formed with the designed dimensions, and the reliability of the multilayer ceramic capacitor 1 can be improved.
  • the boundaries between the dummy electrode layers 63 are indicated by two-dot chain lines, but the actual boundaries are not clearly visible. This is the same for FIGS. 7 and 8.
  • the thickness of the dummy electrode layer 63 may be approximately the same as the thickness of the internal electrode layer 5.
  • the active part 3 of the unsintered laminate 2 is produced by a printing method such as screen printing or gravure printing using ceramic slurry and conductive paste. Therefore, when the thickness of the dummy electrode layer 63 is approximately the same as the thickness of the internal electrode layer 5, the dummy electrode layer 63 can be printed using a printing method similar to the printing method used to print the internal electrode layer 5. As a result, it becomes possible to efficiently form dummy electrodes 61a to 62b of the designed dimensions.
  • the first dielectric portion 61c and the second dielectric portion 62c may be configured with a plurality of dielectric layers 64 stacked.
  • the thickness of the dielectric layer 64 may be approximately the same as the thickness of the dummy electrode layer 63.
  • the dielectric layer 64 can be printed using a printing method similar to the printing method used to print the dummy electrode layer 63. As a result, it is possible to efficiently form the covering portions 61, 62 with the designed dimensions. Note that in FIG. 6, the boundaries between the dielectric layers 64 are shown by two-dot chain lines, but the actual boundaries are not clearly visible. The same applies to FIGS. 7 and 8.
  • the dummy electrode layer 63 may include a common material 63a made of a dielectric material. In this case, the bonding strength between the dummy electrode layers 63 can be increased, and therefore the occurrence of delamination in the dummy electrodes 61a to 62b can be suppressed.
  • the dummy electrode layer 63 may include a common material made of a ceramic material constituting the dielectric layer 4 and the dielectric layer 64. In this case, the bonding strength between the dummy electrode layers 63 can be increased while the bonding strength between the dummy electrodes 61a to 62b and the active portion 3 can be increased.
  • the bonding strength between the first dummy electrode 61a and the second dummy electrode 61b and the first dielectric portion 61c can be increased, and the bonding strength between the third dummy electrode 62a and the fourth dummy electrode 62b and the first dielectric portion 61c can be increased.
  • the occurrence of delamination in the laminate 2 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.
  • the interface 61d between at least one of the first dummy electrode 61a and the second dummy electrode 61b and the first dielectric portion 61c may have an uneven structure.
  • the multilayer ceramic capacitor 1 is used, for example, by solder mounting (reflow solder mounting) on an external substrate.
  • solder mounting reflow solder mounting
  • cracks are likely to occur in the region (hereinafter also referred to as the "opposing region") 2f near the inner end 10t of the external electrodes 10a and 10b on the laminate 2 (first surface 7a) due to the shrinkage of the external electrodes 10a and 10b during cooling after heating.
  • the interface 61d of the first covering portion 61 By having the interface 61d of the first covering portion 61 have an uneven structure, even if a crack occurs in the opposing region 2f of the first covering portion 61, the crack can be prevented from extending to the active portion 3. As a result, the moisture resistance of the multilayer ceramic capacitor 1 can be improved, and the reliability can be improved.
  • the uneven structure of the interface 61d may be formed by regularly or irregularly changing the positions of the ends of the plurality of dummy electrode layers 63 on the first dielectric portion 61c side in the first direction (x-axis direction) as shown in FIG. 7.
  • the uneven structure of the interface 61d may be formed, for example, by providing unevenness at the interface between the electrode pattern that becomes the first dummy electrode 61a and the second dummy electrode 61b and the dielectric pattern that becomes the first dielectric portion 61c in the manufacturing process of the mother laminate (see FIGS. 9 and 12).
  • the interface 62d between at least one of the third dummy electrode 62a and the fourth dummy electrode 62b and the second dielectric portion 62c may have an uneven structure.
  • the effect of the uneven structure of the interface 62d is the same as the effect of the uneven structure of the interface 61d, and the method of making the interface 62d an uneven structure is the same as the method of making the interface 61d an uneven structure, so detailed explanations are omitted.
  • the bottom surfaces of the first dummy electrode 61a and the second dummy electrode 61b may be in contact with the top surface of the active portion 3.
  • the laminate 2 may be configured such that the interface 61e between the active portion 3 and each of the first dummy electrode 61a and the second dummy electrode 61b has an uneven structure. In this case, the active portion 3 is less likely to peel off from the first dummy electrode 61a and the second dummy electrode 61b, and as a result, the reliability of the laminated ceramic capacitor 1 can be improved.
  • the lower surfaces of the first dummy electrode 61a and the second dummy electrode 61b may not be in contact with the upper surface of the active portion 3.
  • the first covering portion 61 may include an intermediate layer (not shown) located between the active portion 3 and the first dummy electrode 61a, and between the active portion 3 and the second dummy electrode 61b.
  • the intermediate layer may be composed of the dielectric material that constitutes the first dielectric portion 61c.
  • the first covering portion 61 may be configured such that the interfaces between the intermediate layer and each of the first dummy electrode 61a and the second dummy electrode 61b have an uneven structure. In this case, peeling in the first covering portion 61 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.
  • the upper surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may be in contact with the lower surface of the active portion 3.
  • the laminate 2 may be configured such that the interface 62e between the active portion 3 and each of the third dummy electrode 62a and the fourth dummy electrode 62b has an uneven structure. In this case, the active portion 3 is less likely to peel off from the third dummy electrode 62a and the fourth dummy electrode 62b, and as a result, the reliability of the laminated ceramic capacitor 1 can be improved.
  • the upper surfaces of the third dummy electrode 62a and the fourth dummy electrode 62b may not be in contact with the lower surface of the active portion 3.
  • the second covering portion 62 may include a second intermediate layer (not shown) located between the active portion 3 and the third dummy electrode 62a, and between the active portion 3 and the fourth dummy electrode 62b.
  • the intermediate layer may be composed of a dielectric material that constitutes the second dielectric portion 62c.
  • the second covering portion 62 may be configured such that the interfaces between the third dummy electrode 62a and the fourth dummy electrode 62b, respectively, and the second intermediate layer have an uneven structure. In this case, peeling in the second covering portion 62 can be suppressed, and the reliability of the multilayer ceramic capacitor 1 can be improved.
  • Figure 9 is a perspective view illustrating an example of a process for producing a mother laminate
  • Figure 10 is a perspective view showing an example of a mother laminate
  • Figure 11 is a perspective view showing an example of a laminate obtained by cutting the mother laminate.
  • a raw material powder mainly composed of a dielectric material such as BaTiO 3 , CaTiO 3 , SrTiO 3 , BaZrO 3 or a mixture thereof is prepared.
  • an organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry.
  • the organic vehicle used to prepare the ceramic slurry may be, for example, a resin such as a butyral resin dissolved in a solvent mixed with ethyl alcohol and toluene.
  • the prepared ceramic slurry is used to form a ceramic green sheet (hereinafter also referred to as a "green sheet") 13 to be the dielectric layer 4 by a sheet forming method such as a doctor blade method or a die coater method.
  • the average thickness of the green sheet 13 may be, for example, about 0.5 to 10 ⁇ m.
  • the above-mentioned ceramic slurry may be used for the dielectric parts 61c and 62c.
  • a conductive paste is prepared by mixing an organic vehicle with a powder mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, or an alloy of these metals as the material for the internal electrode layer 5.
  • the organic vehicle used to prepare the conductive paste may be, for example, a resin such as ethyl cellulose dissolved in a solvent mixed with a dihydroterpineol-based solvent and butyl cellosolve.
  • the dispersant may be, for example, oleic acid, polyethylene glycol, or the like.
  • the above-mentioned conductive paste may be used for the dummy electrodes 61a to 62b.
  • a conductive paste is used to print electrode patterns 14, which will become the internal electrode layers 5, on the main surface of the green sheet 13 to form a pattern sheet 15 (see FIG. 9).
  • the electrode patterns 14 can be printed using a printing method such as screen printing or gravure printing.
  • a temporary laminate which is a precursor of the base laminate, is prepared.
  • the first cover sheet 17 is composed of an electrode pattern 18, which will become the dummy electrodes 61a to 62b, and a dielectric pattern 19, which will become the dielectric parts 61c and 62c.
  • the first cover sheet 17 may be formed by printing multiple times, or may be formed by printing once.
  • Figure 9 shows the case where the first cover sheet 17 is formed by printing multiple times, that is, the dummy electrodes 61a to 62b are formed by stacking multiple dummy electrode layers 63, and the dielectric parts 61c and 62c are formed by stacking multiple dielectric layers 64.
  • the electrode pattern 14 and the electrode pattern 18 are shown hatched.
  • a predetermined number of pattern sheets 15 are laminated on the first cover sheet 17, and a second cover sheet 20 is formed thereon to produce a temporary laminate.
  • the second cover sheet 20 can be formed in the same manner as the first cover sheet 17.
  • the temporary laminate is pressed in the stacking direction to obtain a mother laminate 21 as shown in FIG. 10.
  • the exposed portions of the electrode pattern 14 and the electrode pattern 18 on the surface of the mother laminate 21 are shown hatched.
  • the temporary laminate can be pressed using, for example, a hydrostatic press.
  • the mother laminate 21 is cut along the virtual parting lines 22 to produce a plurality of unsintered laminates 2 as shown in FIG. 11.
  • the mother laminate 21 can be cut using, for example, a press cutter, a dicing saw, or the like. Since the unsintered laminate 2 has the same structure as the laminate 2 after firing, hereinafter, the terms and reference characters such as the internal electrode layer 5, main surfaces 7a, 7b, end faces 8a, 8b, and side surfaces 9a, 9b are also used for the unsintered laminate 2.
  • the parts of the internal electrode layer 5 and the dummy electrodes 61a to 62b that are exposed on the surface of the laminate 2 are shown with hatching.
  • the unfired laminate 2 is subjected to a degreasing process in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere.
  • the degreasing process may be performed under atmospheric pressure or under reduced pressure.
  • the degreased laminate 2 is fired in a reducing atmosphere.
  • the atmospheric gas may be, for example, a mixed gas of hydrogen (H2) and nitrogen (N2).
  • the firing temperature may be, for example, about 1100 to 1300°C.
  • the fired laminate 2 may be subjected to a re-oxidation treatment in an oxidizing atmosphere.
  • the fired laminate 2 is subjected to barrel polishing to fully expose the internal electrode layers 5 on the end faces 8a, 8b and side faces 9a, 9b, and to remove burrs from the surface of the laminate 2, thereby obtaining the laminate 2 as shown in FIG. 2.
  • the laminate 2 thus obtained is then formed with external electrodes 10a, 10b, thereby producing the multilayer ceramic capacitor 1.
  • the external electrodes 10a, 10b may be formed by applying a conductive paste to the unfired laminate 2 to become the external electrodes 10a, 10b, and then simultaneously firing the laminate 2 and the external electrodes 10a, 10b.
  • FIG 12 is a perspective view explaining another example of the manufacturing process of the mother laminate
  • Figure 13 is a perspective view showing another example of the mother laminate
  • Figure 14 is a perspective view showing another example of the laminate obtained by cutting the mother laminate.
  • the electrode pattern 14 and the electrode pattern 18 are shown hatched.
  • Figure 13 the parts of the electrode pattern 14 and the electrode pattern 18 exposed on the surface of the mother laminate are shown hatched.
  • the parts of the internal electrode layer 5 and the dummy electrodes 61a to 62b exposed on the surface of the laminate are shown hatched.
  • one green sheet 13 is placed on a support sheet 16, and a first cover sheet 17 is formed thereon. Furthermore, a predetermined number of pattern sheets 15 are stacked on the first cover sheet 17, a second cover sheet 20 is formed thereon, and one green sheet 13 is placed thereon to produce a temporary laminate.
  • the second cover sheet 20 can be formed in the same manner as the first cover sheet 17.
  • the temporary laminate is pressed in the stacking direction to obtain a mother laminate 23 as shown in FIG. 13.
  • the mother laminate 23 has the same configuration as the mother laminate 21 described above, except that the green sheets 13 are located in the uppermost and lowermost layers in the stacking direction.
  • the laminate 2A has the same structure as the laminate 2 described above, except that a part of the green sheet 13 (reference numeral 13' in FIG. 14) is located in the uppermost and lowermost layers in the stacking direction. It can also be said that the laminate 2A is composed of the laminate 2 and a part of the green sheet 13.
  • the unfired laminate 2A is subjected to a degreasing treatment.
  • the degreasing treatment may be the same as the degreasing treatment in the first manufacturing method.
  • the laminate 2A that has been subjected to the degreasing treatment is fired.
  • the firing atmosphere and firing temperature may be the same as the firing atmosphere and firing temperature in the first manufacturing method.
  • the fired laminate 2A is subjected to barrel polishing to remove the dielectric layer formed by firing a portion of the green sheet 13, fully exposing the internal electrode layer 5 and dummy electrodes 61a to 62b on the surface of the laminate 2, and by removing burrs on the surface of the laminate 2, the laminate 2 shown in FIG. 2 is obtained.
  • the multilayer ceramic capacitor 1 can be manufactured.
  • the electrode patterns 18 that become the dummy electrodes 61a to 62b contact the support sheet 16 via the green sheet 13, and do not contact the support sheet 16 directly.
  • electrode eating the laminate 2A obtained by cutting the base laminate 23 is peeled off from the support sheet 16.
  • poor formation of the dummy electrodes 61a to 62b due to electrode eating can be prevented, and ultimately the reliability of the multilayer ceramic capacitor 1 can be improved.
  • the unsintered laminate 2A will have a substantially vertically symmetrical configuration. Therefore, when the sintered laminate 2A is barrel polished, the upper and lower parts of the laminate 2A are uniformly polished, and the laminate 2A after barrel polishing (i.e., the laminate 2 shown in FIG. 2) will have a substantially vertically symmetrical configuration. As a result, it is possible to prevent bias in the bonding strength between the laminate 2 and the external electrodes 10a, 10b, and ultimately improve the reliability of the multilayer ceramic capacitor 1.
  • Figures 15, 16, 17, 18A, and 18B relate to multilayer ceramic capacitors of other embodiments.
  • Figure 15 is a perspective view showing a multilayer ceramic capacitor of another embodiment
  • Figure 16 is a perspective view showing a laminate of the multilayer ceramic capacitor of Figure 15
  • Figure 17 is a cross-sectional view taken along the cutting line XVII-XVII of Figure
  • Figure 18A is a cross-sectional view taken along the cutting line XVIIIA-XVIIIA of Figure 17
  • Figure 18B is a cross-sectional view taken along the cutting line XVIIIB-XVIIIB of Figure 17.
  • Figure 18A shows an end face cut along the cutting line XVIIIA-XVIIIA of Figure 17.
  • the multilayer ceramic capacitor 1A of this embodiment differs from the multilayer ceramic capacitor 1 in the configuration of the internal electrode layer 5 and the external electrodes 10a, 10b, but otherwise has the same configuration, so detailed description of the similar configuration is omitted.
  • the lead-out portion 5ab of the first internal electrode layer 5a is exposed to the first end face 8a and the side faces 9a and 9b
  • the lead-out portion 5bb of the second internal electrode layer 5b is exposed to the second end face 8b and the side faces 9a and 9b
  • the first dummy electrode 61a is exposed to the first face 7a, the first end face 8a, and the side faces 9a and 9b
  • the second dummy electrode 61b is exposed to the first face 7a, the second end face 8b, and the side faces 9a and 9b.
  • the third dummy electrode 62a is exposed to the second face 7b, the first end face 8a, and the side faces 9a and 9b
  • the fourth dummy electrode 62b is exposed to the second face 7b, the second end face 8b, and the side faces 9a and 9b.
  • the first external electrode 10a is located from the first end face 8a to the main faces 7a, 7b and side faces 9a, 9b
  • the second external electrode 10b is located from the second end face 8b to the main faces 7a, 7b and side faces 9a, 9b.
  • the first external electrode 10a covers the portion of the first dummy electrode 61a exposed to the first face 7a and also covers the portion of the third dummy electrode 62a exposed to the second face 7b.
  • the first external electrode 10a covers the first dummy electrode 61a, the third dummy electrode 62a, and the portions of the lead-out portion 5ab of the first internal electrode layer 5a exposed to the first end face 8a and side faces 9a, 9b.
  • the second external electrode 10b covers the portion of the second dummy electrode 61b exposed on the first surface 7a, and also covers the portion of the fourth dummy electrode 62b exposed on the second surface 7b.
  • the second external electrode 10b covers the second dummy electrode 61b, the fourth dummy electrode 62b, and the portions of the second internal electrode layer 5b exposed on the second end surface 8b and the side surfaces 9a and 9b of the lead-out portion 5bb.
  • the portion of lead-out portion 5ab exposed to the side surfaces 9a, 9b is shorter in length in the first direction (x-axis direction) than the portions of lead-out portion 5ab exposed to the side surfaces 9a, 9b of the first dummy electrode 61a and the third dummy electrode 62a.
  • the end portion of lead-out portion 5ab exposed to the side surfaces 9a, 9b on the second end surface 8b side is located closer to the first end surface 8a than the end portion of lead-out portion 5ab exposed to the side surfaces 9a, 9b of the first dummy electrode 61a and the third dummy electrode 62a on the second end surface 8b side.
  • the portion of lead-out portion 5bb exposed to the side surfaces 9a, 9b is shorter in length in the first direction (x-axis direction) than the portions of lead-out portion 5ab exposed to the side surfaces 9a, 9b of the second dummy electrode 61b and the fourth dummy electrode 62b.
  • the end of the portion of the lead-out portion 5bb exposed on the side surfaces 9a, 9b on the first end surface 8a side is located closer to the second end surface 8b than the end of the portion of the second dummy electrode 61b and the fourth dummy electrode 62b exposed on the side surfaces 9a, 9b on the first end surface 8a side.
  • the external electrodes 10a, 10b have a U-shape when viewed from the second direction (y-axis direction).
  • the multilayer ceramic capacitor 1A has dummy electrodes 61a-62b that are thicker than the internal electrode layers 5, so the number of interfaces between different materials in the coatings 61, 62 can be reduced compared to multilayer ceramic capacitors of the prior art. As a result, the occurrence of delamination in the coatings 61, 62 when the laminate 2 is barrel polished can be reduced, improving the reliability of the multilayer ceramic capacitor 1A.
  • the portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b may be composed of only the outer layer 12.
  • the portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b can be made thin, and as a result, the multilayer ceramic capacitor 1A can be made low-profile.
  • the multilayer ceramic capacitor 1A has largely exposed side surfaces 9a, 9b that have a lower solder wettability than the surfaces of the external electrodes 10a, 10b, so solder is less likely to adhere to the side surfaces 9a, 9b when solder-mounted to an external board. As a result, even if the multilayer ceramic capacitor 1A is made low-profile, the risk of short-circuiting the first external electrode 10a and the second external electrode 10b due to solder adhering to the side surfaces 9a, 9b can be reduced.
  • the multilayer ceramic capacitor 1A may be configured such that all of the dummy electrodes 61a to 62b are thicker than the internal electrode layer 5, as shown in Figures 16 and 17, or may be configured such that at least one of the dummy electrodes 61a to 62b is thicker than the internal electrode layer 5, as in the multilayer ceramic capacitor 1 shown in Figure 5.
  • Figures 19, 20, 21, 22A, and 22B relate to a multilayer ceramic capacitor according to yet another embodiment.
  • Figure 19 is a perspective view showing a multilayer ceramic capacitor according to yet another embodiment
  • Figure 20 is a perspective view showing a laminate of the multilayer ceramic capacitor of Figure 19
  • Figure 21 is a cross-sectional view taken along the cutting line XIX-XIX in Figure 19
  • Figure 22A is a cross-sectional view taken along the cutting line XXIIA-XXIIA in Figure 21
  • Figure 22B is a cross-sectional view taken along the cutting line XXIIB-XXIIB in Figure 21.
  • Figure 22A shows an end face cut along the cutting line XXIIA-XXIIA in Figure 21.
  • the multilayer ceramic capacitor 1B of this embodiment differs from the multilayer ceramic capacitor 1 in the configuration of the internal electrode layer 5, dummy electrodes 61a-62b, and external electrodes 10a, 10b, but the rest of the configuration is similar, so detailed description of the similar configuration is omitted.
  • the lead-out portion 5ab of the first internal electrode layer 5a is exposed only to the first end face 8a, and is not exposed to the side faces 9a and 9b.
  • the lead-out portion 5bb of the second internal electrode layer 5b is exposed only to the second end face 8b, and is not exposed to the side faces 9a and 9b.
  • the first dummy electrode 61a is exposed to the first face 7a, the first end face 8a, and the side faces 9a and 9b
  • the second dummy electrode 61b is exposed to the first face 7a, the second end face 8b, and the side faces 9a and 9b.
  • the third dummy electrode 62a is exposed to the second face 7b, the first end face 8a, and the side faces 9a and 9b
  • the fourth dummy electrode 62b is exposed to the second face 7b, the second end face 8b, and the side faces 9a and 9b.
  • the first external electrode 10a is located from the first end face 8a to the main faces 7a, 7b and side faces 9a, 9b
  • the second external electrode 10b is located from the second end face 8b to the main faces 7a, 7b and side faces 9a, 9b.
  • the first external electrode 10a covers the portion of the first dummy electrode 61a exposed to the first face 7a and side faces 9a, 9b, and also covers the portion of the third dummy electrode 62a exposed to the second face 7b and side faces 9a, 9b.
  • the second external electrode 10b covers the portion of the second dummy electrode 61b exposed to the first face 7a and side faces 9a, 9b, and also covers the portion of the fourth dummy electrode 62b exposed to the second face 7b and side faces 9a, 9b. As shown in FIG. 19, the external electrodes 10a and 10b have a U-shape when viewed from the second direction (y-axis direction).
  • the multilayer ceramic capacitor 1B has dummy electrodes 61a-62b that are thicker than the internal electrode layers 5, so the number of interfaces between different materials in the coatings 61, 62 can be reduced compared to multilayer ceramic capacitors of the prior art. As a result, the occurrence of delamination in the coatings 61, 62 when the laminate 2 is barrel polished can be reduced, improving the reliability of the multilayer ceramic capacitor 1B.
  • the portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b may be composed of only the outer layer 12.
  • the portions of the external electrodes 10a, 10b located on the principal surfaces 7a, 7b can be made thin, and as a result, the multilayer ceramic capacitor 1B can be made low-profile.
  • the multilayer ceramic capacitor 1B has largely exposed side surfaces 9a, 9b that have a lower solder wettability than the surfaces of the external electrodes 10a, 10b, so solder is less likely to adhere to the side surfaces 9a, 9b when solder-mounted to an external board. As a result, even if the multilayer ceramic capacitor 1B is made low-profile, the risk of short-circuiting the first external electrode 10a and the second external electrode 10b due to solder adhering to the side surfaces 9a, 9b can be reduced.
  • the multilayer ceramic capacitor 1B may be configured such that all of the dummy electrodes 61a to 62b are thicker than the internal electrode layer 5, as shown in Figures 20 and 21, or may be configured such that at least one of the dummy electrodes 61a to 62b is thicker than the internal electrode layer 5, as in the multilayer ceramic capacitor 1 shown in Figure 5.
  • FIG. 23 is a perspective view showing a multilayer ceramic capacitor according to yet another embodiment
  • FIG. 24 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 23
  • FIG. 25 is a cross-sectional view taken along the cutting line XXV-XXV of FIG. 23
  • FIG. 26A is a cross-sectional view taken along the cutting line XXVIA-XXVIA of FIG. 25
  • FIG. 26B is a cross-sectional view taken along the cutting line XXVIB-XXVIB of FIG. 25, FIG.
  • 26C is a cross-sectional view taken along the cutting line XXVIC-XXVIC of FIG. 25
  • FIG. 26D is a cross-sectional view taken along the cutting line XXVID-XXVID of FIG. 25.
  • FIG. 24 the portions of the internal electrode layer and the dummy electrode exposed on the surface of the laminate are shown hatched.
  • the multilayer ceramic capacitor 1C of this embodiment includes a laminate 25, a first external electrode 26a, a second external electrode 26b, a third external electrode 26c, and a fourth external electrode 26d.
  • the first external electrode 26a, the second external electrode 26b, the third external electrode 26c, and the fourth external electrode 26d may be collectively referred to as external electrodes 26a to 26d.
  • the laminate 25 is substantially rectangular.
  • the laminate 25 has a first surface 27a and a second surface 27b that face each other, a first end surface 28a and a second end surface 28b that face each other, and a first side surface 29a and a second side surface 29b that face each other.
  • the first end surface 28a and the second end surface 28b may be perpendicular to the first direction (x-axis direction).
  • the first side surface 29a and the second side surface 29b may be perpendicular to the second direction (y-axis direction).
  • the first surface 27a and the second surface 27b may be perpendicular to the third direction (z-axis direction).
  • the first surface 27a and the second surface 27b may be substantially square in plan view.
  • the laminate 25 includes an active section 30, a first covering section 33, and a second covering section 34.
  • the active section 30 is formed by alternately stacking dielectric layers 31 and internal electrode layers 32.
  • the dielectric layers 31 and the internal electrode layers 32 are stacked in the third direction (z-axis direction).
  • the active section 30 forms a capacitance.
  • the boundaries between the active section 30 and the first covering section and the second covering section are shown by two-dot chain lines, but the actual boundaries are not clearly visible.
  • the first covering section 33 and the second covering section 34 may be collectively referred to as covering sections 33, 34.
  • the dielectric layer 31 may be made of a ceramic material mainly composed of, for example, BaTiO3 , CaTiO3 , SrTiO3 , BaZrO3, etc.
  • the internal electrode layer 32 may be made of a metal material mainly composed of, for example, a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au, etc., or an alloy thereof.
  • the internal electrode layer 32 includes a first internal electrode layer 32a and a second internal electrode layer 32b that have mutually different polarities.
  • the active section 30 is configured by alternately stacking the first internal electrode layer 32a and the second internal electrode layer 32b with the dielectric layer 31 in between.
  • Figures 24 and 25 show an example in which the active section 30 has two internal electrode layers 32, the active section 30 may have more than two internal electrode layers 32.
  • the first internal electrode layer 32a has a capacitance forming portion 32aa, a first lead portion 32ab, and a second lead portion 32ac.
  • the first lead portion 32ab is exposed at the first end face 28a and the second side face 29b.
  • the second lead portion 32ac is exposed at the second end face 28b and the first side face 29a.
  • the first lead portion 32ab and the second lead portion 32ac are respectively located at two corners located diagonally opposite each other of the laminate 25 in a plan view.
  • the second internal electrode layer 32b has a capacitance forming portion 32ba, a third lead portion 32bb, and a fourth lead portion 32bc.
  • the third lead portion 32bb is exposed at the first end face 28a and the first side face 29a.
  • the fourth lead portion 32bc is exposed at the second end face 28b and the second side face 29b.
  • the third lead portion 32bb and the fourth lead portion 32bc are respectively located at two corners located diagonally opposite each other of the laminate 25 in a plan view.
  • Capacitance forming portion 32aa and capacitance forming portion 32ba overlap each other in a planar view.
  • First pull-out portion 32ab does not overlap third pull-out portion 32bb and fourth pull-out portion 32bc in a planar view.
  • Second pull-out portion 32ac does not overlap third pull-out portion 32bb and fourth pull-out portion 32bc in a planar view.
  • the first covering portion 33 and the second covering portion 34 are located at both ends of the active portion 30 in the third direction (z-axis direction).
  • the first covering portion 33 includes four dummy electrodes 33a, 33b, 33c, and 33d, and a first dielectric portion 33e.
  • the four dummy electrodes 33a, 33b, 33c, and 33d are located at the four corners of the laminate 25, respectively, in a planar view.
  • the dummy electrodes 33a, 33b, 33c, and 33d are exposed to the first surface 27a.
  • the dummy electrode 33a is further exposed to the first end surface 28a and the second side surface 29b.
  • the dummy electrode 33b is further exposed to the second end surface 28b and the first side surface 29a.
  • the dummy electrode 33c is further exposed to the first end surface 28a and the first side surface 29a.
  • the dummy electrode 33d is further exposed to the second end surface 28b and the second side surface 29b.
  • the dummy electrodes 33a, 33b, 33c, and 33d may be, for example, rectangular parallelepiped, cubic, triangular prism, or quadrant cylinder.
  • the dummy electrodes 33a, 33b, 33c, and 33d may be made of the metal material that constitutes the internal electrode layer 32.
  • the first dielectric portion 33e is made of a dielectric material and electrically insulates the dummy electrodes 33a, 33b, 33c, and 33d from each other.
  • the first dielectric portion 33e may be made of the ceramic material that constitutes the dielectric layer 31.
  • the second covering portion 34 includes four dummy electrodes 34a, 34b, 34c, and 34d, and a second dielectric portion 34e.
  • the four dummy electrodes 34a, 34b, 34c, and 34d are located at the four corners of the laminate 25, respectively, in a planar view.
  • the dummy electrodes 34a, 34b, 34c, and 34d are exposed to the second surface 27b.
  • the dummy electrode 34a is further exposed to the first end surface 28a and the first side surface 29a.
  • the dummy electrode 34b is further exposed to the second end surface 28b and the second side surface 29b.
  • the dummy electrode 34c is further exposed to the first end surface 28a and the second side surface 29b.
  • the dummy electrode 34d is further exposed to the second end surface 28b and the first side surface 29a.
  • the dummy electrodes 34a, 34b, 34c, and 34d may be, for example, rectangular parallelepiped, cubic, triangular prism, or quadrant cylinder.
  • the dummy electrodes 34a, 34b, 34c, and 34d may be made of the metal material that constitutes the internal electrode layer 32.
  • the second dielectric portion 34e is made of a dielectric material and electrically insulates the dummy electrodes 34a, 34b, 34c, and 34d from one another.
  • the second dielectric portion 34e may be made of the ceramic material that constitutes the dielectric layer 31.
  • the dummy electrodes 33a, 33b, 33c, and 33d and the dummy electrodes 34a, 34b, 34c, and 34d may be collectively referred to as dummy electrodes 33a to 34d.
  • the first external electrode 26a is located on the first surface 27a, the first end surface 28a, the second side surface 29b, and the second surface 27b.
  • the first external electrode 26a is connected to the portion of the first lead-out portion 32ab exposed on the surface of the laminate 25, and the portions of the dummy electrode 33a and the dummy electrode 34c exposed on the surface of the laminate 25.
  • the first external electrode 26a may completely cover the portion of the first lead-out portion 32ab exposed on the surface of the laminate 25, and the portions of the dummy electrode 33a and the dummy electrode 34c exposed on the surface of the laminate 25.
  • the second external electrode 26b is located on the first surface 27a, the second end surface 28b, the first side surface 29a, and the second surface 27b.
  • the second external electrode 26b is connected to the portion of the second lead-out portion 32ac exposed on the surface of the laminate 25, and the portions of the dummy electrodes 33b and 34d exposed on the surface of the laminate 25.
  • the second external electrode 26b may completely cover the portion of the second lead-out portion 32ac exposed on the surface of the laminate 25, and the portions of the dummy electrodes 33b and 34d exposed on the surface of the laminate 25.
  • the third external electrode 26c is located on the first surface 27a, the first end surface 28a, the first side surface 29a, and the second surface 27b.
  • the third external electrode 26c is connected to the portion of the third lead-out portion 32bb exposed on the surface of the laminate 25, and the portions of the dummy electrode 33c and the dummy electrode 34a exposed on the surface of the laminate 25.
  • the third external electrode 26c may completely cover the portion of the third lead-out portion 32bb exposed on the surface of the laminate 25, and the portions of the dummy electrode 33c and the dummy electrode 34a exposed on the surface of the laminate 25.
  • the fourth external electrode 26d is located on the first surface 27a, the second end surface 28b, the second side surface 29b, and the second surface 27b.
  • the fourth external electrode 26d is connected to the portion of the fourth lead-out portion 32bc exposed on the surface of the laminate 25, and the portions of the dummy electrodes 33d and 34b exposed on the surface of the laminate 25.
  • the fourth external electrode 26d may completely cover the portion of the fourth lead-out portion 32bc exposed on the surface of the laminate 25, and the portions of the dummy electrodes 33d and 34b exposed on the surface of the laminate 25.
  • the external electrodes 26a to 26d may be composed of a metal material mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, or Au, or an alloy of these metals.
  • the external electrodes 26a to 26d may be formed using a thick-film formation technique such as a dipping method, a screen printing method, or a gravure printing method.
  • the external electrodes 26a to 26d may be composed of a base layer in contact with the surface of the laminate 25 and an outer layer covering the base layer, similar to the external electrodes 10a and 10b shown in Figures 3 and 4.
  • the method of manufacturing the multilayer ceramic capacitor 1C is the same as the method of manufacturing the multilayer ceramic capacitor 1.
  • a base laminate is produced, and then the base laminate is cut to produce a plurality of unfired laminates 25.
  • the unfired laminates 25 are degreased, and the degreased laminates 25 are fired.
  • the fired laminates 2 are barrel polished to obtain the laminate 25 shown in FIG. 24.
  • External electrodes 26a to 26d are formed on the resulting laminates 25 to produce the multilayer ceramic capacitor 1C.
  • the multilayer ceramic capacitor 1C is configured such that the dummy electrodes 33a-34d are thicker in the third direction (z-axis direction) than one internal electrode layer 32. This allows the multilayer ceramic capacitor 1C to reduce the number of interfaces between different materials in the coatings 33, 34 compared to multilayer ceramic capacitors of the prior art. As a result, the occurrence of delamination in the coatings 33, 34 when the laminate 25 is barrel polished can be reduced, improving the reliability of the multilayer ceramic capacitor 1C.
  • the multilayer ceramic capacitor 1C may have a configuration in which at least one of the dummy electrodes 33a to 34d is thicker than the internal electrode layer 32.
  • the multilayer ceramic capacitor 1C may include dummy electrodes 33a to 34d whose thickness is equal to or less than the thickness of the internal electrode layer 32, such as the second dummy electrode 61b, the third dummy electrode 62a, and the fourth dummy electrode 62b shown in FIG. 5.
  • the laminate 25 may have an auxiliary electrode portion similar to the auxiliary electrode portions 61ba, 62aa, and 62ba shown in FIG. 5 on the inside (below) of the dummy electrode 33b in the third direction (z-axis direction).
  • the dummy electrodes 33a to 34d may be single dummy electrodes.
  • the dummy electrodes 33a to 34d may be configured by stacking multiple dummy electrode layers, as in the case of dummy electrodes 61a to 62b shown in FIG. 6. In this case, it becomes easier to form the dummy electrodes 33a to 34d with the designed dimensions, and the reliability of the multilayer ceramic capacitor 1C can be improved.
  • the interface between at least one of the dummy electrodes 33a, 33b, 33c, 33d and the first dielectric portion 33e may have an uneven structure, as shown in interfaces 61d, 62d in FIG. 7.
  • the crack can be prevented from extending to the active portion 30.
  • the moisture resistance of the multilayer ceramic capacitor 1C can be improved, and the reliability can be improved.
  • the interface between at least one of the dummy electrodes 34a, 34b, 34c, 34d and the second dielectric portion 34e may have an uneven structure. In this case, too, the moisture resistance of the multilayer ceramic capacitor 1C can be improved, and the reliability can be improved, as described above.
  • FIG. 27 is a cross-sectional view showing a multilayer ceramic capacitor 1D according to another embodiment of the present disclosure. Note that this embodiment is similar to the embodiment of FIG. 3, and corresponding parts are given the same reference numerals, and duplicated explanations are omitted.
  • the multilayer ceramic capacitor 1D according to this embodiment may further include intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1.
  • the intermediate dummy electrodes 61a1 and 61b1 may be configured, for example, so that the intermediate dummy electrodes 61f and 61g are provided between the electrode layers located inside (below) the first and second dummy electrodes 61a and 61b in the third direction (z-axis direction) and adjacent to the lower sides of the first and second dummy electrodes 61a and 61b.
  • the intermediate dummy electrodes 61a1 and 61b1 are electrically insulated by a dielectric layer made of the same dielectric material as the dielectric portion, and the dielectric layer may be made of a ceramic material.
  • the intermediate dummy electrodes 62a1, 62b1 may be configured so that the intermediate dummy electrodes 61a1, 61b1 are provided between the electrode layers located inside (above) the third and fourth dummy electrodes 62a, 62b, respectively, and close to the third and fourth dummy electrodes 62a, 62b.
  • This can increase the area of the exposed portions of the intermediate dummy electrodes 61a1, 61b1, 62a1, 62b1 on the end faces 8a, 8b and side faces 9a, 9b. Therefore, the reliability of the multilayer ceramic capacitor 1D can be effectively improved.
  • the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have the same shape as the dummy electrodes 61a, 61b, 62a, and 62b in a plan view, or may have a different shape from the dummy electrodes 61a, 61b, 62a, and 62b.
  • the intermediate dummy electrodes 61f, 61g, 62f, and 62g may have a thickness in the third direction (z-axis direction) greater than that of the internal electrode layer 5.
  • the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have approximately the same dimensions as each other.
  • the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may be made of the same metal material as the dummy electrodes 61a, 61b, 62a, and 62b. By positioning the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 between the active portion 3 and the covering portions 61 and 62, it becomes easier for the plating film to be formed from the active portion 3 to the main surface side.
  • Figure 28 is a cross-sectional view showing a multilayer ceramic capacitor 1E according to yet another embodiment of the present disclosure. Note that this embodiment is similar to the embodiment of Figure 25, and corresponding parts are given the same reference numerals, and duplicated explanations will be omitted.
  • the multilayer ceramic capacitor 1E of this embodiment may further be provided with intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1.
  • the intermediate dummy electrodes 34a1, 34c1, 34b1, and 34d1 may be configured so that the intermediate dummy electrodes 34a1, 34c1, 34b1, and 34d1 are provided inside (above) the dummy electrodes 34a, 34c, 34b, and 34d, respectively, between the electrode layers adjacent to the dummy electrodes 34a, 34c, 34b, and 34d.
  • the intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, 34d1 may have the same shape as the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, 34d in a plan view, or may have a different shape from the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, 34d.
  • the intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, 34d1 may have a thickness in the third direction (z-axis direction) greater than that of the internal electrode layer 32.
  • the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, 34d may have approximately the same dimensions as each other.
  • the intermediate dummy electrodes 33a1, 33c1, 33b1, 33d1, 34a1, 34c1, 34b1, and 34d1 may be made of the same metal material as the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d.
  • the dummy electrodes 33a, 33c, 33b, 33d, 34a, 34c, 34b, and 34d may have a length in the y-axis direction shorter than the underlayer.
  • FIG. 29 is a perspective view showing a laminate 2B of a multilayer ceramic capacitor according to another embodiment of the present disclosure.
  • This embodiment is similar to the embodiment of FIG. 20, and corresponding parts are given the same reference numerals, and duplicated explanations are omitted.
  • the multilayer ceramic capacitor of this embodiment may further include intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 in addition to the four dummy electrodes 61a, 61b, 62c, and 62d included in the first covering portion 61.
  • the intermediate dummy electrodes 61a1 and 61b1 may be configured, for example, so that the intermediate dummy electrodes 61a1 and 61b1 are provided on the inner side (below) of the first and second dummy electrodes 61a and 61b in the third direction (z-axis direction) and between the electrode layers adjacent to the first and second dummy electrodes 61a and 61b.
  • the intermediate dummy electrodes 62a1, 62b1 are electrically insulated by a dielectric layer made of the same dielectric material as the dielectric portion, and the dielectric layer may be made of a ceramic material.
  • the intermediate dummy electrodes 62a1, 62b1 may be provided on the inner side (above) of each of the two dummy electrodes 34a, 34b, 34c, 34d included in the second covering portion 62, and between the electrode layers adjacent to the third and fourth dummy electrodes 62a, 62b. This increases the area of the exposed portions of the dummy electrodes on the end faces and side faces, effectively improving the reliability of the multilayer ceramic capacitor.
  • the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have the same shape as the dummy electrodes 61a, 61b, 62a, and 62b in a plan view, or may have a different shape from the dummy electrodes 61a, 61b, 62a, and 62b.
  • the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may have a greater thickness in the third direction (z-axis direction) than the dummy electrodes 61a, 61b, 62a, and 62b.
  • the dummy electrodes 61a, 61b, 62a, and 62b may have approximately the same dimensions.
  • the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 may be made of the same metal material as the dummy electrodes 61a, 61b, 62a, and 62b. By positioning the intermediate dummy electrodes 61a1, 61b1, 62a1, and 62b1 between the active portion 3 and the covering portions 61 and 62, the plating film is easily formed from the active portion to the main surface side.
  • the multilayer ceramic capacitor disclosed herein can suppress the occurrence of delamination in the coating while increasing the bonding strength between the laminate and the external electrodes. Therefore, the multilayer ceramic capacitor disclosed herein can provide a multilayer ceramic capacitor with improved reliability.
  • the multilayer ceramic capacitor disclosed herein can be implemented in the following configurations (1) to (10).
  • a laminate having a substantially rectangular parallelepiped shape including an active section formed by alternately stacking dielectric layers and internal electrode layers, and a first covering section and a second covering section located at both ends of the active section in a stacking direction of the dielectric layers and the internal electrode layers, the laminate having a first surface and a second surface opposed to each other in the stacking direction, a first end surface and a second end surface opposed to each other, and a first side surface and a second side surface opposed to each other; a first external electrode located from the first end surface to the first surface, the second surface, the first side surface, and the second side surface; a second external electrode located from the second end surface to the first surface, the second surface, the first side surface, and the second side surface; the first external electrode and the second external electrode are connected to different internal electrode layers of the internal electrode layer; the first covering portion has a first dielectric portion, and a first dummy electrode and a second dummy electrode located at both ends of the first dielectric portion in a first direction orthogonal to the
  • An interface between at least one of the first dummy electrode and the second dummy electrode and the first dielectric portion has an uneven structure
  • the first covering portion further includes a fifth dummy electrode and a sixth dummy electrode located at both ends of the first dielectric portion in the first direction
  • the second covering portion further includes a seventh dummy electrode and an eighth dummy electrode located at both ends of the second dielectric portion in the first direction
  • the multilayer ceramic capacitor according to any one of the above configurations (1) to (6), wherein the fifth dummy electrode and the seventh dummy electrode are exposed to the first end face, and the sixth dummy electrode and the eighth dummy electrode are exposed to the second end face.
  • the first dummy electrode, the second dummy electrode, the fifth dummy electrode, and the sixth dummy electrode are further exposed to the first surface
  • the first dummy electrode and the second dummy electrode are further exposed to the first side surface
  • the fifth dummy electrode and the sixth dummy electrode are further exposed to the second side surface
  • the third dummy electrode and the fourth dummy electrode are further exposed to the first side surface

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  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
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