WO2024199548A1 - 驱动电路、驱动方法和显示装置 - Google Patents

驱动电路、驱动方法和显示装置 Download PDF

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Publication number
WO2024199548A1
WO2024199548A1 PCT/CN2024/094704 CN2024094704W WO2024199548A1 WO 2024199548 A1 WO2024199548 A1 WO 2024199548A1 CN 2024094704 W CN2024094704 W CN 2024094704W WO 2024199548 A1 WO2024199548 A1 WO 2024199548A1
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WIPO (PCT)
Prior art keywords
transistor
output
control
electrically connected
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/094704
Other languages
English (en)
French (fr)
Inventor
曹丹
郭永林
于子阳
燕青青
谷泉泳
宋江
蒋志亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202480000973.7A priority Critical patent/CN119054009A/zh
Priority to US18/993,648 priority patent/US20250265983A1/en
Priority to DE112024001456.9T priority patent/DE112024001456T5/de
Publication of WO2024199548A1 publication Critical patent/WO2024199548A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device.
  • the existing OLED (organic light-emitting diode) pixel driving method is: each frame completes a reset, data writing and light emission stage, and the full screen maintains a refresh frequency.
  • each frame completes a reset, data writing and light emission stage, and the full screen maintains a refresh frequency.
  • In the low-frequency area some signals do not need to be reset repeatedly when maintaining the frame, and there is no need to write data voltage signals. Therefore, by controlling the source control circuit of these signals and turning off some TFTs (thin film transistors) in the circuit, the purpose of saving power can be achieved.
  • the above technology is partial refresh.
  • the output stability of the driving circuit that provides the driving signal is low.
  • an embodiment of the present disclosure provides a driving circuit, including an output circuit and an inverter circuit;
  • the output circuit is electrically connected to the output control terminal, the switch control terminal, the data line and the drive output terminal respectively, and is used to provide a drive output signal through the drive output terminal according to the data voltage provided by the data line under the control of the switch control signal provided by the switch control terminal and the output control signal provided by the output control terminal;
  • the inverting circuit includes N stages of inverters; N is a positive integer; n is a positive integer less than or equal to N;
  • the input end of the first inverter is electrically connected to the driving output end, and the output end of the Nth inverter is electrically connected to the driving signal output end;
  • the output terminal of the mth inverter is electrically connected to the input terminal of the m+1th inverter, and m is a positive integer less than N;
  • the inverter is used to invert the signal connected to its input terminal to obtain an inverted signal, and output the inverted signal through the output terminal of the inverter.
  • the output circuit includes a first data writing circuit, a differential control circuit, an input control circuit and an output control circuit;
  • the first data writing circuit is electrically connected to the switch control terminal, the first data line and the first differential control node respectively, and is used to write the first data voltage provided by the first data line into the first differential control node under the control of the switch control signal provided by the switch control terminal, and maintain the potential of the first differential control node;
  • the differential control circuit is respectively connected to the first differential control node, the second differential control node, the input node, the first input node,
  • the output node is electrically connected to the second output node, and is used to control the potential of the first output node and the potential of the second output node according to the potential of the input node under the control of the potential of the first differential control node and the potential of the second differential control node;
  • the input control circuit is electrically connected to the output control terminal, the input node and the first voltage terminal respectively, and is used to control the connection or disconnection between the input node and the first voltage terminal under the control of the output control signal provided by the output control terminal;
  • the output control circuit is electrically connected to the output control terminal, the first output node, the second output node and the driving output terminal respectively, and is used to generate and provide a driving output signal through the driving output terminal according to the potential of the first output node and the potential of the second output node under the control of the output control signal.
  • the output control circuit includes a latch circuit and a set circuit
  • the setting circuit is electrically connected to the output control terminal, the intermediate node, the driving output terminal and the second voltage terminal respectively, and is used to control the connection or disconnection between the intermediate node and the second voltage terminal, and control the connection or disconnection between the driving output terminal and the second voltage terminal under the control of the output control signal;
  • the latch circuit is electrically connected to the first output node, the second output node, the intermediate node, the drive output terminal and the second voltage terminal, respectively, and is used to control the potential of the drive output terminal according to the potential of the first output node and the potential of the second output node under the control of the potential of the intermediate node.
  • the output circuit further includes a second data writing circuit
  • the second data writing circuit is electrically connected to the switch control end, the second data line and the second differential control node, respectively, and is used to write the second data voltage provided by the second data line into the second differential control node and maintain the potential of the second differential control node under the control of the switch control signal provided by the switch control end.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a switch control circuit
  • the switch control circuit is electrically connected to the on-off control terminal, the first output control node and the second output control node respectively, and is used to control the connection or disconnection between the first output control node and the second output control node under the control of the on-off control signal provided by the on-off control terminal;
  • the first output control node is electrically connected to the driving output terminal, and the second output control node is electrically connected to the input terminal of the first inverter; or,
  • the first output control node is electrically connected to the output terminal of the Nth inverter, and the second output control node is electrically connected to the drive signal output terminal; or,
  • N is greater than 1
  • the first output control node is electrically connected to the output end of the m-th inverter
  • the second output control node is electrically connected to the input end of the (m+1)-th inverter.
  • the latch circuit is used to control the connection or disconnection between the second output node and the driving output terminal, and the connection or disconnection between the driving output terminal and the second voltage terminal, under the control of the potential of the driving output terminal; and to control the connection or disconnection between the first output node and the intermediate node, and the connection or disconnection between the intermediate node and the second voltage terminal, under the control of the potential of the driving output terminal.
  • a frame time includes a blanking period; the blanking period includes a shutdown phase, and the shutdown phase includes The setting time period is enclosed;
  • the setting circuit is used for controlling the connection between the intermediate node and the second voltage terminal, and controlling the connection between the driving output terminal and the second voltage terminal under the control of the output control signal during the setting period;
  • the switch control circuit is used for controlling the disconnection between the first output control node and the second output control node under the control of the on-off control signal during the off stage.
  • N is equal to 1;
  • the inverter circuit includes a first inverter, and the first inverter includes a first transistor and a second transistor;
  • the gate of the first transistor is electrically connected to the input terminal of the first inverter, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor and the first electrode of the second transistor are both electrically connected to the drive signal output terminal;
  • the gate of the second transistor is electrically connected to the input terminal of the first inverter, and the second electrode of the second transistor is electrically connected to the second voltage terminal;
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • N is equal to 2;
  • the inverter circuit includes a first inverter and a second inverter; the first inverter includes a first transistor and a second transistor; the second inverter includes a third transistor and a fourth transistor;
  • the gate of the first transistor is electrically connected to the input terminal of the first inverter, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor and the first electrode of the second transistor are both electrically connected to the input terminal of the second inverter;
  • the gate of the second transistor is electrically connected to the input terminal of the first inverter, and the second electrode of the second transistor is electrically connected to the second voltage terminal;
  • the gate of the third transistor and the gate of the fourth transistor are both electrically connected to the input terminal of the second inverter, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor and the first electrode of the fourth transistor are both electrically connected to the drive signal output terminal;
  • the second electrode of the fourth transistor is electrically connected to the second voltage terminal
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • the third transistor is a p-type transistor
  • the fourth transistor is an n-type transistor.
  • the first data writing circuit includes a fifth transistor and a first capacitor
  • a gate of the fifth transistor is electrically connected to the switch control terminal, a first electrode of the fifth transistor is electrically connected to the first data line, and a second electrode of the fifth transistor is electrically connected to the first differential control node;
  • a first end of the first capacitor is electrically connected to the first differential control node, and a second end of the first capacitor is electrically connected to a second voltage end.
  • the second data writing circuit includes a sixth transistor and a second capacitor; the gate of the sixth transistor is electrically connected to the switch control terminal, the first electrode of the sixth transistor is electrically connected to the second data line, and the second electrode of the sixth transistor is electrically connected to the second differential control node;
  • the first end of the second capacitor is electrically connected to the second differential control node, and the second end of the second capacitor is electrically connected to the first differential control node.
  • the two voltage terminals are electrically connected.
  • the switch control circuit includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the on-off control terminal, the first electrode of the seventh transistor is electrically connected to the first output control node, and the second electrode of the seventh transistor is electrically connected to the second output control node.
  • the input control circuit includes an eighth transistor, and the differential control circuit includes a ninth transistor and a tenth transistor;
  • the gate of the eighth transistor is electrically connected to the output control terminal, the first electrode of the eighth transistor is electrically connected to the first voltage terminal, and the second electrode of the eighth transistor is electrically connected to the input node;
  • a gate of the ninth transistor is electrically connected to the first differential control node, a first electrode of the ninth transistor is electrically connected to the input node, and a second electrode of the ninth transistor is electrically connected to the first output node;
  • a gate of the tenth transistor is electrically connected to the second differential control node, a first electrode of the tenth transistor is electrically connected to the input node, and a second electrode of the tenth transistor is electrically connected to the second output node.
  • the setting circuit includes an eleventh transistor and a twelfth transistor;
  • the gate of the eleventh transistor is electrically connected to the output control terminal, the first electrode of the eleventh transistor is electrically connected to the intermediate node, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal;
  • the gate of the twelfth transistor is electrically connected to the output control terminal, the first electrode of the twelfth transistor is electrically connected to the driving output terminal, and the second electrode of the twelfth transistor is electrically connected to the second voltage terminal.
  • the eighth transistor is a p-type transistor, and the eleventh transistor and the twelfth transistor are n-type transistors; or, the eighth transistor is an n-type transistor, and the eleventh transistor and the twelfth transistor are p-type transistors.
  • the latch circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;
  • the gate of the thirteenth transistor is electrically connected to the driving output terminal, the first electrode of the thirteenth transistor is electrically connected to the intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;
  • the gate of the fourteenth transistor is electrically connected to the intermediate node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal;
  • the gate of the fifteenth transistor is electrically connected to the driving output terminal, the first electrode of the fifteenth transistor is electrically connected to the first output node, and the second electrode of the fifteenth transistor is electrically connected to the intermediate node;
  • a gate of the sixteenth transistor is electrically connected to the intermediate node, a first electrode of the sixteenth transistor is electrically connected to the second output node, and a second electrode of the sixteenth transistor is electrically connected to the driving output terminal.
  • the thirteenth transistor and the fourteenth transistor are n-type transistors, and the fifteenth transistor and the sixteenth transistor are p-type transistors.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method includes:
  • the output circuit drives the output terminal according to the data voltage under the control of the switch control signal and the output control signal. Providing a driving output signal;
  • the inverter included in the inverting circuit inverts the signal connected to its input terminal to obtain an inverted signal, and outputs the inverted signal through the output terminal of the inverter.
  • the output circuit includes a first data writing circuit, a differential control circuit, an input control circuit and an output control circuit;
  • the output control circuit includes a latch circuit and a set circuit;
  • a frame time includes a blanking period;
  • the blanking period includes a set period and an output stage;
  • the set period includes a reset stage, a data writing stage and a potential maintaining stage;
  • the driving method includes:
  • the setting circuit controls the connection between the intermediate node and the second voltage terminal, and controls the connection between the driving output terminal and the second voltage terminal under the control of the output control signal;
  • the first data writing circuit writes the first data voltage provided by the first data line into the first differential control node under the control of the switch control signal;
  • the first data writing circuit maintains the potential of the first differential control node
  • the input control circuit controls the connection between the input node and the first voltage terminal under the control of the output control signal; the differential control circuit controls the potential of the first output node and the potential of the second output node according to the potential of the input node under the control of the potential of the first differential control node and the potential of the second differential control node; the latch circuit controls the potential of the drive output terminal according to the potential of the first output node and the potential of the second output node under the control of the potential of the intermediate node.
  • the output circuit further includes a second data writing circuit; and the driving method further includes:
  • the second data writing circuit writes the second data voltage provided by the second data line into the second differential control node under the control of the switch control signal;
  • the second data writing circuit maintains the potential of the second differential control node.
  • the driving circuit further includes a switch control circuit; the blanking period includes a turn-off phase, and the turn-off phase includes the setting period; and the driving method further includes:
  • the switch control circuit controls the first output control node to be disconnected from the second output control node under the control of the on-off control signal.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned driving circuit.
  • FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG7A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG7B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG9A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG9B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG10A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG10B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 11A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG11B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG12A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG12B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG13A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG13B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG14A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG14B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG15A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG15B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG16A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG16B is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG17 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG18 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG19 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG20 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG21A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG21B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG21A;
  • FIG21C is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG21A;
  • FIG21D is a circuit diagram of at least one embodiment of a pixel circuit
  • FIG22A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG22B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG22A;
  • FIG22C is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG22A;
  • FIG22D is a waveform diagram of the light emitting control signal provided by each row of light emitting control lines
  • FIG23A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG23B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG23A;
  • FIG23C is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG23A;
  • FIG23D is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG23A;
  • FIG24 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG25 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 26A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG26B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG26A;
  • FIG27 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG28 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG29A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG29B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG29A;
  • FIG30 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG31A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG31B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG31A;
  • FIG32 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG33 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG34 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG35 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG36 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG37 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG38 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG39 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG40 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG41 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG42 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG43 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 44 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit described in the embodiment of the present disclosure includes an output circuit and an inverting circuit
  • the output circuit is electrically connected to the output control terminal, the switch control terminal, the data line and the drive output terminal respectively, and is used to provide a drive output signal through the drive output terminal according to the data voltage provided by the data line under the control of the switch control signal provided by the switch control terminal and the output control signal provided by the output control terminal;
  • the inverting circuit includes N stages of inverters; N is a positive integer; n is a positive integer less than or equal to N;
  • the input end of the first inverter is electrically connected to the driving output end, and the output end of the Nth inverter is electrically connected to the driving signal output end;
  • the output terminal of the mth inverter is electrically connected to the input terminal of the m+1th inverter, and m is a positive integer less than N;
  • the inverter is used to invert the signal connected to its input terminal to obtain an inverted signal, and output the inverted signal through the output terminal of the inverter.
  • the driving circuit described in the embodiment of the present disclosure adopts an inverting circuit.
  • the inverting circuit includes a first-stage inverter, local low refresh can be achieved.
  • the inverting circuit includes a two-stage inverter, the driving signal provided by the driving signal output terminal can be stabilized.
  • the driving circuit described in the embodiment of the present disclosure includes an output circuit 10 and an inverting circuit 11;
  • the output circuit 10 is electrically connected to the output control terminal VCT, the switch control terminal SW, the data line SL and the driving output terminal NT respectively, and is used to provide a driving output signal through the driving output terminal NT according to the data voltage provided by the data line SL under the control of the switch control signal provided by the switch control terminal SW and the output control signal provided by the output control terminal VCT;
  • the inverting circuit comprises a first inverter F1;
  • the input end of the first inverter F1 is electrically connected to the driving output end NT, and the output end of the first inverter F1 is electrically connected to the driving signal output end OT;
  • the first inverter F1 is used to invert a signal connected to its input terminal to obtain an inverted signal, and output the inverted signal through the output terminal of the first inverter F1.
  • N is equal to 1.
  • the driving circuit described in the embodiment of the present disclosure includes an output circuit 10 and an inverting circuit 11;
  • the output circuit 10 is electrically connected to the output control terminal VCT, the switch control terminal SW, the data line SL and the driving output terminal NT respectively, and is used to provide a driving output signal through the driving output terminal NT according to the data voltage provided by the data line SL under the control of the switch control signal provided by the switch control terminal SW and the output control signal provided by the output control terminal VCT;
  • the inverting circuit includes a first inverter F1 and a second inverter F2;
  • the input end of the first inverter F1 is electrically connected to the driving output end NT, and the output end of the first inverter F1 is electrically connected to the input end of the second inverter F2;
  • the output end of the second inverter F2 is electrically connected to the drive signal output end OT;
  • the first inverter F1 is used to invert the signal connected to its input terminal to obtain a first inverted signal. Outputting the first inverted signal through the output end of the first inverter F1;
  • the second inverter F2 is used for inverting the signal connected to its input terminal to obtain a second inverted signal, and outputting the second inverted signal through the output terminal of the second inverter F2.
  • N is equal to 2.
  • the output circuit includes a first data writing circuit, a differential control circuit, an input control circuit, and an output control circuit;
  • the first data writing circuit is electrically connected to the switch control terminal, the first data line and the first differential control node respectively, and is used to write the first data voltage provided by the first data line into the first differential control node under the control of the switch control signal provided by the switch control terminal, and maintain the potential of the first differential control node;
  • the differential control circuit is electrically connected to the first differential control node, the second differential control node, the input node, the first output node, and the second output node, respectively, and is used to control the potential of the first output node and the potential of the second output node according to the potential of the input node under the control of the potential of the first differential control node and the potential of the second differential control node;
  • the input control circuit is electrically connected to the output control terminal, the input node and the first voltage terminal respectively, and is used to control the connection or disconnection between the input node and the first voltage terminal under the control of the output control signal provided by the output control terminal;
  • the output control circuit is electrically connected to the output control terminal, the first output node, the second output node and the driving output terminal respectively, and is used to generate and provide a driving output signal through the driving output terminal according to the potential of the first output node and the potential of the second output node under the control of the output control signal.
  • the first voltage terminal may be a high voltage terminal.
  • the output circuit includes a first data writing circuit 31 , a differential control circuit 32 , an input control circuit 33 and an output control circuit 34 ;
  • the first data writing circuit 31 is electrically connected to the switch control terminal SW, the first data line SL1 and the first differential control node NC1 respectively, and is used to write the first data voltage provided by the first data line SL1 into the first differential control node NC1 under the control of the switch control signal provided by the switch control terminal SW, and maintain the potential of the first differential control node NC1;
  • the second differential control node NC2 is electrically connected to the initial voltage terminal I1, and the initial voltage terminal I1 is used to provide an initial voltage Vinit;
  • the differential control circuit 32 is electrically connected to the first differential control node NC1, the second differential control node NC2, the input node N2, the first output node N3 and the second output node N4, respectively, and is used to control the potential of the first output node N3 and the potential of the second output node N4 according to the potential of the input node N2 under the control of the potential of the first differential control node NC1 and the potential of the second differential control node NC2;
  • the input control circuit 33 is electrically connected to the output control terminal VCT, the input node N2 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the input node N2 and the first voltage terminal V1 under the control of the output control signal provided by the output control terminal VCT;
  • the output control circuit 34 is electrically connected to the output control terminal VCT, the first output node N3, the second output node N4 and the driving output terminal NT, respectively, and is used to generate and provide a driving output signal through the driving output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the output control signal.
  • the output circuit includes a first data writing circuit 31 , a differential control circuit 32 , an input control circuit 33 and an output control circuit 34 ;
  • the first data writing circuit 31 is electrically connected to the switch control terminal SW, the first data line SL1 and the first differential control node NC1 respectively, and is used to write the first data voltage provided by the first data line SL1 into the first differential control node NC1 under the control of the switch control signal provided by the switch control terminal SW, and maintain the potential of the first differential control node NC1;
  • the second differential control node NC is electrically connected to the initial voltage terminal I1, and the initial voltage terminal I1 is used to provide an initial voltage Vinit;
  • the differential control circuit 32 is electrically connected to the first differential control node NC1, the second differential control node NC2, the input node N2, the first output node N3 and the second output node N4, respectively, and is used to control the potential of the first output node N3 and the potential of the second output node N4 according to the potential of the input node N2 under the control of the potential of the first differential control node NC1 and the potential of the second differential control node NC2;
  • the input control circuit 33 is electrically connected to the output control terminal VCT, the input node N2 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the input node N2 and the first voltage terminal V1 under the control of the output control signal provided by the output control terminal VCT;
  • the output control circuit 34 is electrically connected to the output control terminal VCT, the first output node N3, the second output node N4 and the driving output terminal NT, respectively, and is used to generate and provide a driving output signal through the driving output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the output control signal.
  • the output circuit further includes a second data writing circuit
  • the second data writing circuit is electrically connected to the switch control end, the second data line and the second differential control node, respectively, and is used to write the second data voltage provided by the second data line into the second differential control node and maintain the potential of the second differential control node under the control of the switch control signal provided by the switch control end.
  • the output circuit may further include a second data writing circuit, and the second data writing circuit writes the second data voltage into the second differential control node under the control of the switch control signal to maintain the potential of the second differential control node.
  • the output circuit includes a first data writing circuit 31 , a differential control circuit 32 , an input control circuit 33 , an output control circuit 34 and a second data writing circuit 35 ;
  • the first data writing circuit 31 is electrically connected to the switch control terminal SW, the first data line SL1 and the first differential control node NC1 respectively, and is used to write the first data line SL1 to the first differential control node NC1 under the control of the switch control signal provided by the switch control terminal SW.
  • the first data voltage provided by the first data line SL1 is written into the first differential control node NC1, and the potential of the first differential control node NC1 is maintained;
  • the second data writing circuit 35 is electrically connected to the switch control terminal SW, the second data line SL2 and the second differential control node NC2 respectively, and is used to write the second data voltage provided by the second data line SL2 into the second differential control node NC2 under the control of the switch control signal provided by the switch control terminal SW, and maintain the potential of the second differential control node NC2;
  • the differential control circuit 32 is electrically connected to the first differential control node NC1, the second differential control node NC2, the input node N2, the first output node N3 and the second output node N4, respectively, and is used to control the potential of the first output node N3 and the potential of the second output node N4 according to the potential of the input node N2 under the control of the potential of the first differential control node NC1 and the potential of the second differential control node NC2;
  • the input control circuit 33 is electrically connected to the output control terminal VCT, the input node N2 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the input node N2 and the first voltage terminal V1 under the control of the output control signal provided by the output control terminal VCT;
  • the output control circuit 34 is electrically connected to the output control terminal VCT, the first output node N3, the second output node N4 and the driving output terminal NT, respectively, and is used to generate and provide a driving output signal through the driving output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the output control signal.
  • the output circuit includes a first data writing circuit 31 , a differential control circuit 32 , an input control circuit 33 , an output control circuit 34 and a second data writing circuit 35 ;
  • the first data writing circuit 31 is electrically connected to the switch control terminal SW, the first data line SL1 and the first differential control node NC1 respectively, and is used to write the first data voltage provided by the first data line SL1 into the first differential control node NC1 under the control of the switch control signal provided by the switch control terminal SW, and maintain the potential of the first differential control node NC1;
  • the second data writing circuit 35 is electrically connected to the switch control terminal SW, the second data line SL2 and the second differential control node NC2 respectively, and is used to write the second data voltage provided by the second data line SL2 into the second differential control node NC2 under the control of the switch control signal provided by the switch control terminal SW, and maintain the potential of the second differential control node NC2;
  • the differential control circuit 32 is electrically connected to the first differential control node NC1, the second differential control node NC2, the input node N2, the first output node N3 and the second output node N4, respectively, and is used to control the potential of the first output node N3 and the potential of the second output node N4 according to the potential of the input node N2 under the control of the potential of the first differential control node NC1 and the potential of the second differential control node NC2;
  • the input control circuit 33 is electrically connected to the output control terminal VCT, the input node N2 and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the input node N2 and the first voltage terminal V1 under the control of the output control signal provided by the output control terminal VCT;
  • the output control circuit 34 is electrically connected to the output control terminal VCT, the first output node N3, the second output node N4 and the driving output terminal NT, respectively, and is used to generate and provide a driving output signal through the driving output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the output control signal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a switch control circuit
  • the switch control circuit is electrically connected to the on-off control terminal, the first output control node and the second output control node respectively, and is used to control the connection or disconnection between the first output control node and the second output control node under the control of the on-off control signal provided by the on-off control terminal;
  • the first output control node is electrically connected to the driving output terminal, and the second output control node is electrically connected to the input terminal of the first inverter; or,
  • the first output control node is electrically connected to the output terminal of the Nth inverter, and the second output control node is electrically connected to the drive signal output terminal; or,
  • N is greater than 1
  • the first output control node is electrically connected to the output end of the mth inverter
  • the second output control node is electrically connected to the input end of the (m+1)th inverter.
  • the driving circuit may further include a switch control circuit, and the switch control circuit controls the connection or disconnection between the first output control node and the second output control node under the control of an on-off control signal.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the drive output terminal NT and the input terminal of the first inverter F1 respectively, and is used to control the connection or disconnection between the drive output terminal NT and the input terminal of the first inverter F1 under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the drive output terminal NT and the input terminal of the first inverter F1 respectively, and is used to control the connection or disconnection between the drive output terminal NT and the input terminal of the first inverter F1 under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70;
  • the switch control circuit 70 is respectively connected to the on-off control terminal VCT2, the output terminal of the first inverter F1 and the driving
  • the signal output terminal OT is electrically connected and used to control the connection or disconnection between the output terminal of the first inverter F1 and the driving signal output terminal OT under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the first inverter F1
  • NS2 is electrically connected to the driving signal output terminal OT.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the output terminal of the first inverter F1 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the output terminal of the first inverter F1 and the drive signal output terminal OT under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the first inverter F1
  • NS2 is electrically connected to the driving signal output terminal OT.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the drive output terminal NT and the input terminal of the first inverter F1 respectively, and is used to control the connection or disconnection between the drive output terminal NT and the input terminal of the first inverter F1 under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the driving output terminal NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the drive output terminal NT and the input terminal of the first inverter F1 respectively, and is used to control the connection or disconnection between the drive output terminal NT and the input terminal of the first inverter F1 under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the driving output terminal NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the output terminal of the first inverter F1 and the input terminal of the second inverter F2, respectively, and is used to control the connection or disconnection between the output terminal of the first inverter F1 and the input terminal of the second inverter F2 under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is a first output control node.
  • the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output end of the first inverter F1
  • NS2 is electrically connected to the input end of the second inverter F2.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the output terminal of the first inverter F1 and the input terminal of the second inverter F2, respectively, and is used to control the connection or disconnection between the output terminal of the first inverter F1 and the input terminal of the second inverter F2 under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output end of the first inverter F1
  • NS2 is electrically connected to the input end of the second inverter F2.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the output terminal of the second inverter F2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the output terminal of the second inverter F2 and the drive signal output terminal OT under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the second inverter F2, and NS2 is electrically connected to the driving signal output terminal OT.
  • the driving circuit according to at least one embodiment of the present disclosure further includes a switch control circuit 70 ;
  • the switch control circuit 70 is electrically connected to the on-off control terminal VCT2, the output terminal of the second inverter F2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the output terminal of the second inverter F2 and the drive signal output terminal OT under the control of the on-off control signal provided by the on-off control terminal VCT2.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the second inverter F2, and NS2 is electrically connected to the driving signal output terminal OT.
  • the output control circuit includes a latch circuit and a set circuit
  • the setting circuit is electrically connected to the output control terminal, the intermediate node, the driving output terminal and the second voltage terminal respectively, and is used to control the connection or disconnection between the intermediate node and the second voltage terminal, and control the connection or disconnection between the driving output terminal and the second voltage terminal under the control of the output control signal;
  • the latch circuit is electrically connected to the first output node, the second output node, the intermediate node, the drive output terminal and the second voltage terminal, respectively, and is used to control the potential of the drive output terminal according to the potential of the first output node and the potential of the second output node under the control of the potential of the intermediate node.
  • the output control circuit may include a latch circuit and a set circuit.
  • the set circuit under the control of the output control signal, controls the connection or disconnection between the intermediate node and the second voltage terminal, and controls the connection or disconnection between the drive output terminal and the second voltage terminal;
  • the latch circuit under the control of the potential of the intermediate node, controls the potential of the drive output terminal according to the potential of the first output node and the potential of the second output node.
  • the latch circuit is used to control the connection or disconnection between the second output node and the driving output terminal, and the connection or disconnection between the driving output terminal and the second voltage terminal, under the control of the potential of the driving output terminal, and to control the connection or disconnection between the first output node and the intermediate node, and the connection or disconnection between the intermediate node and the second voltage terminal, under the control of the potential of the driving output terminal.
  • the second voltage terminal may be a low voltage terminal.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the driving output terminal NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the driving output terminal NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the first inverter F1
  • NS2 is electrically connected to the driving signal output terminal OT.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the first inverter F1
  • NS2 is electrically connected to the driving signal output terminal OT.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used for controlling the potential of the intermediate node N6.
  • the potential of the driving output terminal NT is controlled according to the potential of the first output node N3 and the potential of the second output node N4.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the driving output terminal NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the driving output terminal NT, and NS2 is electrically connected to the input terminal of the first inverter F1.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output end of the first inverter F1
  • NS2 is electrically connected to the input end of the second inverter F2.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is respectively connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage
  • the terminal V2 is electrically connected to the intermediate node N6, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output end of the first inverter F1
  • NS2 is electrically connected to the input end of the second inverter F2.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is the first output control node, and the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the second inverter F2, and NS2 is electrically connected to the driving signal output terminal OT.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the node labeled NS1 is a first output control node.
  • the node labeled NS2 is the second output control node;
  • NS1 is electrically connected to the output terminal of the second inverter F2, and NS2 is electrically connected to the driving signal output terminal OT.
  • a frame time includes a blanking period; the blanking period includes a shutdown phase, and the shutdown phase includes a setting period;
  • the setting circuit is used for controlling the connection between the intermediate node and the second voltage terminal, and controlling the connection between the driving output terminal and the second voltage terminal under the control of the output control signal during the setting period;
  • the switch control circuit is used for controlling the disconnection between the first output control node and the second output control node under the control of the on-off control signal during the off stage.
  • a frame time includes a blanking time period, the blanking time period includes a shutdown stage, the shutdown stage includes a set time period, in the set time period, the set circuit controls the connection between the intermediate node and the second voltage terminal, and controls the connection between the drive output terminal and the second voltage terminal under the control of the output control signal, and in the shutdown stage, the switch control circuit controls the disconnection between the first output control node and the second output control node under the control of the on-off control signal, so that in the blanking time period, the drive signal provided by the drive signal output terminal is not affected by the rising edge and falling edge of the drive output signal provided by the drive output terminal.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the output control circuit includes a latch circuit 41 and a set circuit 42;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • the output control circuit includes a latch circuit 41 and a set circuit 42 ;
  • the setting circuit 42 is electrically connected to the output control terminal VCT, the intermediate node N6, the driving output terminal NT and the second voltage terminal V2 respectively, and is used to control the connection or disconnection between the intermediate node N6 and the second voltage terminal V2, and control the connection or disconnection between the driving output terminal NT and the second voltage terminal V2 under the control of the output control signal;
  • the latch circuit 41 is electrically connected to the first output node N3, the second output node N4, the intermediate node N6, the drive output terminal NT and the second voltage terminal V2, respectively, and is used to control the potential of the drive output terminal NT according to the potential of the first output node N3 and the potential of the second output node N4 under the control of the potential of the intermediate node N6.
  • N is equal to 1;
  • the inverter circuit includes a first inverter, and the first inverter includes a first transistor and a second transistor;
  • the gate of the first transistor is electrically connected to the input terminal of the first inverter, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor and the first electrode of the second transistor are both electrically connected to the drive signal output terminal;
  • the gate of the second transistor is electrically connected to the input terminal of the first inverter, and the second electrode of the second transistor is electrically connected to the second voltage terminal;
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • N is equal to 2;
  • the inverter circuit includes a first inverter and a second inverter; the first inverter includes a first transistor and a second transistor; the second inverter includes a third transistor and a fourth transistor;
  • the gate of the first transistor is electrically connected to the input terminal of the first inverter, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor and the first electrode of the second transistor are both electrically connected to the input terminal of the second inverter;
  • the gate of the second transistor is electrically connected to the input terminal of the first inverter, and the second electrode of the second transistor is electrically connected to the second voltage terminal;
  • the gate of the third transistor and the gate of the fourth transistor are both electrically connected to the input terminal of the second inverter.
  • the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor and the first electrode of the fourth transistor are both electrically connected to the drive signal output terminal;
  • the second electrode of the fourth transistor is electrically connected to the second voltage terminal
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • the third transistor is a p-type transistor
  • the fourth transistor is an n-type transistor.
  • the first data writing circuit includes a fifth transistor and a first capacitor
  • a gate of the fifth transistor is electrically connected to the switch control terminal, a first electrode of the fifth transistor is electrically connected to the first data line, and a second electrode of the fifth transistor is electrically connected to the first differential control node;
  • a first end of the first capacitor is electrically connected to the first differential control node, and a second end of the first capacitor is electrically connected to a second voltage end.
  • the second data writing circuit includes a sixth transistor and a second capacitor; the gate of the sixth transistor is electrically connected to the switch control terminal, the first electrode of the sixth transistor is electrically connected to the second data line, and the second electrode of the sixth transistor is electrically connected to the second differential control node;
  • a first end of the second capacitor is electrically connected to the second differential control node, and a second end of the second capacitor is electrically connected to the second voltage end.
  • the switch control circuit includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the on-off control terminal, the first electrode of the seventh transistor is electrically connected to the first output control node, and the second electrode of the seventh transistor is electrically connected to the second output control node.
  • the first output control node is electrically connected to the driving output terminal, and the second output control node is electrically connected to the input terminal of the first inverter; or,
  • the first output control node is electrically connected to the output terminal of the Nth inverter, and the second output control node is electrically connected to the drive signal output terminal; or,
  • N is greater than 1
  • the first output control node is electrically connected to the output end of the mth inverter
  • the second output control node is electrically connected to the input end of the (m+1)th inverter.
  • the input control circuit includes an eighth transistor, and the differential control circuit includes a ninth transistor and a tenth transistor;
  • the gate of the eighth transistor is electrically connected to the output control terminal, the first electrode of the eighth transistor is electrically connected to the first voltage terminal, and the second electrode of the eighth transistor is electrically connected to the input node;
  • a gate of the ninth transistor is electrically connected to the first differential control node, a first electrode of the ninth transistor is electrically connected to the input node, and a second electrode of the ninth transistor is electrically connected to the first output node;
  • a gate of the tenth transistor is electrically connected to the second differential control node, a first electrode of the tenth transistor is electrically connected to the input node, and a second electrode of the tenth transistor is electrically connected to the second output node.
  • the setting circuit includes an eleventh transistor and a twelfth transistor;
  • the gate of the eleventh transistor is electrically connected to the output control terminal, the first electrode of the eleventh transistor is electrically connected to the intermediate node, and the second electrode of the eleventh transistor is electrically connected to the second voltage terminal;
  • the gate of the twelfth transistor is electrically connected to the output control terminal, the first electrode of the twelfth transistor is electrically connected to the driving output terminal, and the second electrode of the twelfth transistor is electrically connected to the second voltage terminal.
  • the eighth transistor is a p-type transistor, and the eleventh transistor and the twelfth transistor are n-type transistors; or, the eighth transistor is an n-type transistor, and the eleventh transistor and the twelfth transistor are p-type transistors.
  • the latch circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;
  • the gate of the thirteenth transistor is electrically connected to the driving output terminal, the first electrode of the thirteenth transistor is electrically connected to the intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;
  • the gate of the fourteenth transistor is electrically connected to the intermediate node, the first electrode of the fourteenth transistor is electrically connected to the driving output terminal, and the second electrode of the fourteenth transistor is electrically connected to the second voltage terminal;
  • the gate of the fifteenth transistor is electrically connected to the driving output terminal, the first electrode of the fifteenth transistor is electrically connected to the first output node, and the second electrode of the fifteenth transistor is electrically connected to the intermediate node;
  • a gate of the sixteenth transistor is electrically connected to the intermediate node, a first electrode of the sixteenth transistor is electrically connected to the second output node, and a second electrode of the sixteenth transistor is electrically connected to the driving output terminal.
  • the thirteenth transistor and the fourteenth transistor are n-type transistors, and the fifteenth transistor and the sixteenth transistor are p-type transistors.
  • the first inverter includes a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the input terminal of the first inverter, the source of the first transistor T1 is electrically connected to the high voltage terminal VGH, and the drain of the first transistor T1 and the source of the second transistor T2 are both electrically connected to the drive signal output terminal OT;
  • the gate of the second transistor T2 is electrically connected to the input terminal of the first inverter, and the drain of the second transistor T2 is electrically connected to the low voltage terminal VGL;
  • the input terminal of the first inverter is electrically connected to the driving output terminal NT;
  • the first transistor T1 is a p-type transistor, and the second transistor T2 is an n-type transistor;
  • the first data writing circuit includes a fifth transistor T5 and a first capacitor C1;
  • the gate of the fifth transistor T5 is electrically connected to the switch control terminal SW, the source of the fifth transistor T5 is electrically connected to the first data line SL1, and the drain of the fifth transistor T5 is electrically connected to the first differential control node NC1;
  • a first end of the first capacitor C1 is electrically connected to the first differential control node NC1, and a second end of the first capacitor C1 is electrically connected to the low voltage end VGL;
  • the input control circuit includes an eighth transistor T8, and the differential control circuit includes a ninth transistor T9 and a tenth transistor T10;
  • the gate of the eighth transistor T8 is electrically connected to the output control terminal VCT, and the source of the eighth transistor T8 is electrically connected to the output control terminal VCT.
  • the drain of the eighth transistor T8 is electrically connected to the input node N2;
  • the gate of the ninth transistor T9 is electrically connected to the first differential control node NC1, the source of the ninth transistor T9 is electrically connected to the input node N2, and the drain of the ninth transistor T9 is electrically connected to the first output node N3;
  • the gate of the tenth transistor T10 is electrically connected to the second differential control node NC2, the source of the tenth transistor T10 is electrically connected to the input node N2, and the drain of the tenth transistor T10 is electrically connected to the second output node N4; the second differential control node NC2 is electrically connected to the initial voltage terminal I1;
  • the setting circuit includes an eleventh transistor T11 and a twelfth transistor T12;
  • the gate of the eleventh transistor T11 is electrically connected to the output control terminal VCT, the source of the eleventh transistor T11 is electrically connected to the intermediate node N6, and the source of the eleventh transistor T11 is electrically connected to the low voltage terminal VGL;
  • the gate of the twelfth transistor T12 is electrically connected to the output control terminal VCT, the source of the twelfth transistor T12 is electrically connected to the driving output terminal NT, and the drain of the twelfth transistor T12 is electrically connected to the low voltage terminal VGL;
  • the eighth transistor T8 is a p-type transistor, and the eleventh transistor T11 and the twelfth transistor T12 are n-type transistors;
  • the latch circuit includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16;
  • the gate of the thirteenth transistor T13 is electrically connected to the driving output terminal NT, the source of the thirteenth transistor T13 is electrically connected to the middle node N6, and the drain of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL;
  • the gate of the fourteenth transistor T14 is electrically connected to the middle node N6, the source of the fourteenth transistor T14 is electrically connected to the driving output terminal NT, and the drain of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL;
  • the gate of the fifteenth transistor T15 is electrically connected to the driving output terminal NT, the source of the fifteenth transistor T15 is electrically connected to the first output node N3, and the drain of the fifteenth transistor T15 is electrically connected to the intermediate node N6;
  • the gate of the sixteenth transistor T16 is electrically connected to the intermediate node N6, the source of the sixteenth transistor T16 is electrically connected to the second output node N4, and the drain of the sixteenth transistor T16 is electrically connected to the driving output terminal NT;
  • the thirteenth transistor T13 and the fourteenth transistor T14 are n-type transistors, and the fifteenth transistor T15 and the sixteenth transistor T16 are p-type transistors.
  • the second voltage terminal may be a low voltage terminal, but is not limited thereto.
  • T1 , T8 , T9 , T10 , T15 , and T16 are all p-type transistors, and T2 , T5 , T11 , T12 , T13 , and T14 are all n-type transistors.
  • FIG. 21B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 21A .
  • the time labeled F1 is a frame time
  • the time labeled SX is a blanking time period which is set at the very beginning of the frame time F1
  • the time labeled SD is a display time period included in the frame time F1 .
  • FIG. 21C is an enlarged timing diagram of the blanking period SX in FIG. 21B .
  • the blanking time period includes a first time period ST1 , a second time period ST2 , a third time period ST3 and a fourth time period ST4 which are set successively;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • the potential of N6 is a low voltage
  • NT is connected to VGL
  • T15 and T16 are both turned on
  • N3 and N4 are both connected to VGL
  • the first inverter formed by T1 and T2 inverts the driving output signal provided by NT
  • OT outputs a high voltage signal
  • SW provides a low voltage signal and T5 is turned off;
  • T5 is turned on, and the first data voltage provided by SL1 is written into NC1. Since T5 is an IGZO (indium gallium zinc oxide) TFT (thin film transistor), it takes a certain time to write the first data voltage into NC1.
  • IGZO indium gallium zinc oxide
  • SW provides a low voltage signal
  • VCT provides a high voltage signal
  • T5 is closed, the time for writing the first data voltage into NC1 is up, NC1 is no longer charged, and the potential of NC1 is maintained through C1;
  • VCT provides a low voltage signal
  • T11 and T12 are turned off
  • T8 is turned on
  • VGH is continuously written into N2 through T8
  • I1 provides an initial voltage Vinit. Since there is a voltage difference between the potential of NC1 and the voltage value of Vinit, the potential of N3 is different from the potential of N4.
  • the potential of NC1 is greater than the voltage value of Vinit, and the potential of N3 is less than the potential of N4; at the beginning of the fourth time period ST4, T15 and T16 are turned on, the potential of N6 is less than the potential of NT, T16 is turned on, NT outputs a high voltage signal, and OT outputs a low voltage signal.
  • the fourth time period ST4 when at least one embodiment of the driving circuit shown in FIG. 21A of the present disclosure is in operation, in the fourth time period ST4, when the potential of NC1 is less than the voltage value of Vinit, the potential of N3 is greater than the potential of N4, and at the beginning of the fourth time period ST4, T15 and T16 are turned on, the potential of N6 is greater than the potential of NT, T14 is turned on, NT outputs a low voltage signal, and OT outputs a high voltage signal.
  • the driving signal output by OT in the display time period is the same as the driving signal output by OT in the fourth time period ST4; OT outputs a low voltage signal in both the fourth time period ST4 and the display time period SD; or, OT outputs a high voltage signal in both the fourth time period ST4 and the display time period SD.
  • T13 , T14 , T15 , and T16 constitute a latch
  • T9 and T10 constitute a differential portion.
  • the driving circuit described in at least one embodiment of the present disclosure may provide a driving signal to the gate of the first control transistor M9 in the pixel circuit shown in FIG. 21D through the driving signal output terminal OT;
  • At least one embodiment of the pixel circuit may include a driving transistor M3, a first initialization transistor transistor M1, compensation control transistor M2, data writing transistor M4, first light emission control transistor M5, second light emission control transistor M6, second initialization transistor M7, third initialization transistor M8, first control transistor M9, storage capacitor Cst and organic light emitting diode O1;
  • the gate of M5 is electrically connected to the light emitting control line EM, the source of M5 is electrically connected to the power supply voltage terminal VDD, and the drain of M5 is electrically connected to the source of M3;
  • the gate of M9 is electrically connected to the first control terminal S0, the drain of M9 is electrically connected to the gate of M3, the source of M9 is electrically connected to the drain of M2, and the source of M2 is electrically connected to the drain of M3;
  • the gate of M1 is electrically connected to the first reset control terminal RP, the source of M1 is electrically connected to the first initial voltage terminal I01, and the drain of M1 is electrically connected to the drain of M3;
  • the gate of M2 is electrically connected to the compensation control terminal GN;
  • the gate of M4 is electrically connected to the scanning terminal GP, the source of M4 is electrically connected to the data line DL, and the drain of M4 is electrically connected to the source of M3;
  • the gate of M6 is electrically connected to the light-emitting control line EM, the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low-level terminal VSS;
  • the gate of M7 is electrically connected to the second reset control terminal RH, the source of M7 is electrically connected to the second initial voltage terminal I02, and the drain of M7 is electrically connected to the anode of O1;
  • the gate of M8 is electrically connected to the second reset control terminal RH, the source of M8 is electrically connected to the third initial voltage terminal I03, and the drain of M8 is electrically connected to the source of M3;
  • a first end of Cst is electrically connected to the gate of M3, and a second end of Cst is electrically connected to the power supply voltage terminal VDD.
  • M2 and M9 are oxide transistors, M2 and M9 are n-type transistors, and the other transistors are p-type transistors.
  • the inverter circuit includes a first inverter and a second inverter; the first inverter includes a first transistor T1 and a second transistor T2; the second inverter includes a third transistor T3 and a fourth transistor T4;
  • the gate of the first transistor T1 is electrically connected to the input terminal of the first inverter, the source of the first transistor T1 is electrically connected to the high voltage terminal VGH, and the drain of the first transistor T1 and the source of the second transistor T2 are both electrically connected to the input terminal of the second inverter;
  • the gate of the second transistor T2 is electrically connected to the input terminal of the first inverter, and the drain of the second transistor T2 is electrically connected to the low voltage terminal;
  • the gate of the third transistor T3 and the gate of the fourth transistor T4 are both electrically connected to the input terminal of the second inverter, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 and the source of the fourth transistor T4 are both electrically connected to the drive signal output terminal OT;
  • the drain of the fourth transistor T4 is electrically connected to the low voltage terminal VGL;
  • the first transistor T1 is a p-type transistor
  • the second transistor T2 is an n-type transistor
  • the third transistor T3 is a p-type transistor
  • the fourth transistor T4 is an n-type transistor
  • the input terminal of the first inverter is electrically connected to the driving output terminal NT;
  • the first data writing circuit includes a fifth transistor T5 and a first capacitor C1;
  • the gate of the fifth transistor T5 is electrically connected to the switch control terminal SW, the source of the fifth transistor T5 is electrically connected to the first data line SL1, and the drain of the fifth transistor T5 is electrically connected to the first differential control node NC1;
  • a first end of the first capacitor C1 is electrically connected to the first differential control node NC1, and a second end of the first capacitor C1 is electrically connected to the low voltage end VGL;
  • the input control circuit includes an eighth transistor T8, and the differential control circuit includes a ninth transistor T9 and a tenth transistor T10;
  • the gate of the eighth transistor T8 is electrically connected to the output control terminal VCT, the source of the eighth transistor T8 is electrically connected to the high voltage terminal VGH, and the drain of the eighth transistor T8 is electrically connected to the input node N2;
  • the gate of the ninth transistor T9 is electrically connected to the first differential control node NC1, the source of the ninth transistor T9 is electrically connected to the input node N2, and the drain of the ninth transistor T9 is electrically connected to the first output node N3;
  • the gate of the tenth transistor T10 is electrically connected to the second differential control node NC2, the source of the tenth transistor T10 is electrically connected to the input node N2, and the drain of the tenth transistor T10 is electrically connected to the second output node N4; the second differential control node NC2 is electrically connected to the initial voltage terminal I1;
  • the setting circuit includes an eleventh transistor T11 and a twelfth transistor T12;
  • the gate of the eleventh transistor T11 is electrically connected to the output control terminal VCT, the source of the eleventh transistor T11 is electrically connected to the intermediate node N6, and the source of the eleventh transistor T11 is electrically connected to the low voltage terminal VGL;
  • the gate of the twelfth transistor T12 is electrically connected to the output control terminal VCT, the source of the twelfth transistor T12 is electrically connected to the driving output terminal NT, and the drain of the twelfth transistor T12 is electrically connected to the low voltage terminal VGL;
  • the eighth transistor T8 is a p-type transistor, and the eleventh transistor T11 and the twelfth transistor T12 are n-type transistors;
  • the latch circuit includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16;
  • the gate of the thirteenth transistor T13 is electrically connected to the driving output terminal NT, the source of the thirteenth transistor T13 is electrically connected to the middle node N6, and the drain of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL;
  • the gate of the fourteenth transistor T14 is electrically connected to the middle node N6, and the source of the fourteenth transistor T14 is electrically connected to the middle node N6. is electrically connected to the driving output terminal NT, and the drain of the fourteenth transistor T14 is electrically connected to the low voltage terminal VGL;
  • the gate of the fifteenth transistor T15 is electrically connected to the driving output terminal NT, the source of the fifteenth transistor T15 is electrically connected to the first output node N3, and the drain of the fifteenth transistor T15 is electrically connected to the intermediate node N6;
  • the gate of the sixteenth transistor T16 is electrically connected to the intermediate node N6, the source of the sixteenth transistor T16 is electrically connected to the second output node N4, and the drain of the sixteenth transistor T16 is electrically connected to the driving output terminal OT;
  • the thirteenth transistor T13 and the fourteenth transistor T14 are n-type transistors, and the fifteenth transistor T15 and the sixteenth transistor T16 are p-type transistors.
  • T1 , T3 , T8 , T9 , T10 , T15 , and T16 are all p-type transistors
  • T2 , T4 , T5 , T11 , T12 , T13 , and T14 are all n-type transistors.
  • T1 and T2 form a first inverter
  • T3 and T4 form a second inverter
  • T1, T2, T3, and T4 can be used to amplify and stabilize the driving output signal and output the driving signal.
  • FIG. 22B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 22A .
  • the time labeled F1 is a frame time
  • the time labeled SX is a blanking time period
  • the blanking time period SX is set at the very beginning of the frame time F1
  • the time labeled SD is a display time period included in the frame time F1.
  • the blanking time period includes a first time period ST1 , a second time period ST2 , a third time period ST3 and a fourth time period ST4 which are set successively;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on, NT outputs a low voltage signal, and after passing through two stages of inverters, OT outputs a low voltage signal;
  • SW provides a low voltage signal and T5 is turned off;
  • T5 is turned on, and the first data voltage provided by SL1 is written into NC1. Since T5 is an IGZO TFT (thin film transistor), it takes a certain amount of time to write the first data voltage into NC1.
  • IGZO TFT thin film transistor
  • SW provides a low voltage signal
  • VCT provides a high voltage signal
  • T5 is closed, the time for writing the first data voltage into NC1 is up, NC1 is no longer charged, and the potential of NC1 is maintained through C1;
  • VCT provides a low voltage signal
  • T11 and T12 are turned off
  • T8 is turned on
  • VGH is continuously written into N2 through T8
  • I1 provides an initial voltage Vinit
  • the potential of NC1 is greater than the voltage value of Vinit, and the potential of N3 is less than the potential of N4; at the beginning of the fourth time period ST4, T15 and T16 are turned on, the potential of N6 is less than the potential of NT, T16 is turned on, NT outputs a high voltage signal, and OT outputs a high voltage signal.
  • the fourth time period ST4 when at least one embodiment of the driving circuit shown in FIG. 22A of the present disclosure is in operation, in the fourth time period ST4, when the potential of NC1 is less than the voltage value of Vinit, the potential of N3 is greater than the potential of N4, and at the beginning of the fourth time period ST4, T15 and T16 are turned on, the potential of N6 is greater than the potential of NT, T14 is turned on, NT outputs a low voltage signal, and OT outputs a low voltage signal.
  • the driving signal output by OT in the display time period is the same as the driving signal output by OT in the fourth time period ST4; OT outputs a low voltage signal in both the fourth time period ST4 and the display time period SD; or, OT outputs a high voltage signal in both the fourth time period ST4 and the display time period SD.
  • T13 , T14 , T15 , and T16 form a latch, and T9 and T10 form a differential portion.
  • the driving output signal output by NT will cause a pull-down signal or a pull-up signal with the same pulse width as the output control signal provided by VCT, and the driving signal output by OT will also be disturbed.
  • At least one embodiment of the pixel circuit shown in FIG21D is in operation, when OT outputs a high voltage signal, M9 is in an on state, and when OT outputs a low voltage signal, M9 is in an off state.
  • the capacitance mainly includes: the parasitic capacitance of M9 itself; in the Layout design, the capacitance between nodes outside the TFT; wherein, the capacitance between nodes outside the TFT can be optimized from the design to be reduced as much as possible, but the capacitance of M9 itself is inevitable in the TFT itself and cannot be completely eliminated, and the capacitance value is in the order of fF, which is considered a large capacitance in the capacitance between nodes at the pixel level.
  • the display panel including at least one embodiment of the pixel circuit shown in FIG. 21D includes multiple rows of light emitting control lines, and in the display time period SD, each row of light emitting control lines outputs a corresponding light emitting control signal, and each light emitting control signal has three upward pulses;
  • the light emitting control signals provided by some of the light emitting control lines have rising edges.
  • the light control lines labeled EM1 are the first row
  • the light control lines labeled EM2 are the second row
  • the light control lines labeled EM3 are the third row
  • the light control lines labeled EM4 are the fourth row
  • the light control lines labeled EMN-3 are the N-3th row
  • the light control lines labeled EMN-2 are the N-2th row
  • the light control lines labeled EMN-1 are the N-1th row
  • the light control lines labeled EMN are the Nth row
  • N is an integer greater than 7;
  • the N-3th row light control signal provided by EMN-3, the N-2th row light control signal provided by EMN-2, the N-1th row light control signal provided by EMN-1, and the Nth row light control signal provided by EMN-1 have rising edges.
  • the drive signal output by OT has a pull-down signal.
  • the pixel circuit there is a capacitor between the gate of M9 and the gate of the driving transistor M3.
  • the pull-down signal of the drive signal has a coupling effect on the potential of the gate of M3, thereby lowering the potential of the gate of M3.
  • the light-emitting control line outputs multiple pulses, the light-emitting control signal of some rows is pulled down.
  • the signal is in the off state during the blanking period, and most of the light-emitting control signals remain in the on state during the blanking period.
  • the organic light-emitting diode in the pixel circuit is in the light-emitting stage.
  • the change in the potential of the gate of the driving transistor M3 has different effects on the light-emitting of the pixel circuits corresponding to the two area rows, resulting in brightness differences in different areas, resulting in a multi-split screen situation.
  • the optimization schemes can be divided into two categories: one is to reduce the capacitance between the gate of M9 and the gate of the driving transistor M3, and reduce the coupling effect on the gate of M3 caused by the disturbance of the driving signal; the other is to start from the driving circuit that generates the driving signal, so that the driving signal output by the driving circuit is stable.
  • a driving circuit which adopts a switch control circuit.
  • the switch control circuit controls the connection or disconnection between the first output control node and the second output control node under the control of the on-off control signal provided by the on-off control terminal VCT2, so that the driving signal output by the driving signal output terminal OT is not affected by the output control signal provided by VCT.
  • the pulse width of the on-off control signal provided by VCT2 is greater than the pulse width of the output control signal provided by VCT, the start time of the effective time period of the on-off control signal is earlier than the start time of the effective time period of the output control signal, and the end time of the effective time period of the on-off control signal is later than the end time of the effective time period of the output control signal.
  • the effective time period of the on-off control signal refers to: the time period during which the on-off control signal is a valid voltage signal;
  • the effective time period of the output control signal refers to: the time period during which the output control signal is a valid voltage signal
  • the effective voltage signal is a high voltage signal
  • the transistor controlled by the on-off control signal is a p-type transistor
  • the effective voltage signal is a low voltage signal
  • the effective voltage signal is a high voltage signal
  • the transistor controlled by the output control signal is a p-type transistor
  • the effective voltage signal is a low voltage signal.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the driving output terminal NT, and the drain of the seventh transistor T7 is electrically connected to the gate of T1 .
  • T7 is a p-type transistor, and T7 is an LTPS (low temperature polysilicon) transistor.
  • one frame time includes a blanking period SX, the blanking period includes a shutoff phase SG, and the shutoff phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a high voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • a switch control circuit is additionally provided, and the switch control circuit includes a seventh transistor,
  • the seventh transistor is an isolation TFT (thin film transistor), which isolates the change of the driving output signal caused by the signal jump in each frame in the driving circuit, improves the stability of the driving signal, and improves the display effect of the OLED (organic light emitting diode) display product.
  • FIG23C is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG23B;
  • the time labeled F1 is a frame time
  • the time labeled SX is a blanking time period
  • the blanking time period SX is set at the very beginning of the frame time F1
  • the time labeled SD is a display time period included in the frame time F1.
  • the blanking time period includes a first time period ST1 , a second time period ST2 , a third time period ST3 and a fourth time period ST4 which are set successively;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 and NT are connected to VGL
  • T15 and T16 are turned on
  • NT outputs a low voltage signal
  • T7 is turned off
  • OT maintains outputting a high voltage signal
  • SW provides a low voltage signal and T5 is turned off;
  • T5 is turned on, and the first data voltage provided by SL1 is written into NC1. Since T5 is an IGZO TFT (thin film transistor), it takes a certain amount of time to write the first data voltage into NC1.
  • IGZO TFT thin film transistor
  • SW provides a low voltage signal
  • VCT provides a high voltage signal
  • T5 is closed, the time for writing the first data voltage into NC1 is up, NC1 is no longer charged, and the potential of NC1 is maintained through C1;
  • VCT provides a low voltage signal
  • T11 and T12 are turned off
  • T8 is turned on
  • VGH is continuously written into N2 through T8
  • I1 provides an initial voltage Vinit. Since there is a voltage difference between the potential of NC1 and the voltage value of Vinit, the potential of N3 is different from the potential of N4.
  • VCT2 provides a low voltage signal and T7 is turned on;
  • the potential of NC1 is greater than the voltage value of Vinit, and the potential of N3 is less than the potential of N4; at the beginning of the fourth time period ST4, T15 and T16 are turned on, the potential of N6 is less than the potential of NT, T16 is turned on, NT outputs a high voltage signal, and OT outputs a high voltage signal.
  • the fourth time period ST4 when at least one embodiment of the driving circuit shown in FIG. 23A of the present disclosure is in operation, in the fourth time period ST4, when the potential of NC1 is less than the voltage value of Vinit, the potential of N3 is greater than the potential of N4, and at the beginning of the fourth time period ST4, T15 and T16 are turned on, the potential of N6 is greater than the potential of NT, T14 is turned on, NT outputs a low voltage signal, and OT outputs a low voltage signal.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the drain of T1 , and the drain of the seventh transistor T7 is electrically connected to the gate of T3 .
  • T7 is a p-type transistor, and T7 is a LTPS (low temperature polysilicon transistor). crystalline silicon) transistor.
  • a frame time includes a blanking period SX, the blanking period includes a shutoff phase SG, and the shutoff phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a high voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the drain of T3 , and the drain of the seventh transistor T7 is electrically connected to the drive signal output terminal OT.
  • T7 is a p-type transistor, and T7 is an LTPS (low temperature polysilicon) transistor.
  • a frame time includes a blanking period SX, the blanking period includes a shut-off phase SG, and the shut-off phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a high voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the driving output terminal NT, and the drain of the seventh transistor T7 is electrically connected to the gate of T1 .
  • T7 is an n-type transistor, and T7 is an IGZO (Indium Gallium Zinc Oxide) transistor.
  • one frame time includes a blanking period SX, the blanking period includes a shutoff phase SG, and the shutoff phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL.
  • the NT and VGL are connected;
  • VCT2 provides a low voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the drain of T1 , and the drain of the seventh transistor T7 is electrically connected to the gate of T3 .
  • T7 is an n-type transistor, and T7 is an IGZO (Indium Gallium Zinc Oxide) transistor.
  • a frame time includes a blanking period SX, the blanking period includes a shut-off phase SG, and the shut-off phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a low voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the drain of T3 , and the drain of the seventh transistor T7 is electrically connected to the drive signal output terminal OT.
  • T7 is an n-type transistor, and T7 is an IGZO (Indium Gallium Zinc Oxide) transistor.
  • one frame time includes a blanking period SX, the blanking period includes a shut-off phase SG, and the shut-off phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a low voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the driving output terminal NT, and the drain of the seventh transistor T7 is electrically connected to the gate of T1 .
  • T7 is a p-type transistor, and T7 is an LTPS (low temperature polysilicon) transistor.
  • one frame time includes a blanking period SX
  • the blanking period includes a shutoff phase SG
  • the shutoff phase SG includes a set period SZ
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a high voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the drain of T1 , and the drain of the seventh transistor T7 is electrically connected to the driving signal output terminal OT.
  • T7 is a p-type transistor, and T7 is an LTPS (low temperature polysilicon) transistor.
  • a frame time includes a blanking period SX, the blanking period includes a shutoff phase SG, and the shutoff phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a high voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the driving output terminal NT, and the drain of the seventh transistor T7 is electrically connected to the gate of T1 .
  • T7 is an n-type transistor, and T7 is an IGZO (Indium Gallium) zinc oxide) transistor.
  • one frame time includes a blanking period SX
  • the blanking period includes a shutoff phase SG
  • the shutoff phase SG includes a set period SZ
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a low voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the switch control circuit includes a seventh transistor T7;
  • the gate of the seventh transistor T7 is electrically connected to the on/off control terminal VCT2 , the source of the seventh transistor T7 is electrically connected to the drain of T1 , and the drain of the seventh transistor T7 is electrically connected to the driving signal output terminal OT.
  • T7 is an n-type transistor, and T7 is an IGZO (Indium Gallium Zinc Oxide) transistor.
  • a frame time includes a blanking period SX, the blanking period includes a shutoff phase SG, and the shutoff phase SG includes a set period SZ;
  • VCT provides a high voltage signal
  • T11 and T12 are turned on
  • N6 is connected to VGL
  • NT is connected to VGL
  • VCT2 provides a low voltage signal and T7 is turned off, so that the driving signal provided by OT is not affected by the output control signal provided by VCT.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 33 and at least one embodiment of the driving circuit shown in FIG. 21A is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • T6 is an n-type transistor.
  • the driving circuit shown in FIGS. 33 to 44 of the present disclosure when SW provides a high voltage signal, the first data voltage provided by SL1 is written into NC1, and the second data voltage provided by SL2 is written into NC2.
  • the potential of NC1 and the potential of NC2 are differentiated.
  • the first data voltage provided by SL1 is a low voltage signal
  • the second data voltage provided by SL2 is a low voltage signal.
  • the first data voltage provided by SL1 is a high voltage signal
  • the second data voltage provided by SL2 is a low voltage signal
  • the first data voltage is a 7V voltage signal
  • the second data voltage is a 0V voltage signal
  • the first data voltage is a 0V voltage signal
  • the second data voltage is a 7V voltage signal
  • T15 and T16 can complete a better differential function, and because the potential of the first differential control node NC1 is significantly different from the potential of the second differential control node NC2, therefore, for at least one embodiment of the driving circuit shown in Figures 21A and 22A, the differential effect of T15 and T16 is more obvious, and the Margin of the driving circuit is also larger.
  • the driving circuit since the driving circuit needs to use the data voltages on two adjacent data lines at the same time, the local refresh control resolution in the column direction is relatively large; a first-level driving circuit can drive two adjacent rows of pixel circuits.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 34 and at least one embodiment of the driving circuit shown in FIG. 22A is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the second voltage terminal may be a low voltage terminal.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 35 and at least one embodiment of the driving circuit shown in FIG. 23A is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG36 and at least one embodiment of the driving circuit shown in FIG24 is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 37 and at least one embodiment of the driving circuit shown in FIG. 25 is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 38 and at least one embodiment of the driving circuit shown in FIG. 26A is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 39 and at least one embodiment of the driving circuit shown in FIG. 27 is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 40 and at least one embodiment of the driving circuit shown in FIG. 28 is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 41 and at least one embodiment of the driving circuit shown in FIG. 29A is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 42 and at least one embodiment of the driving circuit shown in FIG. 30 is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 43 and at least one embodiment of the driving circuit shown in FIG. 31A is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 44 and at least one embodiment of the driving circuit shown in FIG. 32 is as follows: it further includes a second data writing circuit;
  • the second data writing circuit includes a sixth transistor T6 and a second capacitor C2;
  • the gate of the sixth transistor T6 is electrically connected to the switch control terminal SW, the source of the sixth transistor T6 is electrically connected to the second data line SL2, and the drain of the sixth transistor T6 is electrically connected to the second differential control node NC2;
  • a first end of the second capacitor C2 is electrically connected to the second differential control node NC2 , and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:
  • the output circuit provides a driving output signal through the driving output terminal according to the data voltage under the control of the switch control signal and the output control signal;
  • the inverter included in the inverting circuit inverts the signal connected to its input terminal to obtain an inverted signal, and outputs the inverted signal through the output terminal of the inverter.
  • the output circuit includes a first data writing circuit, a differential control circuit, an output An input control circuit and an output control circuit;
  • the output control circuit includes a latch circuit and a set circuit;
  • a frame time includes a blanking period;
  • the blanking period includes a set period and an output stage;
  • the set period includes a reset stage, a data writing stage and a potential maintaining stage;
  • the driving method includes:
  • the setting circuit controls the connection between the intermediate node and the second voltage terminal, and controls the connection between the driving output terminal and the second voltage terminal under the control of the output control signal;
  • the first data writing circuit writes the first data voltage provided by the first data line into the first differential control node under the control of the switch control signal;
  • the first data writing circuit maintains the potential of the first differential control node
  • the input control circuit controls the connection between the input node and the first voltage terminal under the control of the output control signal; the differential control circuit controls the potential of the first output node and the potential of the second output node according to the potential of the input node under the control of the potential of the first differential control node and the potential of the second differential control node; the latch circuit controls the potential of the drive output terminal according to the potential of the first output node and the potential of the second output node under the control of the potential of the intermediate node.
  • the output circuit further includes a second data writing circuit; and the driving method further includes:
  • the second data writing circuit writes the second data voltage provided by the second data line into the second differential control node under the control of the switch control signal;
  • the second data writing circuit maintains the potential of the second differential control node.
  • the driving circuit further includes a switch control circuit; the blanking period includes a turn-off phase, and the turn-off phase includes the setting period; and the driving method further includes:
  • the switch control circuit controls the first output control node to be disconnected from the second output control node under the control of the on-off control signal.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

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Abstract

一种驱动电路、驱动方法和显示装置。驱动电路包括输出电路(10)和反相电路(11)；输出电路(10)在开关控制信号和输出控制信号的控制下，根据数据电压，通过驱动输出端提供驱动输出信号；反相电路(11)包括N级反相器；N为正整数；第一反相器的输入端与驱动输出端电连接，第N反相器的输出端与驱动信号输出端电连接；当N大于1时，第m反相器的输出端与第m+1反相器的输入端电连接，m为小于N的正整数；反相器用于对其输入端接入的信号进行反相，得到反相后的信号，通过该反相器的输出端输出反相后的信号。

Description

驱动电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张申请日为2023年3月29日，申请号为PCT/CN2023/084683的PCT国际申请的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法和显示装置。
背景技术
多数情况下，现有的OLED(有机发光二极管)像素驱动方式为：每一帧都完成一次复位、写入数据和发光阶段，全屏保持一个刷新频率。但是随着时代和科技的进步，同一显示器使用不同驱动频率成为可能，低频区域在保持帧时有些信号可以不重复复位，也不需要写入数据电压信号，所以通过控制这些信号的源极控制电路，关闭电路里的某些TFT(薄膜晶体管)，可以达到节省功耗的目的，上述技术为局部刷新。在相关技术中，提供驱动信号的驱动电路的输出稳定性低。
发明内容
在一个方面中，本公开实施例提供一种驱动电路，包括输出电路和反相电路；
所述输出电路分别与输出控制端、开关控制端、数据线和驱动输出端电连接，用于在所述开关控制端提供的开关控制信号和所述输出控制端提供的输出控制信号的控制下，根据所述数据线提供的数据电压，通过所述驱动输出端提供驱动输出信号；
所述反相电路包括N级反相器；N为正整数；n为小于或等于N的正整数；
第一反相器的输入端与所述驱动输出端电连接，第N反相器的输出端与驱动信号输出端电连接；
当N大于1时，第m反相器的输出端与第m+1反相器的输入端电连接，m小于N的正整数；
所述反相器用于对其输入端接入的信号进行反相，得到反相后的信号，通过该反相器的输出端输出所述反相后的信号。
可选的，所述输出电路包括第一数据写入电路、差分控制电路、输入控制电路和输出控制电路；
所述第一数据写入电路分别与开关控制端、第一数据线和第一差分控制节点电连接，用于在所述开关控制端提供的开关控制信号的控制下，将所述第一数据线提供的第一数据电压写入所述第一差分控制节点，并维持所述第一差分控制节点的电位；
所述差分控制电路分别与第一差分控制节点、第二差分控制节点、输入节点、第一输 出节点和第二输出节点电连接，用于在所述第一差分控制节点的电位和所述第二差分控制节点的电位的控制下，根据所述输入节点的电位，控制所述第一输出节点的电位和第二输出节点的电位；
所述输入控制电路分别与所述输出控制端、所述输入节点和第一电压端电连接，用于在所述输出控制端提供的输出控制信号的控制下，控制所述输入节点与所述第一电压端之间连通或断开；
所述输出控制电路分别与所述输出控制端、第一输出节点、第二输出节点和驱动输出端电连接，用于在所述输出控制信号的控制下，根据所述第一输出节点的电位和所述第二输出节点的电位，生成并通过所述所述驱动输出端提供驱动输出信号。
可选的，所述输出控制电路包括锁存电路和置位电路；
所述置位电路分别与输出控制端、中间节点、驱动输出端和第二电压端电连接，用于在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通或断开，控制所述驱动输出端与所述第二电压端之间连通或断开；
所述锁存电路分别与所述第一输出节点、第二输出节点、所述中间节点、所述驱动输出端和第二电压端电连接，用于在所述中间节点的电位的控制下，根据第一输出节点的电位和所述第二输出节点的电位，控制所述驱动输出端的电位。
可选的，所述输出电路还包括第二数据写入电路；
所述第二数据写入电路分别与开关控制端、第二数据线和所述第二差分控制节点电连接，用于在所述开关控制端提供的开关控制信号的控制下，将所述第二数据线提供的第二数据电压写入所述第二差分控制节点，并维持所述第二差分控制节点的电位。
可选的，本公开至少一实施例所述的驱动电路还包括开关控制电路；
所述开关控制电路分别与通断控制端、第一输出控制节点和第二输出控制节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间连通或断开；
所述第一输出控制节点与所述驱动输出端电连接，所述第二输出控制节点与所述第一反相器的输入端电连接；或者，
所述第一输出控制节点与所述第N反相器的输出端电连接，所述第二输出控制节点与所述驱动信号输出端电连接；或者，
N大于1，所述第一输出控制节点与所述第m反相器的输出端电连接，所述第二输出控制节点与所述第m+1反相器的输入端电连接。
可选的，所述锁存电路用于在所述中间节点的电位的控制下，控制所述第二输出节点与所述驱动输出端之间连通或断开，控制所述驱动输出端与所述第二电压端之间连通或断开，在所述驱动输出端的电位的控制下，控制所述第一输出节点与所述中间节点之间连通或断开，控制所述中间节点与所述第二电压端之间连通或断开。
可选的，一帧时间包括消隐时间段；所述消隐时间段包括关断阶段，所述关断阶段包 括置位时间段；
所述置位电路用于在所述置位时间段，在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通，控制所述驱动输出端与所述第二电压端之间连通；
所述开关控制电路用于在关断阶段，在所述通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间断开。
可选的，N等于1；所述反相电路包括第一反相器，所述第一反相器包括第一晶体管和第二晶体管；
所述第一晶体管的栅极与所述第一反相器的输入端电连接，所述第一晶体管的第一极与第一电压端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极都与所述驱动信号输出端电连接；
所述第二晶体管的栅极与所述第一反相器的输入端电连接，所述第二晶体管的第二极与第二电压端电连接；
所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管。
可选的，N等于2；所述反相电路包括第一反相器和第二反相器；所述第一反相器包括第一晶体管和第二晶体管；所述第二反相器包括第三晶体管和第四晶体管；
所述第一晶体管的栅极与所述第一反相器的输入端电连接，所述第一晶体管的第一极与第一电压端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极都与所述第二反相器的输入端电连接；
所述第二晶体管的栅极与所述第一反相器的输入端电连接，所述第二晶体管的第二极与第二电压端电连接；
所述第三晶体管的栅极和所述第四晶体管的栅极都与所述第二反相器的输入端电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极和所述第四晶体管的第一极都与所述驱动信号输出端电连接；
所述第四晶体管的第二极与所述第二电压端电连接；
所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管；所述第三晶体管为p型晶体管，所述第四晶体管为n型晶体管。
可选的，所述第一数据写入电路包括第五晶体管和第一电容；
所述第五晶体管的栅极与所述开关控制端电连接，所述第五晶体管的第一极与所述第一数据线电连接，所述第五晶体管的第二极与所述第一差分控制节点电连接；
所述第一电容的第一端与所述第一差分控制节点电连接，所述第一电容的第二端与第二电压端电连接。
可选的，所述第二数据写入电路包括第六晶体管和第二电容；所述第六晶体管的栅极与所述开关控制端电连接，所述第六晶体管的第一极与所述第二数据线电连接，所述第六晶体管的第二极与所述第二差分控制节点电连接；
所述第二电容的第一端与所述第二差分控制节点电连接，所述第二电容的第二端与第 二电压端电连接。
可选的，所述开关控制电路包括第七晶体管；
所述第七晶体管的栅极与所述通断控制端电连接，所述第七晶体管的第一极与所述第一输出控制节点电连接，所述第七晶体管的第二极与所述第二输出控制节点电连接。
可选的，所述输入控制电路包括第八晶体管，所述差分控制电路包括第九晶体管和第十晶体管；
所述第八晶体管的栅极与所述输出控制端电连接，所述第八晶体管的第一极与所述第一电压端电连接，所述第八晶体管的第二极与所述输入节点电连接；
所述第九晶体管的栅极与所述第一差分控制节点电连接，所述第九晶体管的第一极与所述输入节点电连接，所述第九晶体管的第二极与所述第一输出节点电连接；
所述第十晶体管的栅极与所述第二差分控制节点电连接，所述第十晶体管的第一极与所述输入节点电连接，所述第十晶体管的第二极与所述第二输出节点电连接。
可选的，所述置位电路包括第十一晶体管和第十二晶体管；
所述第十一晶体管的栅极与所述输出控制端电连接，所述第十一晶体管的第一极与所述中间节点电连接，所述第十一晶体管的第二极与所述第二电压端电连接；
所述第十二晶体管的栅极与所述输出控制端电连接，所述第十二晶体管的第一极与所述驱动输出端电连接，所述第十二晶体管的第二极与所述第二电压端电连接。
可选的，所述第八晶体管为p型晶体管，所述第十一晶体管和所述第十二晶体管为n型晶体管；或者，所述第八晶体管为n型晶体管，所述第十一晶体管和所述第十二晶体管为p型晶体管。
可选的，所述锁存电路包括第十三晶体管、第十四晶体管、第十五晶体管和第十六晶体管；
所述第十三晶体管的栅极与所述驱动输出端电连接，所述第十三晶体管的第一极与所述中间节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
所述第十四晶体管的栅极与中间节点电连接，所述第十四晶体管的第一极与所述驱动输出端电连接，所述第十四晶体管的第二极与所述第二电压端电连接；
所述第十五晶体管的栅极与所述驱动输出端电连接，所述第十五晶体管的第一极与所述第一输出节点电连接，所述第十五晶体管的第二极与所述中间节点电连接；
所述第十六晶体管的栅极与所述中间节点电连接，所述第十六晶体管的第一极与所述第二输出节点电连接，所述第十六晶体管的第二极与所述驱动输出端电连接。
可选的，所述第十三晶体管和所述第十四晶体管为n型晶体管，所述第十五晶体管和所述第十六晶体管为p型晶体管。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的驱动电路，所述驱动方法包括：
输出电路在开关控制信号和输出控制信号的控制下，根据数据电压，通过驱动输出端 提供驱动输出信号；
反相电路包括的反相器对其输入端接入的信号进行反相，得到反相后的信号，通过该反相器的输出端输出所述反相后的信号。
可选的，所述输出电路包括第一数据写入电路、差分控制电路、输入控制电路和输出控制电路；所述输出控制电路包括锁存电路和置位电路；一帧时间包括消隐时间段；所述消隐时间段包括置位时间段和输出阶段；所述置位时间段包括复位阶段、数据写入阶段和电位维持阶段；所述驱动方法包括：
在复位阶段，所述置位电路在输出控制信号的控制下，控制中间节点与第二电压端之间连通，控制驱动输出端与所述第二电压端之间连通；
在数据写入阶段，所述第一数据写入电路在开关控制信号的控制下，将第一数据线提供的第一数据电压写入第一差分控制节点；
在电位维持阶段，所述第一数据写入电路维持所述第一差分控制节点的电位；
在输出阶段，所述输入控制电路在输出控制信号的控制下，控制输入节点与第一电压端之间连通；所述差分控制电路在第一差分控制节点的电位和第二差分控制节点的电位的控制下，根据输入节点的电位，控制第一输出节点的电位和第二输出节点的电位；所述锁存电路在所述中间节点的电位的控制下，根据第一输出节点的电位和所述第二输出节点的电位，控制所述驱动输出端的电位。
可选的，所述输出电路还包括第二数据写入电路；所述驱动方法还包括：
在数据写入阶段，所述第二数据写入电路在开关控制信号的控制下，将第二数据线提供的第二数据电压写入第二差分控制节点；
在电位维持阶段，所述第二数据写入电路维持所述第二差分控制节点的电位。
可选的，所述驱动电路还包括开关控制电路；所述消隐时间段包括关断阶段，所述关断阶段包括所述置位时间段；所述驱动方法还包括：
在所述关断阶段，开关控制电路在通断控制信号的控制下，控制第一输出控制节点与第二输出控制节点之间断开。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的驱动电路。
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图1是本公开至少一实施例所述的驱动电路的结构图；
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图3是本公开至少一实施例所述的驱动电路的结构图；
图4是本公开至少一实施例所述的驱动电路的结构图；
图5是本公开至少一实施例所述的驱动电路的结构图；
图6是本公开至少一实施例所述的驱动电路的结构图；
图7A是本公开至少一实施例所述的驱动电路的结构图；
图7B是本公开至少一实施例所述的驱动电路的结构图；
图8A是本公开至少一实施例所述的驱动电路的结构图；
图8B是本公开至少一实施例所述的驱动电路的结构图；
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图9B是本公开至少一实施例所述的驱动电路的结构图；
图10A是本公开至少一实施例所述的驱动电路的结构图；
图10B是本公开至少一实施例所述的驱动电路的结构图；
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图11B是本公开至少一实施例所述的驱动电路的结构图；
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图12B是本公开至少一实施例所述的驱动电路的结构图；
图13A是本公开至少一实施例所述的驱动电路的结构图；
图13B是本公开至少一实施例所述的驱动电路的结构图；
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图15B是本公开至少一实施例所述的驱动电路的结构图；
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图16B是本公开至少一实施例所述的驱动电路的结构图；
图17是本公开至少一实施例所述的驱动电路的结构图；
图18是本公开至少一实施例所述的驱动电路的结构图；
图19是本公开至少一实施例所述的驱动电路的结构图；
图20是本公开至少一实施例所述的驱动电路的结构图；
图21A是本公开至少一实施例所述的驱动电路的电路图；
图21B是图21A所示的驱动电路的至少一实施例的工作时序图；
图21C是图21A所示的驱动电路的至少一实施例的工作时序图；
图21D是像素电路的至少一实施例的电路图；
图22A是本公开至少一实施例所述的驱动电路的电路图；
图22B是图22A所示的驱动电路的至少一实施例的工作时序图；
图22C是图22A所示的驱动电路的至少一实施例的工作时序图；
图22D是各行发光控制线提供的发光控制信号的波形图；
图23A是本公开至少一实施例所述的驱动电路的电路图；
图23B是图23A所示的驱动电路的至少一实施例的工作时序图；
图23C是图23A所示的驱动电路的至少一实施例的工作时序图；
图23D是图23A所示的驱动电路的至少一实施例的工作时序图；
图24是本公开至少一实施例所述的驱动电路的电路图；
图25是本公开至少一实施例所述的驱动电路的电路图；
图26A是本公开至少一实施例所述的驱动电路的电路图；
图26B是图26A所示的驱动电路的至少一实施例的工作时序图；
图27是本公开至少一实施例所述的驱动电路的电路图；
图28是本公开至少一实施例所述的驱动电路的电路图；
图29A是本公开至少一实施例所述的驱动电路的电路图；
图29B是图29A所示的驱动电路的至少一实施例的工作时序图；
图30是本公开至少一实施例所述的驱动电路的电路图；
图31A是本公开至少一实施例所述的驱动电路的电路图；
图31B是图31A所示的驱动电路的至少一实施例的工作时序图；
图32是本公开至少一实施例所述的驱动电路的电路图；
图33是本公开至少一实施例所述的驱动电路的电路图；
图34是本公开至少一实施例所述的驱动电路的电路图；
图35是本公开至少一实施例所述的驱动电路的电路图；
图36是本公开至少一实施例所述的驱动电路的电路图；
图37是本公开至少一实施例所述的驱动电路的电路图；
图38是本公开至少一实施例所述的驱动电路的电路图；
图39是本公开至少一实施例所述的驱动电路的电路图；
图40是本公开至少一实施例所述的驱动电路的电路图；
图41是本公开至少一实施例所述的驱动电路的电路图；
图42是本公开至少一实施例所述的驱动电路的电路图；
图43是本公开至少一实施例所述的驱动电路的电路图；
图44是本公开至少一实施例所述的驱动电路的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的驱动电路包括输出电路和反相电路；
所述输出电路分别与输出控制端、开关控制端、数据线和驱动输出端电连接，用于在所述开关控制端提供的开关控制信号和所述输出控制端提供的输出控制信号的控制下，根据所述数据线提供的数据电压，通过所述驱动输出端提供驱动输出信号；
所述反相电路包括N级反相器；N为正整数；n为小于或等于N的正整数；
第一反相器的输入端与所述驱动输出端电连接，第N反相器的输出端与驱动信号输出端电连接；
当N大于1时，第m反相器的输出端与第m+1反相器的输入端电连接，m小于N的正整数；
所述反相器用于对其输入端接入的信号进行反相，得到反相后的信号，通过该反相器的输出端输出所述反相后的信号。
本公开实施例所述的驱动电路通过采用反相电路，当所述反相电路包括一级反相器时，可以实现局部低刷，当所述反相电路包括两级反相器时，可以稳定所述驱动信号输出端提供的驱动信号。
如图1所示，本公开实施例所述的驱动电路包括输出电路10和反相电路11；
所述输出电路10分别与输出控制端VCT、开关控制端SW、数据线SL和驱动输出端NT电连接，用于在所述开关控制端SW提供的开关控制信号和所述输出控制端VCT提供的输出控制信号的控制下，根据所述数据线SL提供的数据电压，通过所述驱动输出端NT提供驱动输出信号；
所述反相电路包括第一反相器F1；
第一反相器F1的输入端与所述驱动输出端NT电连接，第一反相器F1的输出端与驱动信号输出端OT电连接；
所述第一反相器F1用于对其输入端接入的信号进行反相，得到反相后的信号，通过该第一反相器F1的输出端输出所述反相后的信号。
在图1所示的驱动电路的至少一实施例中，N等于1。
如图2所示，本公开实施例所述的驱动电路包括输出电路10和反相电路11；
所述输出电路10分别与输出控制端VCT、开关控制端SW、数据线SL和驱动输出端NT电连接，用于在所述开关控制端SW提供的开关控制信号和所述输出控制端VCT提供的输出控制信号的控制下，根据所述数据线SL提供的数据电压，通过所述驱动输出端NT提供驱动输出信号；
所述反相电路包括第一反相器F1和第二反相器F2；
第一反相器F1的输入端与所述驱动输出端NT电连接，第一反相器F1的输出端与第二反相器F2的输入端电连接；
第二反相器F2的输出端与驱动信号输出端OT电连接；
所述第一反相器F1用于对其输入端接入的信号进行反相，得到第一反相后的信号， 通过该第一反相器F1的输出端输出所述第一反相后的信号；
所述第二反相器F2用于对其输入端接入的信号进行反相，得到第二反相后的信号，通过该第二反相器F2的输出端输出所述第二反相后的信号。
在图2所示的至少一实施例中，N等于2。
在本公开至少一实施例中，所述输出电路包括第一数据写入电路、差分控制电路、输入控制电路和输出控制电路；
所述第一数据写入电路分别与开关控制端、第一数据线和所述第一差分控制节点电连接，用于在所述开关控制端提供的开关控制信号的控制下，将所述第一数据线提供的第一数据电压写入所述第一差分控制节点，并维持所述第一差分控制节点的电位；
所述差分控制电路分别与第一差分控制节点、第二差分控制节点、输入节点、第一输出节点和第二输出节点电连接，用于在所述第一差分控制节点的电位和所述第二差分控制节点的电位的控制下，根据所述输入节点的电位，控制所述第一输出节点的电位和第二输出节点的电位；
所述输入控制电路分别与所述输出控制端、所述输入节点和第一电压端电连接，用于在所述输出控制端提供的输出控制信号的控制下，控制所述输入节点与所述第一电压端之间连通或断开；
所述输出控制电路分别与所述输出控制端、第一输出节点、第二输出节点和驱动输出端电连接，用于在所述输出控制信号的控制下，根据所述第一输出节点的电位和所述第二输出节点的电位，生成并通过所述所述驱动输出端提供驱动输出信号。
可选的，所述第一电压端可以为高电压端。
如图3所示，在图1所示的驱动电路的至少一实施例的基础上，所述输出电路包括第一数据写入电路31、差分控制电路32、输入控制电路33和输出控制电路34；
所述第一数据写入电路31分别与开关控制端SW、第一数据线SL1和所述第一差分控制节点NC1电连接，用于在所述开关控制端SW提供的开关控制信号的控制下，将所述第一数据线SL1提供的第一数据电压写入所述第一差分控制节点NC1，并维持所述第一差分控制节点NC1的电位；
第二差分控制节点NC2与初始电压端I1电连接，所述初始电压端I1用于提供初始电压Vinit；
所述差分控制电路32分别与第一差分控制节点NC1、第二差分控制节点NC2、输入节点N2、第一输出节点N3和第二输出节点N4电连接，用于在所述第一差分控制节点NC1的电位和所述第二差分控制节点NC2的电位的控制下，根据所述输入节点N2的电位，控制所述第一输出节点N3的电位和第二输出节点N4的电位；
所述输入控制电路33分别与所述输出控制端VCT、所述输入节点N2和第一电压端V1电连接，用于在所述输出控制端VCT提供的输出控制信号的控制下，控制所述输入节点N2与所述第一电压端V1之间连通或断开；
所述输出控制电路34分别与所述输出控制端VCT、第一输出节点N3、第二输出节点N4和驱动输出端NT电连接，用于在所述输出控制信号的控制下，根据所述第一输出节点N3的电位和所述第二输出节点N4的电位，生成并通过所述所述驱动输出端NT提供驱动输出信号。
如图4所示，在图2所示的驱动电路的至少一实施例的基础上，所述输出电路包括第一数据写入电路31、差分控制电路32、输入控制电路33和输出控制电路34；
所述第一数据写入电路31分别与开关控制端SW、第一数据线SL1和所述第一差分控制节点NC1电连接，用于在所述开关控制端SW提供的开关控制信号的控制下，将所述第一数据线SL1提供的第一数据电压写入所述第一差分控制节点NC1，并维持所述第一差分控制节点NC1的电位；
第二差分控制节点NC与初始电压端I1电连接，所述初始电压端I1用于提供初始电压Vinit；
所述差分控制电路32分别与第一差分控制节点NC1、第二差分控制节点NC2、输入节点N2、第一输出节点N3和第二输出节点N4电连接，用于在所述第一差分控制节点NC1的电位和所述第二差分控制节点NC2的电位的控制下，根据所述输入节点N2的电位，控制所述第一输出节点N3的电位和第二输出节点N4的电位；
所述输入控制电路33分别与所述输出控制端VCT、所述输入节点N2和第一电压端V1电连接，用于在所述输出控制端VCT提供的输出控制信号的控制下，控制所述输入节点N2与所述第一电压端V1之间连通或断开；
所述输出控制电路34分别与所述输出控制端VCT、第一输出节点N3、第二输出节点N4和驱动输出端NT电连接，用于在所述输出控制信号的控制下，根据所述第一输出节点N3的电位和所述第二输出节点N4的电位，生成并通过所述所述驱动输出端NT提供驱动输出信号。
在本公开至少一实施例中，所述输出电路还包括第二数据写入电路；
所述第二数据写入电路分别与开关控制端、第二数据线和所述第二差分控制节点电连接，用于在所述开关控制端提供的开关控制信号的控制下，将所述第二数据线提供的第二数据电压写入所述第二差分控制节点，并维持所述第二差分控制节点的电位。
在具体实施时，所述输出电路还可以包括第二数据写入电路，所述第二数据写入电路在开关控制信号的控制下，将第二数据电压写入第二差分控制节点，维持第二差分控制节点的电位。
如图5所示，在图1所示的驱动电路的至少一实施例的基础上，所述输出电路包括第一数据写入电路31、差分控制电路32、输入控制电路33、输出控制电路34和第二数据写入电路35；
所述第一数据写入电路31分别与开关控制端SW、第一数据线SL1和所述第一差分控制节点NC1电连接，用于在所述开关控制端SW提供的开关控制信号的控制下，将所 述第一数据线SL1提供的第一数据电压写入所述第一差分控制节点NC1，并维持所述第一差分控制节点NC1的电位；
所述第二数据写入电路35分别与开关控制端SW、第二数据线SL2和所述第二差分控制节点NC2电连接，用于在所述开关控制端SW提供的开关控制信号的控制下，将所述第二数据线SL2提供的第二数据电压写入所述第二差分控制节点NC2，并维持所述第二差分控制节点NC2的电位；
所述差分控制电路32分别与第一差分控制节点NC1、第二差分控制节点NC2、输入节点N2、第一输出节点N3和第二输出节点N4电连接，用于在所述第一差分控制节点NC1的电位和所述第二差分控制节点NC2的电位的控制下，根据所述输入节点N2的电位，控制所述第一输出节点N3的电位和第二输出节点N4的电位；
所述输入控制电路33分别与所述输出控制端VCT、所述输入节点N2和第一电压端V1电连接，用于在所述输出控制端VCT提供的输出控制信号的控制下，控制所述输入节点N2与所述第一电压端V1之间连通或断开；
所述输出控制电路34分别与所述输出控制端VCT、第一输出节点N3、第二输出节点N4和驱动输出端NT电连接，用于在所述输出控制信号的控制下，根据所述第一输出节点N3的电位和所述第二输出节点N4的电位，生成并通过所述所述驱动输出端NT提供驱动输出信号。
如图6所示，在图2所示的驱动电路的至少一实施例的基础上，所述输出电路包括第一数据写入电路31、差分控制电路32、输入控制电路33、输出控制电路34和第二数据写入电路35；
所述第一数据写入电路31分别与开关控制端SW、第一数据线SL1和所述第一差分控制节点NC1电连接，用于在所述开关控制端SW提供的开关控制信号的控制下，将所述第一数据线SL1提供的第一数据电压写入所述第一差分控制节点NC1，并维持所述第一差分控制节点NC1的电位；
所述第二数据写入电路35分别与开关控制端SW、第二数据线SL2和所述第二差分控制节点NC2电连接，用于在所述开关控制端SW提供的开关控制信号的控制下，将所述第二数据线SL2提供的第二数据电压写入所述第二差分控制节点NC2，并维持所述第二差分控制节点NC2的电位；
所述差分控制电路32分别与第一差分控制节点NC1、第二差分控制节点NC2、输入节点N2、第一输出节点N3和第二输出节点N4电连接，用于在所述第一差分控制节点NC1的电位和所述第二差分控制节点NC2的电位的控制下，根据所述输入节点N2的电位，控制所述第一输出节点N3的电位和第二输出节点N4的电位；
所述输入控制电路33分别与所述输出控制端VCT、所述输入节点N2和第一电压端V1电连接，用于在所述输出控制端VCT提供的输出控制信号的控制下，控制所述输入节点N2与所述第一电压端V1之间连通或断开；
所述输出控制电路34分别与所述输出控制端VCT、第一输出节点N3、第二输出节点N4和驱动输出端NT电连接，用于在所述输出控制信号的控制下，根据所述第一输出节点N3的电位和所述第二输出节点N4的电位，生成并通过所述所述驱动输出端NT提供驱动输出信号。
本公开至少一实施例所述的驱动电路还包括开关控制电路；
所述开关控制电路分别与通断控制端、第一输出控制节点和第二输出控制节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间连通或断开；
所述第一输出控制节点与所述驱动输出端电连接，所述第二输出控制节点与所述第一反相器的输入端电连接；或者，
所述第一输出控制节点与所述第N反相器的输出端电连接，所述第二输出控制节点与所述驱动信号输出端电连接；或者，
N大于1，所述第一输出控制节点与所述第m反相器的输出端电连接，所述第二输出控制节点与所述第m+1反相器的输入端电连接。
在具体实施时，所述驱动电路还可以包括开关控制电路，所述开关控制电路在通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间连通或断开。
如图7A所示，在图3所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述驱动输出端NT和第一反相器F1的输入端电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述驱动输出端NT和第一反相器F1的输入端之间连通或断开。
在图7A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与NT电连接，NS2与所述第一反相器F1的输入端电连接。
如图7B所示，在图5所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述驱动输出端NT和第一反相器F1的输入端电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述驱动输出端NT和第一反相器F1的输入端之间连通或断开。
在图7B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与NT电连接，NS2与所述第一反相器F1的输入端电连接。
如图8A所示，在图3所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述第一反相器F1的输出端和驱动 信号输出端OT电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述第一反相器F1的输出端和驱动信号输出端OT之间连通或断开。
在图8A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与第一反相器F1的输出端电连接，NS2与所述驱动信号输出端OT电连接。
如图8B所示，在图5所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述第一反相器F1的输出端和驱动信号输出端OT电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述第一反相器F1的输出端和驱动信号输出端OT之间连通或断开。
在图8B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与第一反相器F1的输出端电连接，NS2与所述驱动信号输出端OT电连接。
如图9A所示，在图4所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述驱动输出端NT和第一反相器F1的输入端电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述驱动输出端NT和第一反相器F1的输入端之间连通或断开。
在图9A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述驱动输出端NT电连接，NS2与第一反相器F1的输入端电连接。
如图9B所示，在图6所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述驱动输出端NT和第一反相器F1的输入端电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述驱动输出端NT和第一反相器F1的输入端之间连通或断开。
在图9B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述驱动输出端NT电连接，NS2与第一反相器F1的输入端电连接。
如图10A所示，在图4所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述第一反相器F1的输出端和所述第二反相器F2的输入端电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述第一反相器F1的输出端和所述第二反相器F2的输入端之间连通或断开。
在图10A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点， 标号为NS2的为第二输出控制节点；
NS1与所述第一反相器F1的输出端电连接，NS2与所述第二反相器F2的输入端电连接。
如图10B所示，在图6所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述第一反相器F1的输出端和所述第二反相器F2的输入端电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述第一反相器F1的输出端和所述第二反相器F2的输入端之间连通或断开。
在图10B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第一反相器F1的输出端电连接，NS2与所述第二反相器F2的输入端电连接。
如图11A所示，在图4所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述第二反相器F2的输出端和驱动信号输出端OT电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述第二反相器F2的输出端和驱动信号输出端OT之间连通或断开。
在图11A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第二反相器F2的输出端电连接，NS2与所述驱动信号输出端OT电连接。
如图11B所示，在图6所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括开关控制电路70；
所述开关控制电路70分别与通断控制端VCT2、所述第二反相器F2的输出端和驱动信号输出端OT电连接，用于在所述通断控制端VCT2提供的通断控制信号的控制下，控制所述第二反相器F2的输出端和驱动信号输出端OT之间连通或断开。
在图11B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第二反相器F2的输出端电连接，NS2与所述驱动信号输出端OT电连接。
在本公开至少一实施例中，所述输出控制电路包括锁存电路和置位电路；
所述置位电路分别与输出控制端、中间节点、驱动输出端和第二电压端电连接，用于在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通或断开，控制所述驱动输出端与所述第二电压端之间连通或断开；
所述锁存电路分别与所述第一输出节点、第二输出节点、所述中间节点、所述驱动输出端和第二电压端电连接，用于在所述中间节点的电位的控制下，根据第一输出节点的电位和所述第二输出节点的电位，控制所述驱动输出端的电位。
在具体实施时，所述输出控制电路可以包括锁存电路和置位电路，所述置位电路在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通或断开，控制所述驱动输出端与所述第二电压端之间连通或断开；所述锁存电路在所述中间节点的电位的控制下，根据第一输出节点的电位和所述第二输出节点的电位，控制所述驱动输出端的电位。
在本公开至少一实施例中，所述锁存电路用于在所述中间节点的电位的控制下，控制所述第二输出节点与所述驱动输出端之间连通或断开，控制所述驱动输出端与所述第二电压端之间连通或断开，在所述驱动输出端的电位的控制下，控制所述第一输出节点与所述中间节点之间连通或断开，控制所述中间节点与所述第二电压端之间连通或断开。
可选的，所述第二电压端可以为低电压端。
如图12A所示，在图7A所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图12A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述驱动输出端NT电连接，NS2与所述第一反相器F1的输入端电连接。
如图12B所示，在图7B所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图12B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述驱动输出端NT电连接，NS2与所述第一反相器F1的输入端电连接。
如图13A所示，在图8A所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图13A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第一反相器F1的输出端电连接，NS2与所述驱动信号输出端OT电连接。
如图13B所示，在图8B所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图13B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第一反相器F1的输出端电连接，NS2与所述驱动信号输出端OT电连接。
如图14A所示，在图9A所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下， 根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图14A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述驱动输出端NT电连接，NS2与所述第一反相器F1的输入端电连接。
如图14B所示，在图9B所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图14B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述驱动输出端NT电连接，NS2与所述第一反相器F1的输入端电连接。
如图15A所示，在图10A所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图15A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第一反相器F1的输出端电连接，NS2与所述第二反相器F2的输入端电连接。
如图15B所示，在图10B所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压 端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图15B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第一反相器F1的输出端电连接，NS2与所述第二反相器F2的输入端电连接。
如图16A所示，在图11A所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图16A所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点，标号为NS2的为第二输出控制节点；
NS1与所述第二反相器F2的输出端电连接，NS2与所述驱动信号输出端OT电连接。
如图16B所示，在图11B所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
在图16B所示的驱动电路的至少一实施例中，标号为NS1的为第一输出控制节点， 标号为NS2的为第二输出控制节点；
NS1与所述第二反相器F2的输出端电连接，NS2与所述驱动信号输出端OT电连接。
在本公开至少一实施例中，一帧时间包括消隐时间段；所述消隐时间段包括关断阶段，所述关断阶段包括置位时间段；
所述置位电路用于在所述置位时间段，在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通，控制所述驱动输出端与所述第二电压端之间连通；
所述开关控制电路用于在关断阶段，在所述通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间断开。
在具体实施时，一帧时间包括消隐时间段，所述消隐时间段包括关断阶段，所述关断阶段包括置位时间段，在置位时间段，所述置位电路在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通，控制所述驱动输出端与所述第二电压端之间连通，在关断阶段，所述开关控制电路在所述通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间断开，以使得在消隐时间段，所述驱动信号输出端提供的驱动信号，不受所述驱动输出端提供的驱动输出信号的上升沿和下降沿的影响。
如图17所示，在图3所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
如图18所示，在图4所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
如图19所示，在图5所示的驱动电路的至少一实施例的基础上，在本公开至少一实 施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
如图20所示，在图6所示的驱动电路的至少一实施例的基础上，在本公开至少一实施例中，所述输出控制电路包括锁存电路41和置位电路42；
所述置位电路42分别与输出控制端VCT、中间节点N6、驱动输出端NT和第二电压端V2电连接，用于在所述输出控制信号的控制下，控制所述中间节点N6与所述第二电压端V2之间连通或断开，控制所述驱动输出端NT与所述第二电压端V2之间连通或断开；
所述锁存电路41分别与所述第一输出节点N3、第二输出节点N4、所述中间节点N6、所述驱动输出端NT和第二电压端V2电连接，用于在所述中间节点N6的电位的控制下，根据第一输出节点N3的电位和所述第二输出节点N4的电位，控制所述驱动输出端NT的电位。
可选的，N等于1；所述反相电路包括第一反相器，所述第一反相器包括第一晶体管和第二晶体管；
所述第一晶体管的栅极与所述第一反相器的输入端电连接，所述第一晶体管的第一极与第一电压端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极都与所述驱动信号输出端电连接；
所述第二晶体管的栅极与所述第一反相器的输入端电连接，所述第二晶体管的第二极与第二电压端电连接；
所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管。
可选的，N等于2；所述反相电路包括第一反相器和第二反相器；所述第一反相器包括第一晶体管和第二晶体管；所述第二反相器包括第三晶体管和第四晶体管；
所述第一晶体管的栅极与所述第一反相器的输入端电连接，所述第一晶体管的第一极与第一电压端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极都与所述第二反相器的输入端电连接；
所述第二晶体管的栅极与所述第一反相器的输入端电连接，所述第二晶体管的第二极与第二电压端电连接；
所述第三晶体管的栅极和所述第四晶体管的栅极都与所述第二反相器的输入端电连 接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极和所述第四晶体管的第一极都与所述驱动信号输出端电连接；
所述第四晶体管的第二极与所述第二电压端电连接；
所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管；所述第三晶体管为p型晶体管，所述第四晶体管为n型晶体管。
可选的，所述第一数据写入电路包括第五晶体管和第一电容；
所述第五晶体管的栅极与所述开关控制端电连接，所述第五晶体管的第一极与所述第一数据线电连接，所述第五晶体管的第二极与所述第一差分控制节点电连接；
所述第一电容的第一端与所述第一差分控制节点电连接，所述第一电容的第二端与第二电压端电连接。
可选的，所述第二数据写入电路包括第六晶体管和第二电容；所述第六晶体管的栅极与所述开关控制端电连接，所述第六晶体管的第一极与所述第二数据线电连接，所述第六晶体管的第二极与所述第二差分控制节点电连接；
所述第二电容的第一端与所述第二差分控制节点电连接，所述第二电容的第二端与第二电压端电连接。
可选的，所述开关控制电路包括第七晶体管；
所述第七晶体管的栅极与所述通断控制端电连接，所述第七晶体管的第一极与所述第一输出控制节点电连接，所述第七晶体管的第二极与所述第二输出控制节点电连接。
在本公开至少一实施例中，所述第一输出控制节点与所述驱动输出端电连接，所述第二输出控制节点与所述第一反相器的输入端电连接；或者，
所述第一输出控制节点与所述第N反相器的输出端电连接，所述第二输出控制节点与所述驱动信号输出端电连接；或者，
N大于1，所述第一输出控制节点与所述第m反相器的输出端电连接，所述第二输出控制节点与所述第m+1反相器的输入端电连接。
可选的，所述输入控制电路包括第八晶体管，所述差分控制电路包括第九晶体管和第十晶体管；
所述第八晶体管的栅极与所述输出控制端电连接，所述第八晶体管的第一极与所述第一电压端电连接，所述第八晶体管的第二极与所述输入节点电连接；
所述第九晶体管的栅极与所述第一差分控制节点电连接，所述第九晶体管的第一极与所述输入节点电连接，所述第九晶体管的第二极与所述第一输出节点电连接；
所述第十晶体管的栅极与所述第二差分控制节点电连接，所述第十晶体管的第一极与所述输入节点电连接，所述第十晶体管的第二极与所述第二输出节点电连接。
可选的，所述置位电路包括第十一晶体管和第十二晶体管；
所述第十一晶体管的栅极与所述输出控制端电连接，所述第十一晶体管的第一极与所述中间节点电连接，所述第十一晶体管的第二极与所述第二电压端电连接；
所述第十二晶体管的栅极与所述输出控制端电连接，所述第十二晶体管的第一极与所述驱动输出端电连接，所述第十二晶体管的第二极与所述第二电压端电连接。
可选的，所述第八晶体管为p型晶体管，所述第十一晶体管和所述第十二晶体管为n型晶体管；或者，所述第八晶体管为n型晶体管，所述第十一晶体管和所述第十二晶体管为p型晶体管。
可选的，所述锁存电路包括第十三晶体管、第十四晶体管、第十五晶体管和第十六晶体管；
所述第十三晶体管的栅极与所述驱动输出端电连接，所述第十三晶体管的第一极与所述中间节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
所述第十四晶体管的栅极与中间节点电连接，所述第十四晶体管的第一极与所述驱动输出端电连接，所述第十四晶体管的第二极与所述第二电压端电连接；
所述第十五晶体管的栅极与所述驱动输出端电连接，所述第十五晶体管的第一极与所述第一输出节点电连接，所述第十五晶体管的第二极与所述中间节点电连接；
所述第十六晶体管的栅极与所述中间节点电连接，所述第十六晶体管的第一极与所述第二输出节点电连接，所述第十六晶体管的第二极与所述驱动输出端电连接。
可选的，所述第十三晶体管和所述第十四晶体管为n型晶体管，所述第十五晶体管和所述第十六晶体管为p型晶体管。
如图21A所示，在图17所示的像素电路的至少一实施例的基础上，
所述第一反相器包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与所述第一反相器的输入端电连接，所述第一晶体管T1的源极与高电压端VGH电连接，所述第一晶体管T1的漏极与所述第二晶体管T2的源极都与所述驱动信号输出端OT电连接；
所述第二晶体管T2的栅极与所述第一反相器的输入端电连接，所述第二晶体管T2的漏极与低电压端VGL电连接；
所述第一反相器的输入端与驱动输出端NT电连接；
所述第一晶体管T1为p型晶体管，所述第二晶体管T2为n型晶体管；
所述第一数据写入电路包括第五晶体管T5和第一电容C1；
所述第五晶体管T5的栅极与所述开关控制端SW电连接，所述第五晶体管T5的源极与所述第一数据线SL1电连接，所述第五晶体管T5的漏极与所述第一差分控制节点NC1电连接；
所述第一电容C1的第一端与所述第一差分控制节点NC1电连接，所述第一电容C1的第二端与低电压端VGL电连接；
所述输入控制电路包括第八晶体管T8，所述差分控制电路包括第九晶体管T9和第十晶体管T10；
所述第八晶体管T8的栅极与所述输出控制端VCT电连接，所述第八晶体管T8的源 极与所述高电压端VGH电连接，所述第八晶体管T8的漏极与所述输入节点N2电连接；
所述第九晶体管T9的栅极与所述第一差分控制节点NC1电连接，所述第九晶体管T9的源极与所述输入节点N2电连接，所述第九晶体管T9的漏极与所述第一输出节点N3电连接；
所述第十晶体管T10的栅极与所述第二差分控制节点NC2电连接，所述第十晶体管T10的源极与所述输入节点N2电连接，所述第十晶体管T10的漏极与所述第二输出节点N4电连接；所述第二差分控制节点NC2与初始电压端I1电连接；
所述置位电路包括第十一晶体管T11和第十二晶体管T12；
所述第十一晶体管T11的栅极与所述输出控制端VCT电连接，所述第十一晶体管T11的源极与所述中间节点N6电连接，所述第十一晶体管T11的源极与所述低电压端VGL电连接；
所述第十二晶体管T12的栅极与所述输出控制端VCT电连接，所述第十二晶体管T12的源极与所述驱动输出端NT电连接，所述第十二晶体管T12的漏极与所述低电压端VGL电连接；
所述第八晶体管T8为p型晶体管，所述第十一晶体管T11和所述第十二晶体管T12为n型晶体管；
所述锁存电路包括第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第十六晶体管T16；
所述第十三晶体管T13的栅极与所述驱动输出端NT电连接，所述第十三晶体管T13的源极与所述中间节点N6电连接，所述第十三晶体管T13的漏极与低电压端VGL电连接；
所述第十四晶体管T14的栅极与中间节点N6电连接，所述第十四晶体管T14的源极与所述驱动输出端NT电连接，所述第十四晶体管T14的漏极与所述低电压端VGL电连接；
所述第十五晶体管T15的栅极与所述驱动输出端NT电连接，所述第十五晶体管T15的源极与所述第一输出节点N3电连接，所述第十五晶体管T15的漏极与所述中间节点N6电连接；
所述第十六晶体管T16的栅极与所述中间节点N6电连接，所述第十六晶体管T16的源极与所述第二输出节点N4电连接，所述第十六晶体管T16的漏极与所述驱动输出端NT电连接；
所述第十三晶体管T13和所述第十四晶体管T14为n型晶体管，所述第十五晶体管T15和所述第十六晶体管T16为p型晶体管。
在本公开至少一实施例中，第二电压端可以为低电压端，但不以此为限。
在图21A所示的驱动电路的至少一实施例中，T1、T8、T9、T10、T15和T16都为p型晶体管，T2、T5、T11、T12、T13和T14都为n型晶体管。
图21B是图21A所示的驱动电路的至少一实施例的工作时序图。
在图21B中，标号为F1的为一帧时间，标号为SX的为消隐时间段，消隐时间段SX设置于一帧时间F1的最开始的时间段，标号为SD的为一帧时间F1包括的显示时间段。
图21C是图21B中的消隐时间段SX的放大后的时序图。
如图21C所示，本公开图21A所示的驱动电路的至少一实施例在工作时，消隐时间段包括先后设置的第一时间段ST1、第二时间段ST2、第三时间段ST3和第四时间段ST4；
在第一时间段ST1、第二时间段ST2和第三时间段ST3，VCT提供高电压信号，T11和T12打开，N6的电位为低电压，NT与VGL之间连通，T15和T16都打开，N3和N4都与VGL之间连通，T1和T2形成的第一反相器对NT提供的驱动输出信号进行反相，OT输出高电压信号；
在第一时间段ST1，SW提供低电压信号，T5关断；
在第二时间段ST2，SW提供高电压信号，VCT提供高电压信号，T5打开，将SL1提供的第一数据电压写入NC1，由于T5是IGZO(铟镓锌氧化物)TFT(薄膜晶体管)，将第一数据电压写入NC1需要一定时间；
在第三时间段ST3，SW提供低电压信号，VCT提供高电压信号，T5关闭，第一数据电压写入NC1的时间到，不再对NC1充电，通过C1维持NC1的电位；
在第四时间段ST4，VCT提供低电压信号，T11和T12关断，T8打开，VGH通过T8持续写入N2，I1提供初始电压Vinit，由于NC1的电位与Vinit的电压值之间存在电压差，导致N3的电位与N4的电位有差异；
在第四时间段ST4，NC1的电位大于Vinit的电压值，N3的电位小于N4的电位；在第四时间段ST4开始时，T15和T16打开，N6的电位小于NT的电位，T16打开，NT输出高电压信号，OT输出低电压信号。
本公开图21A所示的驱动电路的至少一实施例在工作时，在第四时间段ST4，当NC1的电位小于Vinit的电压值时，N3的电位大于N4的电位，在第四时间段ST4开始时，T15和T16打开，N6的电位大于NT的电位，T14打开，NT输出低电压信号，OT输出高电压信号。
本公开图21A所示的驱动电路的至少一实施例在工作时，在显示时间段，OT输出的驱动信号与在第四时间段ST4，OT输出的驱动信号相同；在第四时间段ST4和显示时间段SD，OT都输出低电压信号；或者，在第四时间段ST4和显示时间段SD，OT都输出高电压信号。
在图21A所示的驱动电路的至少一实施例中，T13、T14、T15和T16组成锁存器，T9和T10组成差分部分。
本公开至少一实施例所述的驱动电路可以通过驱动信号输出端OT为图21D所示的像素电路中的第一控制晶体管M9的栅极提供驱动信号；
如图21D所示，像素电路的至少一实施例可以包括驱动晶体管M3、第一初始化晶体 管M1、补偿控制晶体管M2、数据写入晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6、第二初始化晶体管M7、第三初始化晶体管M8、第一控制晶体管M9、存储电容Cst和有机发光二极管O1；
M5的栅极与发光控制线EM电连接，M5的源极与电源电压端VDD电连接，M5的漏极与M3的源极电连接；
M9的栅极与第一控制端S0电连接，M9的漏极与M3的栅极电连接，M9的源极与M2的漏极电连接，M2的源极与M3的漏极电连接；
M1的栅极与第一复位控制端RP电连接，M1的源极与第一初始电压端I01电连接，M1的漏极与M3的漏极电连接；
M2的栅极与补偿控制端GN电连接；
M4的栅极与扫描端GP电连接，M4的源极与数据线DL电连接，M4的漏极与M3的源极电连接；
M6的栅极与发光控制线EM电连接，M6的源极与M3的漏极电连接，M6的漏极与O1的阳极电连接；O1的阴极与低电平端VSS电连接；
M7的栅极与第二复位控制端RH电连接，M7的源极与第二初始电压端I02电连接，M7的漏极与O1的阳极电连接；
M8的栅极与第二复位控制端RH电连接，M8的源极与第三初始电压端I03电连接，M8的漏极与M3的源极电连接；
Cst的第一端与M3的栅极电连接，Cst的第二端与电源电压端VDD电连接。
在图21D所示的像素电路的至少一实施例中，M2和M9为氧化物晶体管，M2和M9为n型晶体管，其他晶体管都为p型晶体管。
图21D所示的像素电路的至少一实施例在工作时，在一帧时间包括的显示时间段，当OT输出高电压信号时，M9打开，正常对所述像素电路进行刷新；在所述显示时间段，当OT输出低电压信号时，M9关断，不对所述像素电路进行刷新。
如图22A所示，在图18所示的像素电路的至少一实施例的基础上，
所述反相电路包括第一反相器和第二反相器；所述第一反相器包括第一晶体管T1和第二晶体管T2；所述第二反相器包括第三晶体管T3和第四晶体管T4；
所述第一晶体管T1的栅极与所述第一反相器的输入端电连接，所述第一晶体管T1的源极与高电压端VGH电连接，所述第一晶体管T1的漏极与所述第二晶体管T2的源极都与所述第二反相器的输入端电连接；
所述第二晶体管T2的栅极与所述第一反相器的输入端电连接，所述第二晶体管T2的漏极与低电压端电连接；
所述第三晶体管T3的栅极和所述第四晶体管T4的栅极都与所述第二反相器的输入端电连接，所述第三晶体管T3的源极与所述高电压端VGH电连接，所述第三晶体管T3的漏极和所述第四晶体管T4的源极都与所述驱动信号输出端OT电连接；
所述第四晶体管T4的漏极与所述低电压端VGL电连接；
所述第一晶体管T1为p型晶体管，所述第二晶体管T2为n型晶体管；所述第三晶体管T3为p型晶体管，所述第四晶体管T4为n型晶体管；
所述第一反相器的输入端与驱动输出端NT电连接；
所述第一数据写入电路包括第五晶体管T5和第一电容C1；
所述第五晶体管T5的栅极与所述开关控制端SW电连接，所述第五晶体管T5的源极与所述第一数据线SL1电连接，所述第五晶体管T5的漏极与所述第一差分控制节点NC1电连接；
所述第一电容C1的第一端与所述第一差分控制节点NC1电连接，所述第一电容C1的第二端与低电压端VGL电连接；
所述输入控制电路包括第八晶体管T8，所述差分控制电路包括第九晶体管T9和第十晶体管T10；
所述第八晶体管T8的栅极与所述输出控制端VCT电连接，所述第八晶体管T8的源极与所述高电压端VGH电连接，所述第八晶体管T8的漏极与所述输入节点N2电连接；
所述第九晶体管T9的栅极与所述第一差分控制节点NC1电连接，所述第九晶体管T9的源极与所述输入节点N2电连接，所述第九晶体管T9的漏极与所述第一输出节点N3电连接；
所述第十晶体管T10的栅极与所述第二差分控制节点NC2电连接，所述第十晶体管T10的源极与所述输入节点N2电连接，所述第十晶体管T10的漏极与所述第二输出节点N4电连接；所述第二差分控制节点NC2与初始电压端I1电连接；
所述置位电路包括第十一晶体管T11和第十二晶体管T12；
所述第十一晶体管T11的栅极与所述输出控制端VCT电连接，所述第十一晶体管T11的源极与所述中间节点N6电连接，所述第十一晶体管T11的源极与所述低电压端VGL电连接；
所述第十二晶体管T12的栅极与所述输出控制端VCT电连接，所述第十二晶体管T12的源极与所述驱动输出端NT电连接，所述第十二晶体管T12的漏极与所述低电压端VGL电连接；
所述第八晶体管T8为p型晶体管，所述第十一晶体管T11和所述第十二晶体管T12为n型晶体管；
所述锁存电路包括第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第十六晶体管T16；
所述第十三晶体管T13的栅极与所述驱动输出端NT电连接，所述第十三晶体管T13的源极与所述中间节点N6电连接，所述第十三晶体管T13的漏极与低电压端VGL电连接；
所述第十四晶体管T14的栅极与中间节点N6电连接，所述第十四晶体管T14的源极 与所述驱动输出端NT电连接，所述第十四晶体管T14的漏极与所述低电压端VGL电连接；
所述第十五晶体管T15的栅极与所述驱动输出端NT电连接，所述第十五晶体管T15的源极与所述第一输出节点N3电连接，所述第十五晶体管T15的漏极与所述中间节点N6电连接；
所述第十六晶体管T16的栅极与所述中间节点N6电连接，所述第十六晶体管T16的源极与所述第二输出节点N4电连接，所述第十六晶体管T16的漏极与所述驱动输出端OT电连接；
所述第十三晶体管T13和所述第十四晶体管T14为n型晶体管，所述第十五晶体管T15和所述第十六晶体管T16为p型晶体管。
在图22A所示的至少一实施例中，T1、T3、T8、T9、T10、T15和T16都为p型晶体管，T2、T4、T5、T11、T12、T13和T14都为n型晶体管。
在图22A所示的驱动电路的至少一实施例中，T1和T2组成第一反相器，T3和T4组成第二反相器，T1、T2、T3和T4可以用于对所述驱动输出信号进行放大和稳定，输出驱动信号。
图22B是图22A所示的驱动电路的至少一实施例的工作时序图。
在图22B中，标号为F1的为一帧时间，标号为SX的为消隐时间段，消隐时间段SX设置于一帧时间F1的最开始的时间段，标号为SD的为一帧时间F1包括的显示时间段。
如图22C所示，本公开图22A所示的驱动电路的至少一实施例在工作时，消隐时间段包括先后设置的第一时间段ST1、第二时间段ST2、第三时间段ST3和第四时间段ST4；
在第一时间段ST1、第二时间段ST2和第三时间段ST3，VCT提供高电压信号，T11和T12打开，NT输出低电压信号，经过两级反相器后，OT输出低电压信号；
在第一时间段ST1，SW提供低电压信号，T5关断；
在第二时间段ST2，SW提供高电压信号，VCT提供高电压信号，T5打开，将SL1提供的第一数据电压写入NC1，由于T5是IGZO TFT(薄膜晶体管)，将第一数据电压写入NC1需要一定时间；
在第三时间段ST3，SW提供低电压信号，VCT提供高电压信号，T5关闭，第一数据电压写入NC1的时间到，不再对NC1充电，通过C1维持NC1的电位；
在第四时间段ST4，VCT提供低电压信号，T11和T12关断，T8打开，VGH通过T8持续写入N2，I1提供初始电压Vinit，由于NC1的电位与Vinit的电压值之间存在电压差，T9的栅极电位与T10的栅极电位之间存在差异，导致第一输出节点N3和第二输出节点N4的电压写入速度或电压值有差异；
在第四时间段ST4，NC1的电位大于Vinit的电压值，N3的电位小于N4的电位；在第四时间段ST4开始时，T15和T16打开，N6的电位小于NT的电位，T16打开，NT输出高电压信号，OT输出高电压信号。
本公开图22A所示的驱动电路的至少一实施例在工作时，在第四时间段ST4，当NC1的电位小于Vinit的电压值时，N3的电位大于N4的电位，在第四时间段ST4开始时，T15和T16打开，N6的电位大于NT的电位，T14打开，NT输出低电压信号，OT输出低电压信号。
本公开图22A所示的驱动电路的至少一实施例在工作时，在显示时间段，OT输出的驱动信号与在第四时间段ST4，OT输出的驱动信号相同；在第四时间段ST4和显示时间段SD，OT都输出低电压信号；或者，在第四时间段ST4和显示时间段SD，OT都输出高电压信号。
在图22A所示的驱动电路的至少一实施例中，T13、T14、T15和T16组成锁存器，T9和T10组成差分部分。
本公开图21A、图22A所示的驱动电路的至少一实施例在工作时，在每一帧时间中的消隐时间段，在VCT提供的输出控制信号的置高过程中，都会导致NT输出的驱动输出信号有与VCT提供的输出控制信号相同脉宽的一个下拉信号或上拉信号，OT输出的驱动信号也会受到扰动。
图21D所示的像素电路的至少一实施例在工作时，当OT输出高电压信号时，M9处于开启状态，当OT输出低电压信号时，M9处于关闭状态。由于M9的栅极与M9的漏极之间存在电容，该电容主要包括：M9自身的寄生电容；在Layout(布局)设计中，TFT之外的节点之间的电容；其中，TFT之外的节点之间的电容可以从设计上进行优化尽可能减小，但是M9自身的电容是TFT自身必然存在的，无法彻底消除，且电容值为fF量级，在像素级别的节点之间的电容里算是大电容。
当发光控制线EM提供的发光控制信号在显示时间段内采用多pulse(脉冲)时，如图22D所示，包括图21D所示的像素电路的至少一实施例的显示面板包括多行发光控制线，在显示时间段SD内，各行发光控制线输出相应的发光控制信号，各发光控制信号具有三个向上的脉冲；
在消隐时间段SX，部分发光控制线提供的发光控制信号具有上升沿。
在图22D中，标号为EM1的为第一行发光控制线，标号为EM2的为第二行发光控制线，标号为EM3的为第三行发光控制线，标号为EM4的为第四行发光控制线，标号为EMN-3的为第N-3行发光控制线，标号为EMN-2的为第N-2行发光控制线，标号为EMN-1的为第N-1行发光控制线，标号为EMN的为第N行发光控制线；N为大于7的整数；
如图22D所示，在消隐时间段SX，EMN-3提供的第N-3行发光控制信号、EMN-2提供的第N-2行发光控制信号、EMN-1提供的第N-1行发光控制信号和EMN提供的第N行发光控制信号具有上升沿。
在消隐时间段，OT输出的驱动信号存在下拉信号，在像素电路中，M9的栅极与驱动晶体管M3的栅极之间存在电容，所述驱动信号的下拉信号对M3的栅极的电位造成耦合影响，而将M3的栅极的电位拉低；当所述发光控制线多脉冲输出时，部分行发光控制信 号在消隐时间段为关闭状态，大多数发光控制信号在消隐时间段保持开启状态，像素电路中的有机发光二极管处于发光阶段，此时驱动晶体管M3的栅极的电位的变化对这两种区域行对应的像素电路发光影响不同，造成不同区域的亮度差异，造成多分屏的情况。
针对上述问题，优化方案可以分为两大类：一是降低M9的栅极与驱动晶体管M3的栅极之间的电容，降低因驱动信号的扰动对M3的栅极带来的耦合影响；二是从生成驱动信号的驱动电路着手，使得该驱动电路输出的驱动信号稳定。本公开至少一实施例提供一种驱动电路，采用开关控制电路，所述开关控制电路在通断控制端VCT2提供的通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间连通或断开，使得驱动信号输出端OT输出的驱动信号不受VCT提供的输出控制信号的影响。
在具体实施时，在消隐时间段，VCT2提供的通断控制信号的脉宽大于VCT提供的输出控制信号的脉宽，所述通断控制信号的有效时间段的开始时刻早于所述输出控制信号的有效时间段的开始时刻，所述通断控制信号的有效时间段的结束时刻晚于所述输出控制信号的有效时间段的结束时刻。
在本公开至少一实施例中，所述通断控制信号的有效时间段指的是：所述通断控制信号为有效电压信号的时间段；
所述输出控制信号的有效时间段指的是：所述输出控制信号为有效电压信号的时间段；
当所述通断控制信号控制的晶体管为n型晶体管时，有效电压信号为高电压信号，当所述通断控制信号控制的晶体管为p型晶体管时，有效电压信号为低电压信号；
当所述输出控制信号控制的晶体管为n型晶体管时，有效电压信号为高电压信号，当所述输出控制信号控制的晶体管为p型晶体管时，有效电压信号为低电压信号。图23A所示的驱动电路的至少一实施例与图22A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与所述驱动输出端NT电连接，所述第七晶体管T7的漏极与T1的栅极电连接。
在图23A所示的驱动电路的至少一实施例中，T7为p型晶体管，T7为LTPS(低温多晶硅)晶体管。
如图23B所示，本公开图23A所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供高电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
在本公开至少一实施例中，增设了开关控制电路，所述开关控制电路包括第七晶体管， 所述第七晶体管为隔断TFT(薄膜晶体管)，隔断因驱动电路中，在每一帧的信号跳变带来的驱动输出信号的变化，提升驱动信号的稳定性，提高OLED(有机发光二极管)显示产品的显示效果。
图23C是图23B所示的驱动电路的至少一实施例的工作时序图；
在图23C中，标号为F1的为一帧时间，标号为SX的为消隐时间段，消隐时间段SX设置于一帧时间F1的最开始的时间段，标号为SD的为一帧时间F1包括的显示时间段。
如图23D所示，本公开图23A所示的驱动电路的至少一实施例在工作时，消隐时间段包括先后设置的第一时间段ST1、第二时间段ST2、第三时间段ST3和第四时间段ST4；
在第一时间段ST1、第二时间段ST2和第三时间段ST3，VCT提供高电压信号，T11和T12打开，N6和NT都与VGL之间连通，T15和T16都打开，NT输出低电压信号，T7关断，OT维持输出高电压信号；
在第一时间段ST1，SW提供低电压信号，T5关断；
在第二时间段ST2，SW提供高电压信号，VCT提供高电压信号，T5打开，将SL1提供的第一数据电压写入NC1，由于T5是IGZO TFT(薄膜晶体管)，将第一数据电压写入NC1需要一定时间；
在第三时间段ST3，SW提供低电压信号，VCT提供高电压信号，T5关闭，第一数据电压写入NC1的时间到，不再对NC1充电，通过C1维持NC1的电位；
在第四时间段ST4，VCT提供低电压信号，T11和T12关断，T8打开，VGH通过T8持续写入N2，I1提供初始电压Vinit，由于NC1的电位与Vinit的电压值之间存在电压差，导致N3的电位与N4的电位有差异；
在第四时间段ST4，VCT2提供低电压信号，T7打开；
在第四时间段ST4，NC1的电位大于Vinit的电压值，N3的电位小于N4的电位；在第四时间段ST4开始时，T15和T16打开，N6的电位小于NT的电位，T16打开，NT输出高电压信号，OT输出高电压信号。
本公开图23A所示的驱动电路的至少一实施例在工作时，在第四时间段ST4，当NC1的电位小于Vinit的电压值时，N3的电位大于N4的电位，在第四时间段ST4开始时，T15和T16打开，N6的电位大于NT的电位，T14打开，NT输出低电压信号，OT输出低电压信号。
图24所示的驱动电路的至少一实施例与图22A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与T1的漏极电连接，所述第七晶体管T7的漏极与T3的栅极电连接。
在图24所示的驱动电路的至少一实施例中，T7为p型晶体管，T7为LTPS(低温多 晶硅)晶体管。
如图23B所示，本公开图24所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供高电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图25所示的驱动电路的至少一实施例与图22A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与T3的漏极电连接，所述第七晶体管T7的漏极与所述驱动信号输出端OT电连接。
在图25所示的驱动电路的至少一实施例中，T7为p型晶体管，T7为LTPS(低温多晶硅)晶体管。
如图23B所示，本公开图25所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供高电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图26A所示的驱动电路的至少一实施例与图22A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与所述驱动输出端NT电连接，所述第七晶体管T7的漏极与T1的栅极电连接。
在图26A所示的驱动电路的至少一实施例中，T7为n型晶体管，T7为IGZO(铟镓锌氧化物)晶体管。
如图26B所示，本公开图26A所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通， NT与VGL之间连通；
在关断阶段SG，VCT2提供低电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图27所示的驱动电路的至少一实施例与图22A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与T1的漏极电连接，所述第七晶体管T7的漏极与T3的栅极电连接。
在图27所示的驱动电路的至少一实施例中，T7为n型晶体管，T7为IGZO(铟镓锌氧化物)晶体管。
如图26B所示，本公开图27所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供低电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图28所示的驱动电路的至少一实施例与图22A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与T3的漏极电连接，所述第七晶体管T7的漏极与所述驱动信号输出端OT电连接。
在图28所示的驱动电路的至少一实施例中，T7为n型晶体管，T7为IGZO(铟镓锌氧化物)晶体管。
如图26B所示，本公开图28所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供低电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图29A所示的驱动电路的至少一实施例与图21A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与所述驱动输出端NT电连接，所述第七晶体管T7的漏极与T1的栅极电连接。
在图29A所示的驱动电路的至少一实施例中，T7为p型晶体管，T7为LTPS(低温多晶硅)晶体管。
如图29B所示，本公开图29A所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供高电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图30所示的驱动电路的至少一实施例与图21A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与T1的漏极电连接，所述第七晶体管T7的漏极与驱动信号输出端OT电连接。
在图30所示的驱动电路的至少一实施例中，T7为p型晶体管，T7为LTPS(低温多晶硅)晶体管。
如图29B所示，本公开图30所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供高电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图31A所示的驱动电路的至少一实施例与图21A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与所述驱动输出端NT电连接，所述第七晶体管T7的漏极与T1的栅极电连接。
在图31A所示的驱动电路的至少一实施例中，T7为n型晶体管，T7为IGZO(铟镓 锌氧化物)晶体管。
如图31B所示，本公开图31A所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供低电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图32所示的驱动电路的至少一实施例与图21A所示的驱动电路的至少一实施例的区别如下：
还包括开关控制电路；
所述开关控制电路包括第七晶体管T7；
所述第七晶体管T7的栅极与所述通断控制端VCT2电连接，所述第七晶体管T7的源极与T1的漏极电连接，所述第七晶体管T7的漏极与驱动信号输出端OT电连接。
在图32所示的驱动电路的至少一实施例中，T7为n型晶体管，T7为IGZO(铟镓锌氧化物)晶体管。
如图31B所示，本公开图32所示的驱动电路的至少一实施例在工作时，一帧时间包括消隐时间段SX，所述消隐时间段包括关断阶段SG，所述关断阶段SG包括置位时间段SZ；
在置位时间段SZ，VCT提供高电压信号，T11和T12打开，N6与VGL之间连通，NT与VGL之间连通；
在关断阶段SG，VCT2提供低电压信号，T7关断，使得OT提供的驱动信号不受VCT提供的输出控制信号的影响。
图33所示的驱动电路的至少一实施例与图21A所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
在图33-图44所示的驱动电路的至少一实施例中，T6为n型晶体管。
在本公开图33-图44所示的驱动电路的至少一实施例中，当SW提供高电压信号时，SL1提供的第一数据电压写入NC1，SL2提供的第二数据电压写入NC2，NC1的电位和NC2的电位进行差分，SL1提供的第一数据电压为低电压信号，SL2提供的第二数据电压 为高电压信号，或者，SL1提供的第一数据电压为高电压信号，SL2提供的第二数据电压为低电压信号，例如，第一数据电压为7V电压信号，第二数据电压为0V电压信号，或者，第一数据电压为0V电压信号，第二数据电压为7V电压信号；当第一数据电压、第二数据电压具有一高一低的特点时，T15和T16才能完成较好的差分功能，且由于第一差分控制节点NC1的电位与第二差分控制节点NC2的电位相差较大，因此针对于图21A、图22A所示的驱动电路的至少一实施例，T15和T16的差分效果更明显，驱动电路的Margin也更大。
在图33-图44所示的驱动电路的至少一实施例中，由于驱动电路需要同时使用相邻两路数据线上的数据电压，使得列方向上的局部刷新控制分辨率较大；一级驱动电路可以驱动相邻两行像素电路。
图34所示的驱动电路的至少一实施例与图22A所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
可选的，所述第二电压端可以为低电压端。
图35所示的驱动电路的至少一实施例与图23A所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图36所示的驱动电路的至少一实施例与图24所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图37所示的驱动电路的至少一实施例与图25所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图38所示的驱动电路的至少一实施例与图26A所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图39所示的驱动电路的至少一实施例与图27所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图40所示的驱动电路的至少一实施例与图28所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图41所示的驱动电路的至少一实施例与图29A所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图42所示的驱动电路的至少一实施例与图30所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图43所示的驱动电路的至少一实施例与图31A所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
图44所示的驱动电路的至少一实施例与图32所示的驱动电路的至少一实施例的区别如下：还包括第二数据写入电路；
所述第二数据写入电路包括第六晶体管T6和第二电容C2；
所述第六晶体管T6的栅极与所述开关控制端SW电连接，所述第六晶体管T6的源极与所述第二数据线SL2电连接，所述第六晶体管T6的漏极与所述第二差分控制节点NC2电连接；
所述第二电容C2的第一端与所述第二差分控制节点NC2电连接，所述第二电容C2的第二端与低电压端VGL电连接。
本公开实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：
输出电路在开关控制信号和输出控制信号的控制下，根据数据电压，通过驱动输出端提供驱动输出信号；
反相电路包括的反相器对其输入端接入的信号进行反相，得到反相后的信号，通过该反相器的输出端输出所述反相后的信号。
在本公开至少一实施例中，所述输出电路包括第一数据写入电路、差分控制电路、输 入控制电路和输出控制电路；所述输出控制电路包括锁存电路和置位电路；一帧时间包括消隐时间段；所述消隐时间段包括置位时间段和输出阶段；所述置位时间段包括复位阶段、数据写入阶段和电位维持阶段；所述驱动方法包括：
在复位阶段，所述置位电路在输出控制信号的控制下，控制中间节点与第二电压端之间连通，控制驱动输出端与所述第二电压端之间连通；
在数据写入阶段，所述第一数据写入电路在开关控制信号的控制下，将第一数据线提供的第一数据电压写入所述第一差分控制节点；
在电位维持阶段，所述第一数据写入电路维持所述第一差分控制节点的电位；
在输出阶段，所述输入控制电路在输出控制信号的控制下，控制输入节点与第一电压端之间连通；所述差分控制电路在第一差分控制节点的电位和第二差分控制节点的电位的控制下，根据输入节点的电位，控制第一输出节点的电位和第二输出节点的电位；所述锁存电路在所述中间节点的电位的控制下，根据第一输出节点的电位和所述第二输出节点的电位，控制所述驱动输出端的电位。
在本公开至少一实施例中，所述输出电路还包括第二数据写入电路；所述驱动方法还包括：
在数据写入阶段，所述第二数据写入电路在开关控制信号的控制下，将第二数据线提供的第二数据电压写入第二差分控制节点；
在电位维持阶段，所述第二数据写入电路维持所述第二差分控制节点的电位。
可选的，所述驱动电路还包括开关控制电路；所述消隐时间段包括关断阶段，所述关断阶段包括所述置位时间段；所述驱动方法还包括：
在所述关断阶段，开关控制电路在通断控制信号的控制下，控制第一输出控制节点与第二输出控制节点之间断开。
本公开实施例所述的显示装置包括上述的驱动电路。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种驱动电路，包括输出电路和反相电路；
    所述输出电路分别与输出控制端、开关控制端、数据线和驱动输出端电连接，用于在所述开关控制端提供的开关控制信号和所述输出控制端提供的输出控制信号的控制下，根据所述数据线提供的数据电压，通过所述驱动输出端提供驱动输出信号；
    所述反相电路包括N级反相器；N为正整数；n为小于或等于N的正整数；
    第一反相器的输入端与所述驱动输出端电连接，第N反相器的输出端与驱动信号输出端电连接；
    当N大于1时，第m反相器的输出端与第m+1反相器的输入端电连接，m小于N的正整数；
    所述反相器用于对其输入端接入的信号进行反相，得到反相后的信号，通过该反相器的输出端输出所述反相后的信号。
  2. 如权利要求1所述的驱动电路，其中，所述输出电路包括第一数据写入电路、差分控制电路、输入控制电路和输出控制电路；
    所述第一数据写入电路分别与开关控制端、第一数据线和第一差分控制节点电连接，用于在所述开关控制端提供的开关控制信号的控制下，将所述第一数据线提供的第一数据电压写入所述第一差分控制节点，并维持所述第一差分控制节点的电位；
    所述差分控制电路分别与第一差分控制节点、第二差分控制节点、输入节点、第一输出节点和第二输出节点电连接，用于在所述第一差分控制节点的电位和所述第二差分控制节点的电位的控制下，根据所述输入节点的电位，控制所述第一输出节点的电位和第二输出节点的电位；
    所述输入控制电路分别与所述输出控制端、所述输入节点和第一电压端电连接，用于在所述输出控制端提供的输出控制信号的控制下，控制所述输入节点与所述第一电压端之间连通或断开；
    所述输出控制电路分别与所述输出控制端、第一输出节点、第二输出节点和驱动输出端电连接，用于在所述输出控制信号的控制下，根据所述第一输出节点的电位和所述第二输出节点的电位，生成并通过所述所述驱动输出端提供驱动输出信号。
  3. 如权利要求2所述的驱动电路，其中，所述输出控制电路包括锁存电路和置位电路；
    所述置位电路分别与输出控制端、中间节点、驱动输出端和第二电压端电连接，用于在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通或断开，控制所述驱动输出端与所述第二电压端之间连通或断开；
    所述锁存电路分别与所述第一输出节点、第二输出节点、所述中间节点、所述驱动输出端和第二电压端电连接，用于在所述中间节点的电位的控制下，根据第一输出节点的电 位和所述第二输出节点的电位，控制所述驱动输出端的电位。
  4. 如权利要求3所述的驱动电路，其中，所述输出电路还包括第二数据写入电路；
    所述第二数据写入电路分别与开关控制端、第二数据线和所述第二差分控制节点电连接，用于在所述开关控制端提供的开关控制信号的控制下，将所述第二数据线提供的第二数据电压写入所述第二差分控制节点，并维持所述第二差分控制节点的电位。
  5. 如权利要求3所述的驱动电路，其中，还包括开关控制电路；
    所述开关控制电路分别与通断控制端、第一输出控制节点和第二输出控制节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间连通或断开；
    所述第一输出控制节点与所述驱动输出端电连接，所述第二输出控制节点与所述第一反相器的输入端电连接；或者，
    所述第一输出控制节点与所述第N反相器的输出端电连接，所述第二输出控制节点与所述驱动信号输出端电连接；或者，
    N大于1，所述第一输出控制节点与所述第m反相器的输出端电连接，所述第二输出控制节点与所述第m+1反相器的输入端电连接。
  6. 如权利要求5所述的驱动电路，其中，所述锁存电路用于在所述中间节点的电位的控制下，控制所述第二输出节点与所述驱动输出端之间连通或断开，控制所述驱动输出端与所述第二电压端之间连通或断开，在所述驱动输出端的电位的控制下，控制所述第一输出节点与所述中间节点之间连通或断开，控制所述中间节点与所述第二电压端之间连通或断开。
  7. 如权利要求6所述的驱动电路，其中，一帧时间包括消隐时间段；所述消隐时间段包括关断阶段，所述关断阶段包括置位时间段；
    所述置位电路用于在所述置位时间段，在所述输出控制信号的控制下，控制所述中间节点与所述第二电压端之间连通，控制所述驱动输出端与所述第二电压端之间连通；
    所述开关控制电路用于在关断阶段，在所述通断控制信号的控制下，控制所述第一输出控制节点与所述第二输出控制节点之间断开。
  8. 如权利要求1所述的驱动电路，其中，N等于1；所述反相电路包括第一反相器，所述第一反相器包括第一晶体管和第二晶体管；
    所述第一晶体管的栅极与所述第一反相器的输入端电连接，所述第一晶体管的第一极与第一电压端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极都与所述驱动信号输出端电连接；
    所述第二晶体管的栅极与所述第一反相器的输入端电连接，所述第二晶体管的第二极与第二电压端电连接；
    所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管。
  9. 如权利要求1所述的驱动电路，其中，N等于2；所述反相电路包括第一反相器和 第二反相器；所述第一反相器包括第一晶体管和第二晶体管；所述第二反相器包括第三晶体管和第四晶体管；
    所述第一晶体管的栅极与所述第一反相器的输入端电连接，所述第一晶体管的第一极与第一电压端电连接，所述第一晶体管的第二极与所述第二晶体管的第一极都与所述第二反相器的输入端电连接；
    所述第二晶体管的栅极与所述第一反相器的输入端电连接，所述第二晶体管的第二极与第二电压端电连接；
    所述第三晶体管的栅极和所述第四晶体管的栅极都与所述第二反相器的输入端电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极和所述第四晶体管的第一极都与所述驱动信号输出端电连接；
    所述第四晶体管的第二极与所述第二电压端电连接；
    所述第一晶体管为p型晶体管，所述第二晶体管为n型晶体管；所述第三晶体管为p型晶体管，所述第四晶体管为n型晶体管。
  10. 如权利要求2所述的驱动电路，其中，所述第一数据写入电路包括第五晶体管和第一电容；
    所述第五晶体管的栅极与所述开关控制端电连接，所述第五晶体管的第一极与所述第一数据线电连接，所述第五晶体管的第二极与所述第一差分控制节点电连接；
    所述第一电容的第一端与所述第一差分控制节点电连接，所述第一电容的第二端与第二电压端电连接。
  11. 如权利要求4所述的驱动电路，其中，所述第二数据写入电路包括第六晶体管和第二电容；所述第六晶体管的栅极与所述开关控制端电连接，所述第六晶体管的第一极与所述第二数据线电连接，所述第六晶体管的第二极与所述第二差分控制节点电连接；
    所述第二电容的第一端与所述第二差分控制节点电连接，所述第二电容的第二端与第二电压端电连接。
  12. 如权利要求5所述的驱动电路，其中，所述开关控制电路包括第七晶体管；
    所述第七晶体管的栅极与所述通断控制端电连接，所述第七晶体管的第一极与所述第一输出控制节点电连接，所述第七晶体管的第二极与所述第二输出控制节点电连接。
  13. 如权利要求3所述的驱动电路，其中，所述输入控制电路包括第八晶体管，所述差分控制电路包括第九晶体管和第十晶体管；
    所述第八晶体管的栅极与所述输出控制端电连接，所述第八晶体管的第一极与所述第一电压端电连接，所述第八晶体管的第二极与所述输入节点电连接；
    所述第九晶体管的栅极与所述第一差分控制节点电连接，所述第九晶体管的第一极与所述输入节点电连接，所述第九晶体管的第二极与所述第一输出节点电连接；
    所述第十晶体管的栅极与所述第二差分控制节点电连接，所述第十晶体管的第一极与所述输入节点电连接，所述第十晶体管的第二极与所述第二输出节点电连接。
  14. 如权利要求13所述的驱动电路，其中，所述置位电路包括第十一晶体管和第十二晶体管；
    所述第十一晶体管的栅极与所述输出控制端电连接，所述第十一晶体管的第一极与所述中间节点电连接，所述第十一晶体管的第二极与所述第二电压端电连接；
    所述第十二晶体管的栅极与所述输出控制端电连接，所述第十二晶体管的第一极与所述驱动输出端电连接，所述第十二晶体管的第二极与所述第二电压端电连接。
  15. 如权利要求14所述的驱动电路，其中，所述第八晶体管为p型晶体管，所述第十一晶体管和所述第十二晶体管为n型晶体管；或者，所述第八晶体管为n型晶体管，所述第十一晶体管和所述第十二晶体管为p型晶体管。
  16. 如权利要求6所述的驱动电路，其中，所述锁存电路包括第十三晶体管、第十四晶体管、第十五晶体管和第十六晶体管；
    所述第十三晶体管的栅极与所述驱动输出端电连接，所述第十三晶体管的第一极与所述中间节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
    所述第十四晶体管的栅极与中间节点电连接，所述第十四晶体管的第一极与所述驱动输出端电连接，所述第十四晶体管的第二极与所述第二电压端电连接；
    所述第十五晶体管的栅极与所述驱动输出端电连接，所述第十五晶体管的第一极与所述第一输出节点电连接，所述第十五晶体管的第二极与所述中间节点电连接；
    所述第十六晶体管的栅极与所述中间节点电连接，所述第十六晶体管的第一极与所述第二输出节点电连接，所述第十六晶体管的第二极与所述驱动输出端电连接。
  17. 如权利要求16所述的驱动电路，其中，所述第十三晶体管和所述第十四晶体管为n型晶体管，所述第十五晶体管和所述第十六晶体管为p型晶体管。
  18. 一种驱动方法，应用于如权利要求1至17中任一权利要求所述的驱动电路，所述驱动方法包括：
    输出电路在开关控制信号和输出控制信号的控制下，根据数据电压，通过驱动输出端提供驱动输出信号；
    反相电路包括的反相器对其输入端接入的信号进行反相，得到反相后的信号，通过该反相器的输出端输出所述反相后的信号。
  19. 如权利要求18所述的驱动方法，其中，所述输出电路包括第一数据写入电路、差分控制电路、输入控制电路和输出控制电路；所述输出控制电路包括锁存电路和置位电路；一帧时间包括消隐时间段；所述消隐时间段包括置位时间段和输出阶段；所述置位时间段包括复位阶段、数据写入阶段和电位维持阶段；所述驱动方法包括：
    在复位阶段，所述置位电路在输出控制信号的控制下，控制中间节点与第二电压端之间连通，控制驱动输出端与所述第二电压端之间连通；
    在数据写入阶段，所述第一数据写入电路在开关控制信号的控制下，将第一数据线提供的第一数据电压写入第一差分控制节点；
    在电位维持阶段，所述第一数据写入电路维持所述第一差分控制节点的电位；
    在输出阶段，所述输入控制电路在输出控制信号的控制下，控制输入节点与第一电压端之间连通；所述差分控制电路在第一差分控制节点的电位和第二差分控制节点的电位的控制下，根据输入节点的电位，控制第一输出节点的电位和第二输出节点的电位；所述锁存电路在所述中间节点的电位的控制下，根据第一输出节点的电位和所述第二输出节点的电位，控制所述驱动输出端的电位。
  20. 如权利要求19所述的驱动方法，其中，所述输出电路还包括第二数据写入电路；所述驱动方法还包括：
    在数据写入阶段，所述第二数据写入电路在开关控制信号的控制下，将第二数据线提供的第二数据电压写入第二差分控制节点；
    在电位维持阶段，所述第二数据写入电路维持所述第二差分控制节点的电位。
  21. 如权利要求19或20所述的驱动方法，其中，所述驱动电路还包括开关控制电路；所述消隐时间段包括关断阶段，所述关断阶段包括所述置位时间段；所述驱动方法还包括：
    在所述关断阶段，开关控制电路在通断控制信号的控制下，控制第一输出控制节点与第二输出控制节点之间断开。
  22. 一种显示装置，包括如权利要求1至17中任一权利要求所述的驱动电路。
PCT/CN2024/094704 2023-03-29 2024-05-22 驱动电路、驱动方法和显示装置 Ceased WO2024199548A1 (zh)

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