WO2024195041A1 - 半導体装置、および、半導体装置の製造方法 - Google Patents

半導体装置、および、半導体装置の製造方法 Download PDF

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WO2024195041A1
WO2024195041A1 PCT/JP2023/011186 JP2023011186W WO2024195041A1 WO 2024195041 A1 WO2024195041 A1 WO 2024195041A1 JP 2023011186 W JP2023011186 W JP 2023011186W WO 2024195041 A1 WO2024195041 A1 WO 2024195041A1
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layer
collector
gate electrode
type
semiconductor device
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PCT/JP2023/011186
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English (en)
French (fr)
Japanese (ja)
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雅貴 須藤
正則 附田
知秀 寺島
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三菱電機株式会社
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Priority to JP2025508010A priority Critical patent/JPWO2024195041A1/ja
Priority to PCT/JP2023/011186 priority patent/WO2024195041A1/ja
Publication of WO2024195041A1 publication Critical patent/WO2024195041A1/ja

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

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  • the technology disclosed in this specification relates to semiconductor technology.
  • Some conventional semiconductor devices have a superjunction structure (a structure in which p-type columnar layers and n-type columnar layers are arranged alternately) in the drift region (see, for example, Patent Document 1).
  • the technology disclosed in this specification was developed in consideration of the problems described above, and is a technology for suppressing the occurrence of high surge voltages in semiconductor devices with a superjunction structure.
  • a semiconductor device includes a first pillar layer of a first conductivity type, a plurality of second pillar layers of a second conductivity type provided at a depth extending from an upper surface of the first pillar layer to within the first pillar layer, a first impurity layer of a first conductivity type provided on the upper surface of the first pillar layer, a base layer of a second conductivity type provided on the surface layer of the upper surface of the first impurity layer, a trench provided from the upper surface of the base layer to the first impurity layer and further to the inside of the first pillar layer, a first gate electrode provided within the trench and surrounded by a first insulating film, a source layer of a first conductivity type provided on a portion of the surface layer of the upper surface of the base layer and in contact with the first insulating film, and a first interlayer film provided covering a portion of the source layer and the first gate electrode.
  • FIG. 1 is a plan view showing an example of a configuration of a semiconductor device according to an embodiment
  • 2 is a cross-sectional view showing an example of the configuration of the element region of the configuration shown in FIG. 1 taken along the line AB.
  • 2 is a cross-sectional view showing another example of the configuration of the element region of the configuration shown in FIG. 1 taken along the line AB of the cross section.
  • 1 is a diagram conceptually illustrating an example of a configuration of a semiconductor device according to an embodiment
  • FIG. 5 is a diagram showing a state in which the semiconductor devices shown in FIG. 4 are connected in series.
  • 5 is a diagram showing an example of current mode discrimination when a current detected by a current detection unit in FIG. 4 is judged by a current mode judgment unit.
  • FIG. 5 is a diagram showing an example of current mode discrimination when a current detected by a current detection unit in FIG. 4 is judged by a current mode judgment unit.
  • 11A and 11B are diagrams illustrating examples of gate signals for different current modes of a collector current.
  • 11A and 11B are diagrams illustrating an example of how to determine a large current region and a small current region when the polarity of the collector current is positive.
  • 1 is a diagram conceptually illustrating an example of a configuration of a semiconductor device according to an embodiment; 10 is a diagram showing an example of distinguishing voltage modes when a voltage detected by a voltage detection means in FIG. 9 is judged by a voltage mode judgment means.
  • FIG. 11 is a diagram showing an example of how to determine a high voltage region and a low voltage region when the polarity of the collector-emitter voltage is positive.
  • FIG. 1 is a plan view showing an example of a configuration of a semiconductor device according to an embodiment
  • 13 is a cross-sectional view showing an example of the configuration shown in FIG. 12 taken along the line AB spanning the element region and the termination region.
  • FIG. 14 is a cross-sectional view showing a modified example of the configuration shown in FIG. 13.
  • FIG. 14 is a cross-sectional view showing another modified example of the configuration shown in FIG. 13.
  • the upper surface of " or “the lower surface of " when it is stated that “the upper surface of " or “the lower surface of " is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component.
  • the upper surface of " or “the lower surface of " when it is stated that "B is provided on the upper surface of A,” it does not prevent another component "C" from being interposed between A and B.
  • ⁇ Configuration of Semiconductor Device> 1 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in the example in Fig. 1, the semiconductor device includes an element region 12 and a termination region 14 that surrounds the element region 12 in a plan view.
  • FIG. 2 is a cross-sectional view showing an example of the configuration of the element region 12 taken along the line A-B in the configuration shown in FIG. 1.
  • the element region 12 includes an n-type pillar layer 22 and a plurality of p-type pillar layers 24 that are provided from the top surface of the n-type pillar layer 22 to a predetermined depth within the n-type pillar layer 22.
  • the structure in which the n-type pillar layers 22 and the p-type pillar layers 24 are alternately arranged in a direction perpendicular to the depth direction is also referred to as a breakdown voltage retention section.
  • the element region 12 also includes an n-type buffer layer 26 provided on the lower surface of the n-type pillar layer 22, and an emitter-side n-type layer 28 provided on the upper surface of the n-type pillar layer 22.
  • the element region 12 also includes a p-type collector layer 30 provided on the surface layer on the lower side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper side of the emitter-side n-type layer 28.
  • the element region 12 is provided with a trench 50 extending from the lower surface of the p-type collector layer 30 to the inside of the n-type buffer layer 26, and a trench 52 extending from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the inside of the n-type pillar layer 22.
  • the trench 50 is provided with an insulating film 54 provided along the bottom and side surfaces of the trench 50, and a collector-side gate electrode 58 provided within the trench 50 and surrounded by the insulating film 54.
  • the trench 52 is provided with an insulating film 56 provided along the bottom and side surfaces of the trench 52, and an emitter-side gate electrode 60 provided within the trench 52 and surrounded by the insulating film 56.
  • the collector-side gate electrode 58 contacts the p-type collector layer 30 sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54.
  • the collector-side gate electrode 58 is provided without reaching the n-type pillar layer 22.
  • the element region 12 also includes a collector-side n-type layer 34 that is provided on a portion of the surface layer on the lower side of the p-type collector layer 30 and in contact with the insulating film 54, and an n-type source layer 36 that is provided on a portion of the surface layer on the upper side of the p-type base layer 32 and in contact with the insulating film 56.
  • the n-type source layer 36, the p-type base layer 32, the insulating film 56, and the emitter-side gate electrode 60 are collectively also referred to as the emitter-side channel portion.
  • the collector-side n-type layer 34, the p-type collector layer 30, the insulating film 54, and the collector-side gate electrode 58 are collectively also referred to as the collector-side channel portion.
  • the element region 12 also includes an interlayer film 38 provided to cover a portion of the collector-side n-type layer 34 and the collector-side gate electrode 58, a collector electrode 42 provided to cover the p-type collector layer 30, the collector-side n-type layer 34 and the interlayer film 38, an interlayer film 40 provided to cover a portion of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 provided to cover the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.
  • an interlayer film 38 provided to cover a portion of the collector-side n-type layer 34 and the collector-side gate electrode 58
  • a collector electrode 42 provided to cover the p-type collector layer 30, the collector-side n-type layer 34 and the interlayer film 38
  • an interlayer film 40 provided to cover a portion of the n-type source layer 36 and the emitter-side gate electrode 60
  • an emitter electrode 44 provided to cover the p-type base layer 32, the n
  • the emitter-side n-type layer 28 is shallower than the bottom of the emitter-side gate electrode 60 and is formed between the p-type base layer 32 and the breakdown voltage holding portion.
  • the breakdown voltage holding portion consisting of the n-type pillar layer 22 and the p-type pillar layer 24 is also called a superjunction structure.
  • the peak impurity concentration of the n-type source layer 36 is, for example, not less than 1 ⁇ 10 18 cm ⁇ 3 and not more than 1 ⁇ 10 21 cm ⁇ 3
  • the peak impurity concentration of the p-type base layer 32 is, for example, 1 ⁇ 10 17 cm ⁇ 3 .
  • the peak impurity concentration of the emitter-side n-type layer 28 is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less
  • the peak impurity concentration of the n-type buffer layer 26 is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the impurity concentration is about 1 ⁇ 10 14 cm ⁇ 3 , but in the above-mentioned superjunction structure, the impurity concentrations of the n-type pillar layer 22 and the p-type pillar layer 24 are about 1 ⁇ 10 15 cm ⁇ 3 .
  • the repeating interval (emitter side gate pitch) of the emitter side gate electrodes 60 and the repeating interval (collector side gate pitch) of the collector side gate electrodes 58 do not have to be the same.
  • the element region 12 includes an n-pillar layer 22, a p-pillar layer 24, an n-buffer layer 26A provided on the lower surface of the n-pillar layer 22, and an emitter-side n-layer 28.
  • the element region 12 also includes a collector-side n-type layer 34A provided on a portion of the surface layer on the lower side of the p-type collector layer 30A, and an n-type source layer 36.
  • the element region 12 is also provided with an insulating film 54A covering a part of the p-type collector layer 30A, the collector-side n-type layer 34A, and the exposed n-type buffer layer 26A, a collector-side gate electrode 58A covering the insulating film 54A, an interlayer film 38A covering the collector-side gate electrode 58A, a collector electrode 42 provided to cover the p-type collector layer 30A and the interlayer film 38A, an interlayer film 40, and an emitter electrode 44.
  • the collector-side gate electrode 58A contacts the p-type collector layer 30A sandwiched between the n-type buffer layer 26A and the collector-side n-type layer 34A via the insulating film 54A.
  • the collector-side gate electrode 58A is provided without reaching the n-type pillar layer 22.
  • a positive voltage is applied to the collector side gate electrode 58, and the collector side channel portion electrically connects the collector side n-type layer 34 and the voltage retention portion.
  • unipolar operation refers to an operation in which electrons pass from the collector side n-type layer 34 through the channel, flow through the breakdown voltage holding portion, and reach the n-type source layer 36.
  • bipolar operation refers to an operation in which holes are injected from the p-type base layer 32 when electrons pass from the collector side n-type layer 34 through the channel, flow through the breakdown voltage holding portion, and reach the p-type base layer 32.
  • reverse recovery which is the transition process from a reverse conductive state to a cutoff state
  • electrons are discharged to the collector-side n-type layer 34 and holes are discharged to the p-type base layer 32, and a depletion layer spreads from both sides of the breakdown voltage retention section.
  • the breakdown voltage holding section When the breakdown voltage holding section is made thinner by the superjunction structure, it becomes easier for the breakdown voltage holding section to become completely depleted during bipolar recovery. When the breakdown voltage holding section becomes completely depleted, the recovery current is suddenly cut off, so if the breakdown voltage holding section becomes completely depleted when a large recovery current is flowing, a large surge voltage will be generated.
  • the emitter-side n-type layer 28 is provided, hole injection from the p-type base layer 32 decreases during reverse conduction of the bipolar, and carrier accumulation on the emitter side can be reduced. This promotes depletion from the emitter side during bipolar recovery. This suppresses depletion from the collector side, and makes it possible to suppress the generation of a large surge voltage due to complete depletion.
  • the semiconductor device according to this embodiment can avoid a large surge voltage during bipolar recovery. Therefore, it is possible to pass current in both directions while suppressing electromagnetic noise or destruction caused by a large surge voltage.
  • Second Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described.
  • components similar to those described in the above embodiment are illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • Fig. 4 is a diagram conceptually showing an example of the configuration of a semiconductor device according to this embodiment.
  • the semiconductor device includes a collector-side gate driver 102 for driving the collector-side gate electrode 58 of Fig. 1, an emitter-side gate driver 104 for driving the emitter-side gate electrode 60 of Fig. 1, a PWM (Pulse Width Modulation) control means 106 for outputting control signals to the collector-side gate driver 102 and the emitter-side gate driver 104, a current detector 108 for detecting a collector current (load current), and a current mode determination means 110 for determining a current mode based on a current value detected by the current detector 108.
  • PWM Pulse Width Modulation
  • FIG. 5 shows the semiconductor devices shown in FIG. 4 connected in series.
  • FIG. 6 shows an example of how the current mode is distinguished when the current detected by the current detection means 108 in FIG. 4 is judged by the current mode judgment means 110.
  • the current mode determination means 110 sets the emitter side gate signal as a PWM control signal (i.e., a PWM control signal is output from the PWM control means 106 to the emitter side gate drive means 104 based on the determination result in the current mode determination means 110).
  • the current mode determination means 110 turns off the collector side gate signal (i.e., the signal that drives the collector side gate electrode 58) when the collector current value is greater than a predetermined threshold value, and turns on the collector side gate signal when the collector current value is less than the predetermined threshold value.
  • the current mode determination means 110 turns on the collector side gate signal when the current detection means 108 detects a collector current with a negative polarity.
  • the current mode determination means 110 sets the emitter side gate signal to a PWM control signal when the collector current value is smaller than a predetermined threshold value, and cuts off the PWM control signal and does not output the emitter side gate signal when the collector current value is larger than the predetermined threshold value.
  • FIG. 7 shows examples of gate signals for different collector current modes. As shown in the example in FIG. 7, when the collector current polarity is positive and the collector current value is large (i.e., in the large current region), bipolar operation is achieved by turning off the collector side gate signal.
  • the collector side gate signal is turned on to achieve unipolar operation.
  • the collector side gate signal is turned on to achieve unipolar operation.
  • the PWM control signal for the emitter side gate is cut off and the collector side gate signal is turned on to achieve bipolar operation.
  • Figure 8 shows an example of how to determine the large current region and the small current region when the polarity of the collector current is positive.
  • Figure 8 shows the collector current X1 when the collector side gate signal is turned on, and the collector current X2 when the collector side gate signal is turned off.
  • the vertical axis shows the magnitude of the collector current
  • the horizontal axis shows the magnitude of the voltage between the collector electrode and the emitter electrode.
  • collector current X1 As shown in the example in Figure 8, as the voltage between the collector electrode and the emitter electrode increases, both collector current X1 and collector current X2 increase. Furthermore, collector current X2 is smaller than collector current X1 in the range where the voltage between the collector electrode and the emitter electrode is small, and is larger than collector current X1 in the range where the voltage between the collector electrode and the emitter electrode is large.
  • the value of the collector current at the timing when the magnitude relationship between collector current X1 and collector current X2 is reversed can be defined as the boundary value between the large current region and the small current region.
  • the collector current transitions in the following order: (positive large), (positive small), (negative small), (negative large), (negative small), (positive small), (positive large), (positive small), ... but the operating mode (current mode) remains the same before and after the polarity reversal of the collector current. Therefore, there is no need to detect the current when the polarity of the collector current reverses (detect that the current is 0A).
  • Fig. 9 is a diagram conceptually showing an example of the configuration of a semiconductor device according to this embodiment.
  • the semiconductor device includes a collector-side gate drive means 102 for driving the collector-side gate electrode 58 of Fig. 1, an emitter-side gate drive means 104 for driving the emitter-side gate electrode 60 of Fig. 1, a PWM control means 106 for outputting control signals to the collector-side gate drive means 102 and the emitter-side gate drive means 104, a voltage detection means 112 for detecting a collector-emitter voltage, and a voltage mode determination means 114 for determining a voltage mode based on a voltage value detected by the voltage detection means 112.
  • FIG. 10 is a diagram showing an example of how the voltage mode is distinguished when the voltage detected by the voltage detection means 112 in FIG. 9 is judged by the voltage mode judgment means 114.
  • the voltage mode determination means 114 sets the emitter side gate signal as a PWM control signal (i.e., a PWM control signal is output from the PWM control means 106 to the emitter side gate drive means 104 based on the determination result in the voltage mode determination means 114).
  • the voltage mode determination means 114 turns off the collector side gate signal (i.e., the signal that drives the collector side gate electrode 58) when the collector-emitter voltage is greater than a predetermined threshold value, and turns on the collector side gate signal when the collector current value is less than the predetermined threshold value.
  • the voltage mode determination means 114 turns on the collector side gate signal when the voltage detection means 112 detects a collector current with a negative polarity.
  • the voltage mode determination means 114 sets the emitter side gate signal to a PWM control signal when the collector-emitter voltage is smaller than a predetermined threshold value, and cuts off the PWM control signal and does not output the emitter side gate signal when the collector-emitter voltage is larger than the predetermined threshold value.
  • the collector side gate is turned off to achieve bipolar operation.
  • the collector side gate is turned on to achieve unipolar operation.
  • the collector side gate is turned on to achieve unipolar operation.
  • the PWM control signal for the emitter gate is cut off and the collector gate is turned on, resulting in bipolar operation.
  • Figure 11 shows an example of how to determine the high voltage region and the low voltage region when the polarity of the collector-emitter voltage is positive.
  • Figure 11 shows the collector current Y1 when the collector side gate signal is turned on, and the collector current Y2 when the collector side gate signal is turned off.
  • the vertical axis shows the magnitude of the collector current
  • the horizontal axis shows the magnitude of the voltage between the collector electrode and the emitter electrode.
  • the collector current Y2 is smaller than the collector current Y1 in the range where the voltage between the collector electrode and the emitter electrode is small, and is larger than the collector current Y1 in the range where the voltage between the collector electrode and the emitter electrode is large.
  • the value of the collector-emitter voltage at the timing when the magnitude relationship between collector current Y1 and collector current Y2 is reversed can be defined as the boundary value between the high voltage region and the low voltage region.
  • the collector-emitter voltage transitions in the following order: (positive large), (positive small), (negative small), (negative large), (negative small), (positive small), (positive large), (positive small), ... but the operating mode (voltage mode) remains the same before and after the polarity reversal of the collector-emitter voltage. Therefore, there is no need to detect the voltage (detect that the voltage is 0V) when the polarity of the collector-emitter voltage reverses.
  • ⁇ Configuration of Semiconductor Device> 12 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in the example of FIG. 12, the semiconductor device includes an element region 12 and a termination region 14A that surrounds the element region 12 in a plan view.
  • FIG. 13 is a cross-sectional view showing an example of the configuration shown in FIG. 12 taken along the line A-B spanning the element region 12 and the termination region 14A.
  • the element region 12 and the termination region 14A are provided with an n-type pillar layer 22 and a number of p-type pillar layers 24.
  • the element region 12 and the termination region 14A are also provided with an n-type buffer layer 26.
  • the element region 12 is also provided with an emitter-side n-type layer 28 provided on the upper surface of the n-type pillar layer 22.
  • the element region 12 also includes a p-type collector layer 30 provided on the surface layer on the lower side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper side of the emitter-side n-type layer 28.
  • the termination region 14A also includes an n-type cathode layer 62 provided in the surface layer on the lower surface side of the n-type buffer layer 26, and a plurality of p-type well layers 64 provided across the p-type pillar layers 24 in the surface layer on the upper surface side of the n-type pillar layers 22.
  • the peak impurity concentration of the n-type cathode layer 62 is, for example, not less than 1 ⁇ 10 18 cm -3 and not more than 1 ⁇ 10 21 cm -3 .
  • the element region 12 also includes a trench 50 and a trench 52.
  • the trench 50 includes an insulating film 54 and a collector-side gate electrode 58.
  • the trench 52 includes an insulating film 56 and an emitter-side gate electrode 60.
  • the element region 12 also includes a collector-side n-type layer 34 and an n-type source layer 36.
  • the element region 12 also includes an interlayer film 38, a collector electrode 42, an interlayer film 40, and an emitter electrode 44.
  • the termination region 14A is also provided with an interlayer film 66 provided to cover a portion of the p-type well layer 64, an interlayer film 68 provided to cover a portion of the p-type well layer 64 and the p-type pillar layer 24, an interlayer film 70 provided to cover a portion of the p-type well layer 64 and the n-type pillar layer 22, an electrode 72 provided to cover a portion of the interlayer film 66, a portion of the interlayer film 68, and the exposed p-type well layer 64, and an electrode 74 provided to cover a portion of the interlayer film 68, a portion of the interlayer film 70, and the exposed p-type well layer 64.
  • a portion of the interlayer film 66 is covered by the emitter electrode 44.
  • a collector electrode 42 is provided to cover the n-type cathode layer 62.
  • the termination region 14A shown in Figures 12 and 13 has a FLR (Field Limiting Ring) structure, but may have a RESURF (Reduced Surface Electric Field) structure or a VLD (Variation of lateral doping) structure.
  • FLR Field Limiting Ring
  • RESURF Reduced Surface Electric Field
  • VLD Variation of lateral doping
  • a pn diode is formed consisting of a p-type layer (p-type pillar layer 24, p-type well layer 64) on the front side of the n-type pillar layer 22 and an n-type cathode layer 62 on the back side of the n-type pillar layer 22. Therefore, even if the collector side gate signal is stopped due to a malfunction, reverse conduction is possible, and damage to the semiconductor device can be suppressed.
  • FIG. 14 is a cross-sectional view showing a modification of the configuration shown in FIG.
  • the element region 12B and the termination region 14B are provided with an n-type pillar layer 22 and a plurality of p-type pillar layers 24.
  • the element region 12B and the termination region 14B are provided with an n-type buffer layer 26.
  • the element region 12B is also provided with an emitter-side n-type layer 28 provided on the upper surface of the n-type pillar layer 22.
  • the element region 12B also includes a p-type collector layer 30B provided on a portion of the surface layer on the lower side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper side of the emitter-side n-type layer 28.
  • the termination region 14B also includes an n-type cathode layer 62B provided on the surface layer on the lower side of the n-type buffer layer 26, and a plurality of p-type well layers 64 provided across the p-type pillar layer 24 on the surface layer on the upper side of the n-type pillar layer 22.
  • the n-type cathode layer 62B is also provided on a portion of the surface layer on the lower side of the n-type buffer layer 26 in the element region 12B.
  • the n-type cathode layer 62B provided in the element region 12B and the n-type cathode layer 62B provided in the termination region 14B may be continuous or discontinuous. In other words, the n-type cathode layer 62B provided in the element region 12B may be provided discretely in the element region 12B.
  • the element region 12B includes a trench 50 and a trench 52.
  • the trench 50 includes an insulating film 54 and a collector-side gate electrode 58.
  • the trench 52 includes an insulating film 56 and an emitter-side gate electrode 60.
  • the element region 12B also includes a collector-side n-type layer 34 and an n-type source layer 36.
  • the element region 12B is also provided with an interlayer film 38, a collector electrode 42, an interlayer film 40, and an emitter electrode 44.
  • the collector electrode 42 is provided to cover the p-type collector layer 30B and the n-type cathode layer 62B.
  • the termination region 14B is provided with an interlayer film 66, an interlayer film 68, an interlayer film 70, an electrode 72, and an electrode 74. A portion of the interlayer film 66 is covered by the emitter electrode 44.
  • a pn diode is formed consisting of a p-type layer (p-type pillar layer 24, p-type well layer 64) on the front side of the n-type pillar layer 22 and an n-type cathode layer 62B on the back side of the n-type pillar layer 22. Therefore, even if the collector side gate signal is stopped due to a malfunction, reverse conduction is possible, and damage to the semiconductor device can be suppressed.
  • FIG. 15 is a cross-sectional view showing another modification of the configuration shown in FIG.
  • the element region 12C and the termination region 14C are provided with an n-type pillar layer 22 and a number of p-type pillar layers 24.
  • the element region 12C and the termination region 14C are provided with an n-type buffer layer 26.
  • the element region 12C is also provided with an emitter-side n-type layer 28 provided on the upper surface of the n-type pillar layer 22.
  • the element region 12C also includes a p-type collector layer 30B provided on a portion of the surface layer on the lower side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper side of the emitter-side n-type layer 28.
  • the termination region 14C is provided with an n-type cathode layer 62C provided on the surface layer on the lower side of the n-type buffer layer 26, and a plurality of p-type well layers 64 provided across the p-type pillar layer 24 on the surface layer on the upper side of the n-type pillar layer 22.
  • the n-type cathode layer 62C is also provided on a part of the surface layer on the lower side of the n-type buffer layer 26 in the element region 12C.
  • the n-type cathode layer 62C provided in the element region 12C and the n-type cathode layer 62C provided in the termination region 14C may be continuous or discontinuous.
  • the n-type cathode layer 62C provided in the element region 12C may be provided discretely in the element region 12C.
  • the n-type cathode layer 62C is a layer formed to have at least one of the impurity concentration and depth equal to that of the collector-side n-type layer 34. Note that the same impurity concentration or the same depth includes cases where there is a deviation of, for example, a few percent within the range of measurement error.
  • the element region 12C includes a trench 50 and a trench 52.
  • the trench 50 includes an insulating film 54 and a collector-side gate electrode 58.
  • the trench 52 includes an insulating film 56 and an emitter-side gate electrode 60.
  • the element region 12C also includes a collector-side n-type layer 34 and an n-type source layer 36.
  • the element region 12C also includes an interlayer film 38, a collector electrode 42, an interlayer film 40, and an emitter electrode 44.
  • the termination region 14C is provided with an interlayer film 66, an interlayer film 68, an interlayer film 70, an electrode 72, and an electrode 74. A portion of the interlayer film 66 is covered by the emitter electrode 44.
  • the method for manufacturing the configuration shown in FIG. 15 involves first providing n-type pillar layers 22 and p-type pillar layers 24 in the element region 12C and the termination region 14C.
  • the p-type pillar layers 24 are provided at a depth that reaches from the upper surface of the n-type pillar layer 22 into the n-type pillar layer 22.
  • the n-type pillar layers 22 and the p-type pillar layers 24 are formed alternately in a direction perpendicular to the depth direction of the n-type pillar layer 22.
  • an emitter-side n-type layer 28 is provided on the upper surface of the n-type pillar layer 22, and a p-type base layer 32 is provided in the surface layer of the upper surface of the emitter-side n-type layer 28.
  • an n-type source layer 36 is provided in part of the surface layer of the upper surface of the p-type base layer 32.
  • a trench 52 is provided that extends from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the inside of the n-type pillar layer 22 so as to contact the n-type source layer 36, and an emitter-side gate electrode 60 surrounded by an insulating film 56 is provided within the trench 52.
  • an interlayer film 40 is provided to cover a portion of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 is provided to cover the p-type base layer 32, the n-type source layer 36, and the interlayer film 40.
  • an n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22.
  • a p-type collector layer 30B is provided on a portion of the surface layer of the lower surface of the n-type buffer layer 26.
  • an n-type cathode layer 62C is provided on another part of the surface layer of the lower surface of the n-type buffer layer 26, and a collector-side n-type layer 34 is provided on a part of the surface layer of the lower surface of the p-type collector layer 30B.
  • an n-type cathode layer 62C is provided on the surface layer of the lower surface of the n-type buffer layer 26.
  • a collector-side gate electrode 58 is provided so as to contact the p-type collector layer 30B sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54, but not to reach the n-type pillar layer 22.
  • a trench 50 is provided in the element region 12C so as to contact the collector-side n-type layer 34 from the lower surface of the p-type collector layer 30B to the inside of the n-type buffer layer 26, but not to reach the n-type pillar layer 22, and a collector-side gate electrode 58 surrounded by the insulating film 54 is provided in the trench 50.
  • an interlayer film 38 is provided to cover the collector-side gate electrode 58.
  • a collector electrode 42 is provided to cover the p-type collector layer 30B, the interlayer film 38, and the n-type cathode layer 62C.
  • a pn diode is formed consisting of a p-type layer (p-type pillar layer 24, p-type well layer 64) on the front side of the n-type pillar layer 22 and an n-type cathode layer 62C on the back side of the n-type pillar layer 22. Therefore, even if the collector side gate signal is stopped due to a malfunction, reverse conduction is possible, and damage to the semiconductor device can be suppressed.
  • the semiconductor device includes a first pillar layer of a first conductivity type (n type), a plurality of second pillar layers of a second conductivity type (p type), a first impurity layer of n type, a p-type base layer, a trench 52, a first gate electrode, an n-type source layer, a first interlayer film, an emitter electrode 44, an n-type buffer layer, a p-type collector layer, a second impurity layer, a second gate electrode, a second interlayer film, and a collector electrode 42.
  • the first pillar layer corresponds to, for example, the n-type pillar layer 22, etc.
  • the second pillar layer corresponds to, for example, the p-type pillar layer 24, etc.
  • the first impurity layer corresponds to, for example, the emitter-side n-type layer 28, etc.
  • the base layer corresponds to, for example, the p-type base layer 32, etc.
  • the first gate electrode corresponds to, for example, the emitter-side gate electrode 60.
  • the source layer corresponds to, for example, the n-type source layer 36.
  • the first interlayer film corresponds to, for example, the interlayer film 40.
  • the buffer layer corresponds to, for example, the n-type buffer layer 26, the n-type buffer layer 26A.
  • the collector layer corresponds to, for example, the p-type collector layer 30, the p-type collector layer 30A, the p-type collector layer 30B.
  • the second impurity layer corresponds to, for example, the collector-side n-type layer 34, the collector-side n-type layer 34A.
  • the second gate electrode corresponds to, for example, the collector-side gate electrode 58, the collector-side gate electrode 58A.
  • the second interlayer film corresponds to, for example, the interlayer film 38, the interlayer film 38A.
  • the p-type pillar layer 24 is provided at a depth reaching from the upper surface of the n-type pillar layer 22 into the n-type pillar layer 22.
  • the emitter-side n-type layer 28 is provided on the upper surface of the n-type pillar layer 22.
  • the p-type base layer 32 is provided in the surface layer of the upper surface of the emitter-side n-type layer 28.
  • the trench 52 is provided from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the inside of the n-type pillar layer 22.
  • the emitter-side gate electrode 60 is provided in the trench 52 surrounded by a first insulating film.
  • the first insulating film corresponds to, for example, the insulating film 56.
  • the n-type source layer 36 is provided in a part of the surface layer of the upper surface of the p-type base layer 32 and is in contact with the insulating film 56.
  • the interlayer film 40 is provided to cover a part of the n-type source layer 36 and the emitter-side gate electrode 60.
  • the emitter electrode 44 is provided to cover the p-type base layer 32, the n-type source layer 36, and the interlayer film 40.
  • the n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22.
  • the p-type collector layer 30 is provided on the surface layer of the lower surface of the n-type buffer layer 26.
  • the collector-side n-type layer 34 is provided on a part of the surface layer of the lower surface of the p-type collector layer 30.
  • the collector-side gate electrode 58 is provided in contact with the p-type collector layer 30 sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via a second insulating film, and does not reach the n-type pillar layer 22.
  • the second insulating film corresponds to, for example, the insulating film 54, the insulating film 54A, etc.
  • the interlayer film 38 is provided to cover the collector-side gate electrode 58.
  • the collector electrode 42 is provided to cover the p-type collector layer 30 and the interlayer film 38.
  • the n-type pillar layers 22 and the p-type pillar layers 24 are arranged alternately in a direction intersecting the depth direction of the n-type pillar layers 22.
  • This configuration makes it possible to suppress the occurrence of high surge voltages in a semiconductor device having a superjunction structure. Specifically, because the emitter-side n-type layer 28 is provided, hole injection from the p-type base layer 32 decreases during reverse conduction of the bipolar. This reduces carrier accumulation on the emitter side. This promotes depletion from the emitter side during bipolar recovery. This in turn suppresses depletion from the collector side, making it possible to suppress the occurrence of large surge voltages due to complete depletion.
  • the semiconductor device includes a current detection unit and a control unit.
  • the current detection unit corresponds to, for example, the current detection means 108.
  • the control unit corresponds to, for example, the current mode determination means 110 and the PWM control means 106.
  • the current detection means 108 detects the collector current output through the collector electrode 42.
  • the control unit controls the voltage applied to the emitter side gate electrode 60 and the collector side gate electrode 58 based on the polarity and current value of the collector current detected by the current detection means 108. With this configuration, the operation of the emitter side gate electrode 60 and the collector side gate electrode 58 is switched according to the detected collector current, and the semiconductor device is selectively used for bipolar operation and unipolar operation, thereby suppressing the generation of a large surge voltage.
  • the control unit when the polarity of the collector current is positive and the current value of the collector current is greater than a predetermined threshold value, the control unit turns the emitter side gate electrode 60 to the ON state and the collector side gate electrode 58 to the OFF state.
  • the control unit turns the emitter side gate electrode 60 to the ON state and the collector side gate electrode 58 to the ON state.
  • the control unit turns the emitter side gate electrode 60 to the ON state and the collector side gate electrode 58 to the ON state.
  • the control unit When the polarity of the collector current is negative and the current value of the collector current is greater than a predetermined threshold value, the control unit turns the emitter side gate electrode 60 to the OFF state and the collector side gate electrode 58 to the ON state.
  • the operation of the emitter side gate electrode 60 and the collector side gate electrode 58 can be switched depending on the detected collector current, and the semiconductor device can be selectively operated between bipolar and unipolar, thereby suppressing the generation of large surge voltages.
  • the semiconductor device includes a voltage detection unit and a control unit.
  • the voltage detection unit corresponds to, for example, the voltage detection means 112 and the like.
  • the control unit corresponds to the voltage mode determination means 114 and the PWM control means 106 and the like.
  • the voltage detection means 112 detects the interelectrode voltage, which is the voltage applied between the collector electrode 42 and the emitter electrode.
  • the control unit controls the voltage applied to the emitter side gate electrode 60 and the collector side gate electrode 58 based on the polarity and voltage value of the interelectrode voltage detected by the voltage detection means 112.
  • the operation of the emitter side gate electrode 60 and the collector side gate electrode 58 is switched according to the detected collector-emitter voltage, and the semiconductor device is selectively used for bipolar operation and unipolar operation, thereby suppressing the generation of a large surge voltage.
  • the control unit when the polarity of the interelectrode voltage is positive and the voltage value of the interelectrode voltage is greater than a predetermined threshold value, the control unit turns the emitter side gate electrode 60 on and the collector side gate electrode 58 off. When the polarity of the interelectrode voltage is positive and the voltage value of the interelectrode voltage is smaller than a predetermined threshold value, the control unit turns the emitter side gate electrode 60 on and the collector side gate electrode 58 on. When the polarity of the interelectrode voltage is negative and the voltage value of the interelectrode voltage is smaller than a predetermined threshold value, the control unit turns the emitter side gate electrode 60 on and the collector side gate electrode 58 on.
  • the control unit When the polarity of the interelectrode voltage is negative and the voltage value of the interelectrode voltage is greater than a predetermined threshold value, the control unit turns the emitter side gate electrode 60 off and the collector side gate electrode 58 on. With this configuration, the operation of the emitter side gate electrode 60 and the collector side gate electrode 58 can be switched depending on the detected collector-emitter voltage, allowing the semiconductor device to operate in either bipolar or unipolar mode, thereby suppressing the occurrence of large surge voltages.
  • the semiconductor device includes an element region 12 (or an element region 12B, an element region 12C) and a termination region 14A (or a termination region 14B, an termination region 14C) surrounding the element region 12 in a planar view.
  • an n-type pillar layer 22, a p-type pillar layer 24, and an n-type buffer layer 26 are provided in the element region 12 and the termination region 14A.
  • the semiconductor device includes an n-type cathode layer provided on the surface layer of the lower surface of the n-type buffer layer 26 in the termination region 14A.
  • the cathode layer corresponds to, for example, an n-type cathode layer 62, an n-type cathode layer 62B, an n-type cathode layer 62C, etc.
  • a collector electrode 42 is provided covering the n-type cathode layer 62.
  • a pn diode is formed in the termination region 14A, consisting of a p-type layer (p-type pillar layer 24, p-type well layer 64) on the front side of the n-type pillar layer 22 and an n-type cathode layer 62 on the back side of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, and damage to the semiconductor device can be suppressed.
  • the n-type cathode layer 62B (or the n-type cathode layer 62C) is provided in a part of the surface layer of the lower surface of the n-type buffer layer 26 in the element region 12B (or the element region 12C).
  • the p-type collector layer 30B is provided in another part of the surface layer of the lower surface of the n-type buffer layer 26.
  • the collector electrode 42 is provided covering the p-type collector layer 30B and the n-type cathode layer 62B (or the n-type cathode layer 62C).
  • a pn diode is formed consisting of the p-type layer (p-type pillar layer 24, p-type well layer 64) on the surface side of the n-type pillar layer 22 and the n-type cathode layer 62B on the back side of the n-type pillar layer 22. Therefore, even if the collector side gate signal stops due to a malfunction, reverse conduction is possible, preventing damage to the semiconductor device.
  • the n-type cathode layer 62C and the collector-side n-type layer 34 are formed in the same process, so that their impurity concentrations or depths are the same.
  • the collector-side n-type layer 34 in the element region 12C and the n-type cathode layer 62C in the element region 12C and the termination region 14C are formed in the same process, so the number of manufacturing steps can be reduced compared to when they are formed separately in different processes.
  • the semiconductor device in the method for manufacturing a semiconductor device, includes an element region 12C and a termination region 14C that surrounds the element region 12C in a planar view.
  • n-type pillar layers 22 and a plurality of p-type pillar layers 24 that are provided at a depth that reaches from the upper surface of the n-type pillar layer 22 into the n-type pillar layer 22 are alternately arranged in a direction intersecting the depth direction of the n-type pillar layer 22.
  • an emitter-side n-type layer 28 is provided on the upper surface of the n-type pillar layer 22, and a p-type base layer 32 is provided in the surface layer of the upper surface of the emitter-side n-type layer 28.
  • an n-type source layer 36 is provided in a part of the surface layer of the upper surface of the p-type base layer 32.
  • a trench 52 is provided extending from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the inside of the n-type pillar layer 22 so as to contact the n-type source layer 36, and an emitter-side gate electrode 60 surrounded by an insulating film 56 is provided in the trench 52.
  • an interlayer film 40 is provided covering a part of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 is provided covering the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.
  • an n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22.
  • a p-type collector layer 30B is provided on a part of the surface layer of the lower surface of the n-type buffer layer 26.
  • an n-type cathode layer 62C is provided on another part of the surface layer of the lower surface of the n-type buffer layer 26, and a collector-side n-type layer 34 is provided on a part of the surface layer of the lower surface of the p-type collector layer 30B.
  • an n-type cathode layer 62C is provided on the surface layer of the lower surface of the n-type buffer layer 26.
  • a collector-side gate electrode 58 is provided so as to contact the p-type collector layer 30B sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54 (or insulating film 54A) and not to reach the n-type pillar layer 22.
  • an interlayer film 38 is provided to cover the collector-side gate electrode 58.
  • a collector electrode 42 is provided to cover the p-type collector layer 30B, the interlayer film 38, and the n-type cathode layer 62C.
  • This configuration makes it possible to suppress the occurrence of high surge voltages in a semiconductor device having a superjunction structure.
  • the collector-side n-type layer 34 in the element region 12C and the n-type cathode layer 62C in the element region 12C and the termination region 14C are formed in the same process, the number of manufacturing steps can be reduced compared to when they are formed separately in separate processes.
  • each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, where one component corresponds to a part of a structure, and even where multiple components are provided in one structure.
  • each component in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320049A (ja) * 2000-05-09 2001-11-16 Fuji Electric Co Ltd 半導体装置およびその製造方法
JP2015195700A (ja) * 2014-03-27 2015-11-05 株式会社デンソー 駆動装置
JP2017054968A (ja) * 2015-09-10 2017-03-16 株式会社東芝 半導体装置及びその駆動方法
JP2018046255A (ja) * 2016-09-16 2018-03-22 株式会社東芝 半導体装置
JP2021150544A (ja) * 2020-03-19 2021-09-27 株式会社東芝 半導体装置及び半導体回路
JP2022075332A (ja) * 2020-11-06 2022-05-18 三菱電機株式会社 半導体装置
JP2022089710A (ja) * 2020-12-04 2022-06-16 国立大学法人 東京大学 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001320049A (ja) * 2000-05-09 2001-11-16 Fuji Electric Co Ltd 半導体装置およびその製造方法
JP2015195700A (ja) * 2014-03-27 2015-11-05 株式会社デンソー 駆動装置
JP2017054968A (ja) * 2015-09-10 2017-03-16 株式会社東芝 半導体装置及びその駆動方法
JP2018046255A (ja) * 2016-09-16 2018-03-22 株式会社東芝 半導体装置
JP2021150544A (ja) * 2020-03-19 2021-09-27 株式会社東芝 半導体装置及び半導体回路
JP2022075332A (ja) * 2020-11-06 2022-05-18 三菱電機株式会社 半導体装置
JP2022089710A (ja) * 2020-12-04 2022-06-16 国立大学法人 東京大学 半導体装置

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