WO2024098302A1 - 一种布线基板、发光基板及显示装置 - Google Patents

一种布线基板、发光基板及显示装置 Download PDF

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Publication number
WO2024098302A1
WO2024098302A1 PCT/CN2022/130968 CN2022130968W WO2024098302A1 WO 2024098302 A1 WO2024098302 A1 WO 2024098302A1 CN 2022130968 W CN2022130968 W CN 2022130968W WO 2024098302 A1 WO2024098302 A1 WO 2024098302A1
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Prior art keywords
pad
pads
row
functional units
pad group
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PCT/CN2022/130968
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English (en)
French (fr)
Inventor
刘纯建
田�健
张建英
雷杰
马亚军
徐佳伟
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Priority to PCT/CN2022/130968 priority Critical patent/WO2024098302A1/zh
Publication of WO2024098302A1 publication Critical patent/WO2024098302A1/zh

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  • the present disclosure relates to the technical field of display equipment, and in particular to a wiring substrate, a light-emitting substrate and a display device.
  • the present disclosure provides a wiring substrate, a light-emitting substrate and a display device.
  • the wiring substrate can greatly simplify the manufacturing process, thereby improving the product yield and significantly reducing the manufacturing cost.
  • a wiring substrate comprising: a plurality of functional units distributed in an array; each of the functional units comprises:
  • a plurality of first pad groups wherein the plurality of first pad groups are arranged at intervals along a first direction, and each of the first pad groups includes a first sub-pad and a second sub-pad arranged at intervals along a second direction;
  • a second pad group is located on one side of the plurality of first pad groups along a second direction, the second pad group includes a plurality of channel pads and at least two functional pads, the number of pads in the second pad group is an even number, and is distributed in an array interval in a 2*N manner;
  • the multiple channel pads are arranged in sequence along the same direction to form a first row, and are respectively connected one-to-one with the same number of multiple first pad groups; one of the at least two functional pads is located in the first row, and the functional pad is adjacent to only one of the multiple channel pads; the remaining functional pads of the at least two functional pads are arranged in the second row along the same direction.
  • it further comprises a plurality of routing groups arranged along the second direction, the number of the plurality of routing groups is the same as the number of columns of the functional units, and each group of the routing groups is correspondingly connected to a column of functional units;
  • Each group of the routing lines includes a plurality of connecting lines, a first type of routing lines and a second type of routing lines, wherein the plurality of connecting lines are used to connect the channel pads in a column of functional units to the second sub-pads in a one-to-one correspondence, the first type of routing lines are connected to the functional pads in a column of functional units, and the second type of routing lines are connected to the first sub-pads in a column of functional units;
  • the first type of routing and the second type of routing are arranged along the second direction and extend along the first direction, at least one routing of the first type passes through the gap between the first row and the second row of the second pad group in a column of functional units, and at least one routing of the second type passes through the gap between the first sub-pad and the second sub-pad in a column of functional units, so that each routing in the multiple routing groups is arranged on the same layer.
  • the plurality of channel pads are arranged adjacent to the second sub-pads in the plurality of first pad groups along the second direction, and an arrangement order of the channel pads matches an arrangement order of the corresponding first pad groups.
  • the at least two functional pads include a signal pad, an address input pad, an address output pad and at least one ground pad;
  • Any one of the signal pad, the address input pad and the address output pad is located in the first row of the second pad group, and at least one of the address input pad and the address output pad is adjacent to only one of the other pads in the row.
  • the first type of routing includes:
  • a signal line connected to all signal pads of a corresponding column of functional units
  • a grounding wire connected to the grounding pad in a corresponding column of functional units
  • a plurality of cascade lines wherein the plurality of cascade lines are used to cascade every two adjacent functional units in a column of functional units, wherein one end of the cascade line is connected to an address output pad of a preceding functional unit, and the other end of the cascade line is connected to an address input pad of a succeeding functional unit;
  • the address line is connected to the address input pad of the first functional unit in a corresponding column of functional units.
  • the extension directions of the first row and the second row of the second pad group are both in the first direction.
  • the signal pads are located in the first row of the second pad group;
  • the signal line is arranged through a gap between a first row and a second row of the second pad group;
  • the ground line is located at a side of the second pad group away from the first pad group.
  • the address input pad and the address output pad are each adjacent to only one of the other pads in the row;
  • the cascade line is located between two adjacent functional units in a column of functional units.
  • one of the address input pad and the address output pad is adjacent to only one of the other pads in the row;
  • the cascading line is disposed through a gap between a first row and a second row of the second pad group.
  • the extension directions of the first row and the second row of the second pad group are both the second direction.
  • one of the address input pad and the address output pad is located in the first row of the second pad group;
  • the cascade line is located between two adjacent functional units in a column of functional units.
  • the at least one ground pad is adjacent to a functional pad located in a first row of the second pad group;
  • the ground line is located at a side of the second pad group away from the plurality of first pad groups along the second direction;
  • the signal line is disposed through a gap between the first row and the second row of the second pads.
  • the signal pad is adjacent to a functional pad located in a first row of the second pad group;
  • the signal line is located at a side of the second pad group away from the plurality of first pad groups along the second direction;
  • the grounding line is disposed in a gap between the first row and the second row of the second pads.
  • the address line is located on a side of the second type of wiring away from the second pad group.
  • the second pad group includes two ground pads, and the two ground pads are adjacent to each other.
  • the plurality of first pad groups are divided into two categories, and first pad groups of the same category are arranged adjacent to each other;
  • the second type of routing includes two power lines, each of which is connected to a type of the first pad group in a column of functional units, one of which is located on a side of the multiple first pad groups away from the second pad group, and the other power line is arranged through a gap between a first sub-pad and a second sub-pad in the first pad group.
  • the present disclosure also provides a light-emitting substrate, comprising any one of the wiring substrates provided in the above technical solutions, and also comprising a plurality of light-emitting elements connected one-to-one with the first pad group and a plurality of driving elements connected one-to-one with the second pad group.
  • the present disclosure also provides a display device, comprising the light-emitting substrate provided in the above technical solution.
  • the embodiments of the present disclosure provide a wiring substrate, a display substrate and a display device, wherein the wiring substrate includes a plurality of identical functional units distributed in an array; each functional unit includes a plurality of first pad groups and a second pad group; the plurality of first pad groups are arranged at intervals along a first direction, and the second pad group is located on the same side of the plurality of first pad groups along a second direction; in the second pad group, a plurality of channel pads are sequentially arranged in a first row at intervals along the same direction, and are respectively connected one-to-one with a plurality of first pad groups of the same number in the functional unit, so that the routing connected to the first pad group, the routing connected between the first pad group and the second pad group, and the routing connected to the second pad group are sequentially arranged along the second direction, No overlap is beneficial for all traces to be arranged on the same layer; in the second pad group, one of at least two functional pads is located in the first row, and the functional pad is adjacent to only one channel
  • the number of functional pads is increased, and the positions of the functional pads are adjusted.
  • the types of signals received by the functional pads can be adjusted, and the shapes and extension directions of the traces connected to the second pad group can be changed, so that all traces in the wiring substrate are arranged on the same layer, and thus the functional units on the wiring substrate and the traces connected to the functional units can be single-layered, which can greatly simplify the process of manufacturing the wiring substrate, thereby improving the product yield, reducing the use of mask plates, and greatly reducing the manufacturing cost.
  • FIG1 is a schematic diagram of a connection structure of pads and traces on a light-emitting substrate in the related art
  • FIG2 is a schematic diagram of a connection structure of a functional unit and a wiring in the related art
  • FIG3 is a schematic diagram of the structure of a functional unit and wiring in the related art
  • FIG4 is a cross-sectional view along the cutting line AA′ in FIG3 ;
  • FIG5 is a schematic diagram of the structure of functional units and wiring on a wiring substrate provided by an embodiment of the present disclosure
  • FIG6 is a cross-sectional view along the cutting line BB′ in FIG5 ;
  • FIG7 is a cross-sectional view of a wiring substrate provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the structure of functional units and wiring on another wiring substrate provided by an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of connecting a first pad group and a second pad group provided by an embodiment of the present disclosure
  • 16 to 29 are schematic diagrams showing connections between a second pad group and a first type of trace provided by an embodiment of the present disclosure
  • FIG30 is a schematic diagram of the structure of a functional unit and its connected wiring provided in an embodiment of the present disclosure.
  • 31-32 are schematic diagrams of connection between a first pad group and a second type of routing provided in an embodiment of the present disclosure.
  • the light-emitting substrate includes a base substrate 01, M1*M2 functional units 02 arranged in an array on the base substrate, M1 address signal lines S, M1 address signal transfer lines Q, M2 data lines D, M2 ground lines G, M2 first power lines Va and M2 second power lines Vb, and multiple pixel units; as shown in Figure 1, it is a schematic diagram of the connection structure of the light-emitting substrate in an embodiment of the present disclosure, and as shown in Figure 2, it is a schematic diagram of the connection structure of a functional unit in an embodiment of the present disclosure.
  • the functional unit 02 includes multiple first pad groups 021 and a second pad group 022.
  • the second pad group 022 includes channel pads CH (for example, CH1, CH2, CH3), data signal pads Da, address pads Uc, and ground pads GND corresponding to the first pad group in the functional unit.
  • the channel pads can be connected to the first pad group 021 one by one through connecting traces 023.
  • the data signal pads Da, address pads Uc, and ground pads GND are functional pads.
  • Multiple pixel units 03 are connected to multiple functional units 02 in a one-to-one correspondence, and the pixel unit 03 includes multiple light-emitting elements 031 and a driving element 032.
  • the number of pads in the first pad group 021 in the functional unit is the same as the number of pins of the light-emitting element 031, and the pins of the light-emitting element 031 are connected to the pads in the first pad group 021 in the functional unit in a one-to-one correspondence.
  • the number of pads in the second pad group 022 in the functional unit is the same as the number of pins of the driving element 032, and the pins of the driving element 032 are connected to the pads in the second pad group 022 in the functional unit in a one-to-one correspondence, for driving the light-emitting element 031 to light up.
  • first direction F1 may be the row direction of the plurality of functional units arranged in an array
  • second direction F2 may be the column direction of the plurality of functional units arranged in an array
  • first direction F1 may be the column direction of the plurality of functional units arranged in an array
  • second direction F2 may be the row direction of the plurality of functional units arranged in an array, which is not limited here.
  • the first direction F1 is the column direction
  • the second direction F2 is the row direction.
  • the value of M1 is equal to the number of rows of the functional units
  • the value of M2 is equal to the number of columns of the functional units.
  • Each address signal line Si (0 ⁇ i ⁇ M1, i is a positive integer) is coupled to an address pad Uc in a second pad group of each functional unit arranged in a row in the second direction F2, for providing address data for the pixel unit.
  • Each address signal transfer line Qi (0 ⁇ i ⁇ M1, i is a positive integer) corresponds to the address signal line Si one by one;
  • Each data line Dj (0 ⁇ j ⁇ M2, j is a positive integer) is coupled to the data signal pad Da of each second pad group of a column of functional units arranged in the first direction F1, and is used to provide for the pixel unit.
  • a ground line Gj (0 ⁇ j ⁇ M2, j is a positive integer) is coupled to the ground pad GND of each second pad group of a column of functional units arranged in the first direction F1, and is used to provide a ground voltage signal for the pixel unit;
  • the first power line Vaj and the second power line Vbj are coupled to a row of first pad groups arranged in the first direction F1; the second sub-pads of each first pad group in the functional unit are respectively coupled to each signal channel pad CH of the second pad group.
  • the address selection information is transmitted to the address pad through each address signal line in turn, and the address selection information includes the address ID of the corresponding pixel row, so that the driving element 032 obtains a specific address ID respectively;
  • the data information is transmitted to each pixel column respectively through each data line; the data information includes the address ID and pixel data information corresponding to all the driving elements in a certain pixel column, so that each driving element can accurately obtain the pixel data information matching its own address ID, and the pixel data information is parsed and subpacked to form an electrical signal for controlling the connected light-emitting unit respectively, thereby realizing an active addressing driving method.
  • the light-emitting substrate specifically includes a base substrate 01, a buffer layer 04, a first metal wiring layer 05, a first insulating layer 061, a first flat layer 071, a second insulating layer 062, a second metal wiring layer 08, a third insulating layer 063, a second flat layer 072 and a fourth insulating layer 064 during the manufacturing process, wherein, as shown in Figure 3, the above-mentioned M1 address signal transfer lines Q, M2 data lines D, M2 ground lines G, M2 first electric lines 064, The source line Va, M2 second power lines Vb, etc.
  • Each routing in the first metal routing layer 05 is connected to the first pad group 021 and the second pad group 022 of the functional unit in the second metal routing layer 08 through the first through hole 091 penetrating the first insulating layer 061, the first flat layer 071, and the second insulating layer 062.
  • the light-emitting element can be connected to the first pad group 021 and the second pad group 022 in the functional unit through the second through hole 092 penetrating the third insulating layer 063, the second flat layer 071 and the fourth insulating layer 064.
  • each pad in the functional unit 02 and the connected routing are an integrated structure, each pad is a portion of the second metal routing layer 08 exposed by the second through hole 092 formed on the third insulating layer 063 , the second flat layer 071 and the fourth insulating layer 064 , and the routing in the second metal routing layer 08 is a portion covered and protected by the third insulating layer 063 , the second flat layer 071 and the fourth insulating layer 064 .
  • the structure of the double-layer metal wiring layer needs to go through multiple patterning processes during the manufacturing process, specifically, for example, including: (1) patterning the first metal wiring layer 05; (2) patterning the first insulating layer 061 and the first flat layer 071; (3) patterning the second insulating layer 062; (4) patterning the second metal wiring layer 08; (5) patterning the third insulating layer 063 and the second flat layer 072; (6) patterning the fourth insulating layer 064. It can be seen that the manufacturing process of the double-layer metal wiring layer is complicated, which may result in low product yield and high cost.
  • the present disclosure provides a wiring substrate, as shown in FIG. 5 and FIG. 6 , including: a plurality of functional units 31 distributed in an array; each functional unit 31 includes:
  • a second pad group 312, the second pad group 312 is located on one side of the plurality of first pad groups 311 along the second direction F2, the second pad group 312 includes a plurality of channel pads Ch and at least two functional pads Gn, the number of pads in the second pad group 312 is an even number, and is distributed in an array interval in a 2*N manner;
  • multiple channel pads Ch are arranged in sequence along the same direction to form a first row 3121, and are respectively connected one-to-one with the same number of multiple first pad groups 311; one functional pad Gn of at least two functional pads Gn is located in the first row 3121, and the functional pad Gn is only adjacent to one channel pad Ch of the multiple channel pads Ch; the remaining functional pads Gn of at least two functional pads are arranged in the second row 3122 along the same direction.
  • the wiring substrate provided in the embodiment of the present disclosure includes a plurality of identical functional units 31 distributed in an array; each functional unit 31 includes a plurality of first pad groups 311 and a second pad group 312; the plurality of first pad groups 311 are arranged at intervals along a first direction F1, and the second pad group 312 is located on the same side of the plurality of first pad groups 311 along a second direction F2; in the second pad group 312, a plurality of channel pads Ch are sequentially arranged in a first row 3121 at intervals along the same direction, and are respectively connected one-to-one with a plurality of first pad groups 311 of the same number in the functional unit 31 where they are located, so that the routing connected to the first pad group 311, the routing connected between the first pad group 311 and the second pad group 312, and the routing connected to the second pad group 312 are sequentially arranged along the second direction F2 without overlapping, which is conducive to making all the routings arranged on the same layer; in the second pad group 312, one of the
  • the number of functional pads Gn is increased, and the position of the functional pads Gn is adjusted.
  • the type of signal received by the functional pad Gn can be adjusted, and the shape and extension direction of the routing connected to the second pad group 312 can be changed, so that all routings in the wiring substrate are set on the same layer, and then the functional unit 31 on the wiring substrate and the routing connected to the functional unit 31 can realize single-layer wiring, which can greatly simplify the process of manufacturing the wiring substrate, thereby improving the product yield, and can reduce the use of mask plates, greatly reducing the production cost.
  • the wiring substrate includes a base substrate 1, a buffer layer 2, a metal wiring layer 3 and an insulating layer 4 which are stacked in sequence.
  • the manufacturing process of the wiring substrate only needs to undergo two mask processes, specifically including: (1) patterning the metal wiring layer 3 to form a metal wiring; (2) patterning the insulating layer 4 to form an opening 41, and the opening 41 on the insulating layer 4 can define the pad in the functional unit 31 in the preset area of the metal wiring.
  • the pixel unit can be connected to the part of the metal wiring exposed at the opening 41 through the opening 41.
  • the pixel unit can include multiple light-emitting elements and driving elements.
  • the light-emitting element can be connected to the first pad group 311, and the driving element can be connected to the second pad group 312. It can be seen that the structure of the wiring substrate provided in the present disclosure can greatly simplify the process of the wiring substrate.
  • the pins of the light-emitting element are rectangular, with the width of the wide side ranging from 30 to 50 ⁇ m, and the length of the long side ranging from 50 to 75 ⁇ m.
  • the length and width of the first sub-pad P1 and the second sub-pad P2 in the corresponding first pad group 311 are 2 to 30 ⁇ m larger than the length and width of the pins of the light-emitting element;
  • the pins of the driving element are rectangular, with the width of the wide side generally ranging from 30 to 50 ⁇ m, and the length of the long side ranging from 45 to 70 ⁇ m.
  • the length and width of the pads in the corresponding second pad group 312 are 2 to 30 ⁇ m larger than the length and width of the pins of the driving element.
  • the gap width d1 between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311 can be 50 to 200 ⁇ m, and the gap width d2 between the two rows in the second pad group 312 can be 50 to 200 ⁇ m. Since the position distribution of the first pad group determines the position distribution of the subsequent light-emitting elements, and the position distribution of the light-emitting elements has a decisive influence on the display effect, when the position of the first pad group 311 is determined, the position of the second pad group 312 must not only consider the design requirements of the routing, but also take into account the distance between the second pad group 312 and the first pad group 311. The distance d3 between the second pad group 312 and the first pad group 311 is greater than or equal to 100 ⁇ m, which can meet the space requirements for repairing the light-emitting elements.
  • the wiring substrate may include a plurality of routing groups 32 arranged along the second direction F2, the number of the plurality of routing groups 32 being the same as the number of columns of the functional units 31, and each routing group 32 being connected to a column of the functional units 31; specifically, each routing group 32 includes a plurality of connecting wires 321, a first type of routing wire 322, and a second type of routing wire 323, the connecting wire 321 being used to connect the channel pads Ch in a column of the functional units 31 to the second sub-pads P2 respectively in a one-to-one correspondence, the first type of routing wire 322 being connected to the functional pads Gn in a column of the functional units 31, and the second type of routing wire 323 being connected to the first sub-pads P1 in a column of the functional units 31; wherein the first type of routing wire 322 and the second type of routing wire 323 are arranged along the second direction F2 and extend along the first direction F1, so that the first type of routing wire 3
  • routing lines of the first type of routing line 322 and the second type of routing line 323 By passing some of the routing lines of the first type of routing line 322 and the second type of routing line 323 through the gap between the pads, all the routing lines in the routing group 32 can be arranged on the same layer, thereby simplifying the structure of the wiring substrate, reducing the difficulty of production, and thus reducing production costs.
  • the distance d4 between two adjacent lines in the first type of lines 322 and the second type of lines 323 can be 5 ⁇ m to 100 ⁇ m, which can be set according to actual conditions.
  • the width of the lines in the first type of lines 322 and the second type of lines 323 varies according to different line functions, and the required line width of the lines is also different, which needs to be set according to actual conditions and is not limited here.
  • the extension direction of the two rows of pads of the second pad group 312 in a functional unit 31 can extend along the first direction F1, as shown in Figures 5 and 6; or, it can also extend along the second direction F2, as shown in Figures 8 and 9, that is, the second pad group 312 in Figures 5 and 6 is rotated 90 degrees counterclockwise.
  • the extension direction of the two rows of pads in the second pad group 312 it is necessary to adaptively adjust the specific position of each pad in the second pad group 312 and the specific direction of each routing line, and those skilled in the art can determine it according to the actual situation according to the method of the embodiment of the present disclosure.
  • each functional unit 31 multiple channel pads Ch are arranged along the second direction F2 adjacent to the second sub-pads P2 in the multiple first pad groups 311, so that the connecting lines connecting the second sub-pads P2 and the channel pads Ch are located between the first pad group 311 and the second pad group 312 of the functional unit 31, and the arrangement order of the channel pads Ch matches the arrangement order of the corresponding first pad groups 311, so that the second sub-pads P2 in each group of corresponding first pad groups 311 and the channel pads Ch in the second pad group 312 can be connected in sequence, and each connecting wire 321 can be arranged on the same layer as the first type of wire 322 and the second type of wire 323, and are insulated from each other without crossing.
  • a functional unit 31 may specifically include a first pad group 3111 for connecting to a red light-emitting element, a first pad group 3112 for connecting to a green light-emitting element, and a first pad group 3113 for connecting to a blue light-emitting element.
  • the second pad group 312 of the functional unit 31 includes a first channel pad Ch1 connected to the first pad group 3111, a second channel pad Ch2 connected to the first pad group 3112, and a third channel pad Ch3 connected to the first pad group 3113. As shown in FIG.
  • two rows of the second pad group 312 of the functional unit 31 extend along the first direction F1, and the first row 3121 of the second pad group 312 of the functional unit 31 is located on a side of the second pad group 312 adjacent to the first pad group 311, so that the first channel pad Ch1, the second channel pad Ch2 and the third channel pad Ch3 are arranged adjacent to the first pad group 311, the first pad group 3111, the first pad group 3112 and the first pad group 3113 are arranged in the first direction F1, and the arrangement order of the first channel pad Ch1, the second channel pad Ch2 and the third channel pad Ch3 in the first direction F1 is the same as the arrangement order of the first pad group 3111, the first pad group 3112 and the first pad group 3113 in the first direction F1, so that the three correspondingly connected connection lines are arranged in sequence, insulated from each other and without crossing.
  • the first pad group 3111, the first pad group 3112, and the first pad group 3113 are arranged in sequence in the first direction F1, and the first channel pad Ch1, the second channel pad Ch1, and the third channel pad Ch1 in the second pad group 312 are arranged in sequence in the first direction F1; or, as shown in FIG11, the positions of the first pad group 3111 and the first pad group 3113 in FIG10 are interchanged, and the positions of the corresponding first channel pad Ch1 and the third channel pad Ch3 are also interchanged; or, as shown in FIG12, the positions of the first channel pad 3112 and the first channel pad 3113 in FIG10 are interchanged, and the positions of the corresponding second channel pad Ch2 and the third channel pad Ch3 are also interchanged; in addition, as shown in FIG13, the positions of the three channel pads Ch in the first row 3121 of the second pad group 312 and the positions of the functional pads Gn can also be interchanged. Specifically, the arrangement of the plurality of first pad groups 3
  • the extension direction of the two rows of pads in the second pad group 312 of the functional unit 31 can also be the second direction F2, and the channel pad Ch in the second pad group 312 can be located in the first row 3121 adjacent to the first pad group 311, and the first pad group 3111, the first pad group 3112, and the first pad group 3113 are arranged in sequence in the first direction F1, and the first channel pad Ch1, the second channel pad Ch1, and the third channel pad Ch1 in the second pad group 312 are arranged in sequence in the second direction F2; or, the order between the three first pad groups can be interchanged, and the positions between the corresponding three channel pads Ch are also interchanged to achieve the purpose of the same arrangement order.
  • the upper and lower positions of the first row 3121 and the second row 3122 of the second pad group 312 can also be interchanged, and the positions of the corresponding three channel pads Ch also need to be adjusted accordingly.
  • the arrangement of multiple first pad groups 311 and multiple channel pads Ch can be determined according to actual conditions.
  • At least two functional pads Gn may include a signal pad Vc, an address input pad D-in, an address output pad D-out and at least one ground pad GND; wherein, any one of the signal pad Vc, the address input pad D-in and the address output pad D-out may be located in the first row 3121 of the second pad group 312, and at least one of the address input pad D-in and the address output pad D-out is only adjacent to one of the other pads in the row, which can facilitate wiring at the end of the second pad group 312, and is conducive to the arrangement of the single-layer metal routing layer 3.
  • the functions of the data signal pad Da and the address pad Uc in the double-layer metal wiring layer 3 in the related technology are replaced by the address input pad D-in, the address output pad D-out, and the data signal pad Vc respectively, and the functions of the pins of the corresponding driving elements connected to the second pad group 312 also need to be redefined.
  • the setting of the single-layer metal wiring layer 3 on the wiring substrate can be realized by adjusting the logic control circuit and function inside the driving element.
  • At least one ground pad GND in the second pad group 312 may include two, and the two ground pads GND may be arranged adjacent to each other in the second row 3122 of the second pad group 312, so as to facilitate connection with the corresponding routing Gd.
  • the specific layout structure on the corresponding wiring substrate in Figure 16 can be as shown in Figures 5 and 6, and the above-mentioned first type of routing 322 may include: a signal line Vcc, a ground line Gd, a plurality of cascade lines L, and an address line Addr; wherein the signal line Vcc is connected to all signal pads Vc in a corresponding column of functional units 31, the ground line Gd is connected to the ground pad GND in a corresponding column of functional units 31, and the plurality of cascade lines L are used to cascade every two adjacent functional units 31 in a column of functional units 31, one end of the cascade line L is connected to the address output pad D-out of the previous functional unit 31, and the other end is connected to the address input pad D-in of the next functional unit 31; the address line Addr is connected to the address input pad D-in of the first functional unit 31 in the corresponding column of functional units 31.
  • the signal line Vcc connected to the signal pad Vc of a column of functional units 31 is used to provide data including address information and luminous information
  • the address line Addr and multiple cascade lines L are used to provide specific address information.
  • the signal transmitted in the signal line Vcc is a power carrier signal, that is, it includes a power signal that provides a working voltage for the driving element, and is loaded with an address data signal and a light-emitting data signal.
  • Each driving element matches the light-emitting data that is the same as its own address information from the data transmitted by the signal line Vcc, and then undergoes internal processing and calculation of the driving element, and controls the driving element and the light-emitting element to form a signal path through the connecting line, so that the light-emitting element presents a specific grayscale brightness, which is different from the driving method of the light-emitting substrate in the related art.
  • the extension directions of the first row 3121 and the second row 3122 of the second pad group 312 may extend in different directions, so that the wiring layout of the wiring substrate obtained is also different.
  • the extension direction of the first row 3121 and the second row 3122 of the second pad group 312 may both be the first direction F1.
  • the pads and wiring layout in each functional unit 31 may be arranged according to the following structure.
  • the signal pad Vc can be located in the first row 3121 of the second pad group 312, and is located in the same row as the multiple channel pads Ch; the signal line Vcc can be arranged through the gap between the first row 3121 and the second row 3122 in the second pad group 312; the ground line Gd can be located on the side of the second pad group 312 away from the first pad group 311, which can avoid interference between the signal line Vcc and the ground line Gd and other routing lines, thereby achieving the same-layer arrangement.
  • the arrangement positions of the signal pad Vc and the multiple channel pads Ch can be exchanged.
  • the specific order of the signal pad Vc and the multiple channel pads Ch is not limited here and can be determined according to actual conditions.
  • the arrangement method of the multiple channel pads Ch can be any one of the above-mentioned technical solutions, which is not limited here and can be determined according to actual conditions.
  • the address input pad D-in and the address output pad D-out are only adjacent to one of the other pads in the row, that is, the address input pad D-in and the address output pad D-out are all located at the end of the second row 3122 of the second pad group 312; in this way, the cascade line L can be located between two adjacent functional units 31 in a column of functional units 31 to avoid interference with other routing lines.
  • the second pad group 312 it can also be arranged that one of the address input pad D-in and the address output pad D-out is adjacent to only one of the other pads in the row, that is, one of the address input pad D-in and the address output pad D-out is located at the end of the second row 3122 of the second pad group 312, and the other is sandwiched between the two pads; in this way, in order to avoid interference between the cascade line L and other routing lines, the cascade line L can be arranged to pass through the gap between the first row 3121 and the second row 3122 in the second pad group 312.
  • the arrangement layout of each pad in the second pad group 312 of the functional unit 31 can not only be set as shown in FIG. 18 , but also can be other various implementations.
  • the positions of the address input pad D-in and the address output pad D-out in FIG18 are interchanged; or, as shown in FIG20, the position of the ground pad GND in FIG18 is interchanged with the position of the address input pad D-in and the address output pad D-out; or, as shown in FIG21, the positions of the address input pad D-in and the address output pad D-out in FIG20 are interchanged; or, as shown in FIG22, the positions of the multiple channel pads Ch in FIG20 are interchanged with the position of the signal pad Vc; or, as shown in FIG23, the positions of the address input pad D-in and the address output pad D-out in FIG22 are interchanged; or, as shown in FIG24, the position of the ground pad GND in FIG22 is interchanged with the position of the address input pad D-in and the address output
  • each functional unit 31 the extension direction of the first row 3121 and the second row 3122 of the second pad group 312 may also be the second direction F2.
  • the pads and routing layout in each functional unit 31 may be arranged according to the following structure.
  • the specific layout structure on the corresponding wiring substrate in FIG26 may be as shown in FIG8 and 9 , where, in each functional unit 31, one of the address input pad D-in and the address output pad D-out is located in the first row 3121 of the second pad group 312, that is, one of the address input pad D-in and the address output pad D-out needs to be arranged at the end of the second pad group 312 away from the first pad group 311; in this way, the other of the address input pad D-in and the address output pad D-out is located in the second row 3122 of the second pad group 312, and the cascade line L may be located between two adjacent functional units 31 in a column of functional units 31, so as to avoid interference between the cascade line L and other routings.
  • At least one ground pad GND can be set adjacent to the functional pad Gn located in the first row 3121 of the second pad group 312; in this way, the ground line Gd can be located on the side of the second pad group 312 away from the multiple first pad groups 311 along the second direction F2 to avoid interference with other routing lines; the signal line Vcc can be set to pass through the gap between the first row 3121 and the second row 3122 of the second pad to avoid interference with other routing lines.
  • the signal pad Vc in the second pad group 312 can be sandwiched between two pads in the second row 3122, and the signal line Vcc can pass through the gap between the first row 3121 and the second row 3122 of the second pad group 312 from the side of the second pad group 312 away from the first pad group 311, so that the cascade line L and the signal line Vcc do not interfere with each other; or, as shown in Figure 28, the signal pad Vc in the second pad group 312 can also be located at the end of the second row 3122, and the signal line Vcc can pass through the gap between the function pad Gn and the channel pad Ch in the first row 3121 of the second pad group 312 and the gap between the second row 3122 and the first row 3121.
  • a signal pad Vc can also be set adjacent to a functional pad Gn located in the first row 3121 of the second pad group 312; the signal line Vcc can be located on the side of the second pad group 312 away from the plurality of first pad groups 311 along the second direction F2; and the ground line Gd can be located in the gap between the first row 3121 and the second row 3122 of the second pad.
  • the above-mentioned address line Addr can be located on the side of the second type of routing 323 away from the second pad group 312, and the address line Addr can be connected to the address input pad D-in of the first functional unit 31 in a column of functional units 31 through the routing located on one side of the functional unit 31 array.
  • the minimum line width of the above-mentioned cascade line L, address line Addr and signal line Vcc can be 30 ⁇ m, and the minimum line width of the ground line Gd can be 150 ⁇ m.
  • the ground line Gd can be set on the side of the second pad group 312 away from the first pad group 311, which can ensure the line width of the ground line Gd.
  • the minimum line width requirement of the signal line Vcc or the cascade line L is small, so that the signal line Vcc or the cascade line L can be set through the gap between the first row 3121 and the second row 3122 in the second pad group 312.
  • the signal line Vcc and the cascade line L passing through the gap in the second pad group 312 can include a first main body located outside the area where the second pad group 312 is located and a first crossing portion passing through the second pad group 312. Since the gap width between the two rows of pads in the second pad group 312 is limited, the line width of the first crossing portion can be set smaller than the line width of the first main body.
  • the gap between two rows of pads in the second pad group 312 can be 50 to 200 ⁇ m, then the line width d51 of the first main portion of the signal line Vcc or the cascade line L can be set to be greater than or equal to 30 ⁇ m, and the line width d52 of the first crossing portion of the signal line Vcc or the cascade line L can be set to be greater than or equal to 5 ⁇ m; if the signal line Vcc and the cascade line L are both located between the two rows of gaps in the second pad group 312, then the line spacing between the signal line Vcc and the cascade line L can be 5 to 20 ⁇ m, and the specific size can be determined based on the actual process capability.
  • each functional unit 31 a plurality of first pad groups 311 are divided into two categories, and first pad groups 311 of the same category are arranged adjacent to each other; specifically, as shown in FIGS. 31 and 32, each functional unit 31 may include a first pad group 3111 for connecting to a red light-emitting element, a first pad group 3112 for connecting to a green light-emitting element, and a first pad group 3113 for connecting to a blue light-emitting element, wherein the light-emitting element is generally a light-emitting diode (LED).
  • LED light-emitting diode
  • the photoelectric characteristics of a green light-emitting diode and a blue light-emitting diode are substantially the same, while the photoelectric characteristics of a red light-emitting diode are different from those of a blue light-emitting diode or a green light-emitting diode. Therefore, the power supply voltage required to be loaded on the red light-emitting diode is different from the power supply voltage required to be loaded on the green light-emitting diode and the blue light-emitting diode.
  • the first pad group 3111 can be used as a first-category first pad group, and the first pad group 3112 and the first pad group 3113 can be used as a second-category first pad group, and the first pad group 3112 and the first pad group 3113 are arranged adjacent to each other;
  • the second type of routing 323 may include two power lines, each power line is connected to a type of first pad group 311 in a column of functional units 31, one power line is located on a side of the multiple first pad groups 311 away from the second pad group 312, and the other power line is set through the gap between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311.
  • the second type of wiring 323 may include a first power line Ve and a second power line Vf, the first power line Ve is connected to the first sub-pad P1 of the first pad group 3111 in a column of functional units 31, and the second power line Vf is connected to the first pad group 3112 and the first pad group 3113 in a column of functional units 31.
  • the specific layout structure on the corresponding wiring substrate may be as shown in FIG5 and FIG6, the first power line Ve may be located on the side of the plurality of first pad groups 311 away from the second pad group 312, and the second power line Vf may be arranged through the gap between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311; or, as shown in FIG32, the second power line Vf may be located on the side of the plurality of first pad groups 311 away from the second pad group 312, and the first power line Ve may be arranged through the gap between the first sub-pad P1 and the second sub-pad P2 in the first pad group 311.
  • the minimum width of the first power line Ve can be 100 ⁇ m, and the minimum width of the second power line Vf can be 50 ⁇ m.
  • the power line passing through the gap between the first sub-pad P1 and the second sub-pad P2 can include a second main body portion located outside the area where the first pad group 311 is located and a second crossing portion located between the first sub-pad P1 and the second sub-pad P2. Since the width of the gap between the first sub-pad P1 and the second sub-pad P2 is limited, the line width of the second crossing portion can be set to be smaller than the line width of the first main body portion. For example, as shown in FIG.
  • the second power line Vf is set to pass through the gap between the first sub-pad P1 and the second sub-pad P2, then the line width d61 of the second main body portion of the second power line Vf can be 100 ⁇ m, and the line width d62 of the second crossing portion of the second power line Vf can be greater than or equal to 20 ⁇ m.
  • the specific size can be not limited here and can be determined according to actual conditions.
  • the embodiment of the present disclosure also provides a light-emitting substrate, including any one of the wiring substrates provided in the above technical solutions, and also including a plurality of light-emitting elements connected one-to-one with the first pad group and a plurality of driving elements connected one-to-one with the second pad group.
  • only one metal routing layer is provided in the wiring substrate, which can simplify the manufacturing process, can greatly simplify the manufacturing process, thereby improving the product yield, and can reduce the use of mask plates, thereby significantly reducing the manufacturing cost.
  • the manufacturing process of the light-emitting substrate may be:
  • Step 1 A buffer layer is formed on the substrate by a sputtering process, which can reduce the stress effect of the metal wiring layer formed in the next step on the substrate, thereby reducing the warping of the substrate.
  • the substrate can be a glass substrate.
  • Step 2 Make a metal wiring layer on top of the buffer layer through the process of sputtering, cleaning, gluing, baking, exposure, development, hard baking, etching, and stripping.
  • this metal wiring layer can also be completed through the electroplating process;
  • Step 3 Make an insulating layer through the process of sputtering, exposure and development;
  • Step 4 Perform nickel-gold treatment on the portion of the metal wiring layer exposed in the opening on the insulating layer;
  • Step 5 Apply white oil on the insulation layer
  • the sixth step is to carry out processes such as die bonding, that is, to connect the light-emitting element and the driving element in the pixel unit to the pads in the metal wiring layer through the opening.
  • the light emitting element may be a sub-millimeter light emitting diode (micro light emitting diode) or a micro light emitting diode (Micro LED), which is not limited here.
  • the driving element may be a driving chip, which is set according to actual conditions and is not limited here.
  • the present disclosure also provides a display device, comprising the light-emitting substrate provided in the above technical solution.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种布线基板，该布线基板包括呈阵列分布的功能单元（31）；每个功能单元（31）包括：多个第一焊盘组（311），沿第一方向排布；第二焊盘组（312），沿第二方向位于多个第一焊盘组（311）的一侧，第二焊盘组（312）包括多个通道焊盘、至少两个功能焊盘，焊盘个数为偶数，以2*N的方式阵列分布；多个通道焊盘沿同一方向依次设置成第一排且分别与相同数目的多个第一焊盘组（311）一一对应连接；至少两个功能焊盘中的一个功能焊盘位于第一排，且该功能焊盘仅与多个通道焊盘中的一个通道焊盘相邻；至少两个功能焊盘中的其余功能焊盘沿同一方向间隔设置成第二排。该布线基板能简化工艺制程，提高产品良率，降低制作成本。还提供了一种发光基板包括该布线基板以及一种显示装置包括该发光基板。

Description

一种布线基板、发光基板及显示装置 技术领域
本公开涉及显示设备技术领域，特别涉及一种布线基板、发光基板及显示装置。
背景技术
目前玻璃基Mini-LED显示技术趋近成熟，越来越多的面板厂转型制作Mini-LED显示面板。随着技术越来越成熟，成本降低，竞争也越发激烈，对于玻璃基Mini-LED直显设备的Back plane灯板(简称BP灯板)，目前主流的工艺制程还是双层铜、6道mask工艺制程，即设置两层金属走线层。灯板上这种双层铜工艺，制程复杂，良率较低，成本高。
发明内容
本公开提供了一种布线基板、发光基板及显示装置，上述布线基板能够大大简化制作工艺制程，进而能够提高产品良率，大幅度降低制作成本。
为达到上述目的，本公开提供以下技术方案：
一种布线基板，包括：呈阵列分布的多个功能单元；每个所述功能单元包括：
多个第一焊盘组，多个所述第一焊盘组沿第一方向间隔排布，每个所述第一焊盘组包括沿第二方向间隔排列的第一子焊盘和第二子焊盘；
第二焊盘组，所述第二焊盘组沿第二方向位于所述多个第一焊盘组的一侧，所述第二焊盘组包括多个通道焊盘、至少两个功能焊盘，所述第二焊盘组中的焊盘个数为偶数，以2*N的方式阵列间隔分布；
其中，所述多个通道焊盘沿同一方向依次间隔设置成第一排、且分别与相同数目的多个第一焊盘组一一对应连接；所述至少两个功能焊盘中的一个功能焊盘位于所述第一排，且该功能焊盘仅与所述多个通道焊盘中的一个通 道焊盘相邻；所述至少两个功能道焊盘中的其余功能焊盘沿同一方向间隔设置成第二排。
可选地，还包括沿第二方向排布的多个走线组，所述多个走线组的数目与所述功能单元的列数相同，每组所述走线组与一列功能单元对应连接；
每组所述走线组包括多条连接线、第一类走线以及第二类走线，所述多条连接线用于将一列功能单元中的通道焊盘与第二子焊盘一一对应连接，所述第一类走线与一列功能单元中的功能焊盘连接，所述第二类走线与一列功能单元中的第一子焊盘连接；
其中，所述第一类走线和第二类走线沿第二方向排列且沿第一方向延伸，所述第一类走线中至少一条走线穿过一列功能单元中所述第二焊盘组的第一排与第二排之间的间隙设置，所述第二类走线中至少一条走线穿过一列功能单元中第一子焊盘与第二子焊盘之间的间隙设置，以使所述多个走线组中的各条走线同层设置。
可选地，每个所述功能单元中，所述多个通道焊盘沿第二方向邻近所述多个第一焊盘组中的第二子焊盘设置，所述通道焊盘的排列顺序与对应的所述第一焊盘组的排列顺序相配合。
可选地，每个所述功能单元中，所述至少两个功能焊盘包括信号焊盘、地址输入焊盘、地址输出焊盘以及至少一个接地焊盘；
所述信号焊盘、地址输入焊盘和所述地址输出焊盘中的任意一个位于所述第二焊盘组的第一排，所述地址输入焊盘和所述地址输出焊盘中至少一个仅与所在排的其他焊盘中的一个相邻。
可选地，所述第一类走线包括：
信号线，所述信号线与对应的一列功能单元中的所有信号焊盘连接；
接地线，所述接地线与对应的一列功能单元中的所述接地焊盘连接；
多条级联线，所述多条级联线用于将一列功能单元中每相邻的两个功能单元级联，所述级联线的一端连接前一个功能单元的地址输出焊盘、另一端连接后一个功能单元的地址输入焊盘；
地址线，所述地址线与对应的一列功能单元中首个功能单元的地址输入焊盘连接。
可选地，每个所述功能单元中，所述第二焊盘组的第一排和第二排的延伸方向均为第一方向。
可选地，每个所述功能单元中，所述信号焊盘位于所述第二焊盘组的第一排；
所述信号线穿过所述第二焊盘组中第一排和第二排之间的间隙设置；
所述接地线位于所述第二焊盘组远离所述第一焊盘组的一侧。
可选地，所述第二焊盘组中，所述地址输入焊盘与所述地址输出焊盘均仅与所在排的其他焊盘中的一个相邻；
所述级联线位于一列功能单元中相邻的两个功能单元之间。
可选地，所述第二焊盘组中，所述地址输入焊盘与所述地址输出焊盘中一个焊盘仅与所在排的其他焊盘中的一个相邻；
所述级联线穿过所述第二焊盘组中第一排和第二排之间的间隙设置。
可选地，每个所述功能单元中，所述第二焊盘组的第一排和第二排的延伸方向均为第二方向。
可选地，每个所述功能单元中，所述地址输入焊盘和所述地址输出焊盘中的一个焊盘位于所述第二焊盘组的第一排；
所述级联线位于一列功能单元中相邻的两个功能单元之间。
可选地，每个所述功能单元中，所述至少一个接地焊盘与位于所述第二焊盘组的第一排的功能焊盘相邻；
所述接地线位于所述第二焊盘组沿第二方向远离多个第一焊盘组的一侧；
所述信号线穿过所述第二焊盘的第一排与第二排之间的间隙设置。
可选地，每个所述功能单元中，所述信号焊盘与位于所述第二焊盘组的第一排的功能焊盘相邻；
所述信号线位于所述第二焊盘组沿第二方向远离多个第一焊盘组的一侧；
所述接地线位于所述第二焊盘的第一排与第二排之间的间隙设置。
可选地，所述地址线位于所述第二类走线远离所述第二焊盘组的一侧。
可选地，所述第二焊盘组包括两个接地焊盘，所述两个接地焊盘相邻设置。
可选地，每个所述功能单元中，所述多个第一焊盘组分为两类，相同类的第一焊盘组相邻设置；
所述第二类走线包括两条电源线，每条所述电源线与一列功能单元中一类所述第一焊盘组连接，其中一条电源线位于所述多个第一焊盘组远离所述第二焊盘组的一侧，另一条电源线穿过所述第一焊盘组中第一子焊盘和第二子焊盘之间的间隙设置。
本公开还提供一种发光基板，包括上述技术方案中提供的任意一种布线基板，还包括与第一焊盘组一一对应连接的多个发光元件以及与第二焊盘组一一对应连接的多个驱动元件。
本公开还提供一种显示装置，包括上述技术方案中提供的发光基板。
本公开实施例提供一种布线基板、显示基板及显示装置，该布线基板中包括呈阵列分布的多个相同的功能单元；每个功能单元包括多个第一焊盘组和第二焊盘组；多个第一焊盘组沿第一方向间隔排布，第二焊盘组沿第二方向位于多个第一焊盘组的同一侧；第二焊盘组中，多个通道焊盘沿同一方向依次间隔设置成第一排、且分别与所在的功能单元中相同数目的多个第一焊盘组一一对应连接，能够使得与第一焊盘组连接的走线、第一焊盘组与第二焊盘组之间连接的走线、以及与第二焊盘组连接的走线沿第二方向依次排列、不交叠，有利于使得各条走线均设置在同一层；第二焊盘组中，至少两个功能焊盘中的一个功能焊盘位于第一排，且该功能焊盘仅与多个通道焊盘中的一个通道焊盘相邻，即第二焊盘组的第一排的端部设置一个功能焊盘，至少两个功能焊盘中的其余功能焊盘沿同一方向间隔设置成第二排，与相关技术中技术方案相比，第二焊盘组中，增加了功能焊盘的数目，并对功能焊盘的位置进行了调整，同时可以调整功能焊盘的所接收信号的类型，改变与第二焊盘组连接的走线的形状以及延伸方向，可以实现布线基板中各条走线均设 置在同一层，进而能够使得布线基板上的功能单元和功能单元连接的走线实现单层布线，能够大大简化制作布线基板的工艺制程，进而能够提高产品良率，并且能够减少掩膜板的使用量，大幅度降低制作成本。
附图说明
图1为相关技术中发光基板上焊盘和走线的连接结构示意图；
图2为相关技术中一个功能单元与走线的连接结构示意图；
图3为相关技术中一个功能单元与走线的结构示意图；
图4为图3中沿剖切线AA’的剖面图；
图5为本公开实施例提供的一种布线基板上功能单元与走线的结构示意图；
图6为图5中沿剖切线BB’的剖面图；
图7为本公开实施例提供的一种布线基板的截面图；
图8为本公开实施例提供的另一种布线基板上功能单元与走线的结构示意图；
图9为本公开实施例提供的一个第一焊盘组和第二焊盘组的连接示意图；
图10-图15为本公开实施例提供的一种功能单元中焊盘排布示意图；
图16-图29为本公开实施例提供的一种第二焊盘组与第一类走线的连接示意图；
图30为本公开实施例提供的一个功能单元及其连接的走线的结构示意图；
图31-图32为本公开实施例提供的一种第一焊盘组与第二类走线的连接示意图。
图标：
1-衬底基板；2-缓冲层；3-金属走线层；31-功能单元；311、3111、3112、3113-第一焊盘组；312-第二焊盘组；3121-第一排；3122-第二排；32-走线组；321-连接走线；322-第一类走线；323-第二类走线；4-绝缘层；41-开口。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
相关技术中，发光基板包括衬底基板01、位于衬底基板上的M1*M2个功能单元02以阵列方式排布、M1条地址信号线S、M1条地址信号转接线Q、M2条数据线D、M2条接地线G、M2条第一电源线Va及M2条第二电源线Vb以及多个像素单元；如图1所示为本公开实施例中发光基板的连接结构示意图，如图2所示为本公开实施例中一个功能单元的连接结构示意图。
其中，多个功能单元02在第一方向F1和第二方向F2上呈阵列分布，第一方向F1与第二方向F2相互交叉，功能单元02包括多个第一焊盘组021和一个第二焊盘组022，第二焊盘组022包括与该功能单元中第一焊盘组对应的通道焊盘CH(例如CH1、CH2、CH3)、数据信号焊盘Da、地址焊盘Uc、接地焊盘GND，通道焊盘可以通过连接走线023与第一焊盘组021一一对应连接，数据信号焊盘Da、地址焊盘Uc、接地焊盘GND属于功能焊盘。
多个像素单元03与多个功能单元02一一对应连接，像素单元03包括多个发光元件031以及驱动元件032，功能单元中第一焊盘组021中焊盘的个数与发光元件031的引脚的个数相同，发光元件031的引脚与功能单元中第一焊盘组021中的焊盘一一对应连接，功能单元中第二焊盘组022中焊盘的个数与驱动元件032的引脚的个数相同，驱动元件032的引脚与功能单元中第二焊盘组022中的焊盘一一对应连接，用于驱动发光元件031点亮。
应该说明的是，第一方向F1可以为阵列排布的多个功能单元的行方向，第二方向F2可以为阵列排布的多个功能单元的列方向；或者，第一方向F1可以为阵列排布的多个功能单元的列方向，第二方向F2可以为阵列排布的多个功能单元的行方向，在此不做限定。为了便于说明，在本公开实施例中，第一方向F1为列方向，第二方向F2为行方向。M1的数值与功能单元的行数 相等，M2的数值与功能单元的列数相等。
其中，各地址信号线Si(0＜i≤M1，i为正整数)与在第二方向F2上排列的一行各功能单元的第二焊盘组中地址焊盘Uc耦接，用于为像素单元提供地址数据。
各地址信号转接线Q i(0＜i≤M1，i为正整数)与地址信号线S i一一对应；
各数据线Dj(0＜j≤M2，j为正整数)与在第一方向F1上排列的一列功能单元的各第二焊盘组的数据信号焊盘Da耦接，用于为像素单元提供。
接地线Gj(0＜j≤M2，j为正整数)与在第一方向F1上排列的一列功能单元的各第二焊盘组的接地焊盘GND耦接，用于为像素单元提供接地电压信号；
第一电源线Vaj、第二电源线Vbj与在第一方向F1上排列的一行第一焊盘组耦接；功能单元中的各第一焊盘组的第二子焊盘分别与第二焊盘组的各信号通道焊盘CH耦接。
上述发光基板在驱动的过程中，在地址分配阶段，依次通过各地址信号线向地址焊盘传输选址信息，选址信息中包括对应的像素行的地址ID，从而驱动元件032分别获得特定的地址ID；在数据信号传输阶段，向各数据线分别向各像素列传输数据信息；数据信息包括与某像素列中所有驱动元件一一对应的地址ID及像素数据信息，因而，各个驱动元件可以准确获取与自己地址ID匹配的像素数据信息，并将该像素数据信息经过解析分包处理后形成用于分别控制所连接的发光单元的电学信号，从而实现了有源寻址的驱动方式。
上述发光基板中一个功能单元02所在区域具体的布线结构示意图和截面图可以分别如图3和图4所示。如图4为图3中沿剖切线AA’形成的剖面图，在制作过程中发光基板具体包括衬底基板01、缓冲层04、第一金属走线层05、第一绝缘层061、第一平坦层071、第二绝缘层062、第二金属走线层08、第三绝缘层063、第二平坦层072以及第四绝缘层064，其中，如图3所示，上述M1条地址信号转接线Q、M2条数据线D、M2条接地线G、M2条第一电 源线Va、M2条第二电源线Vb等可以属于第一金属走线层，多个功能单元02、连接走线023、M1条地址信号线S可以属于第二金属走线层08，形成双层走线层，第一金属走线层05中的各个走线通过贯穿第一绝缘层061、第一平坦层071、第二绝缘层062的第一通孔091与第二金属走线层08中的功能单元的第一焊盘组021和第二焊盘组022连接，发光元件可以通过贯穿第三绝缘层063、第二平坦层071以及第四绝缘层064的第二通孔092与功能单元中第一焊盘组021和第二焊盘组022连接。
其中，如图3所示，上述第二金属走线层08中，功能单元02中的各个焊盘与连接的走线为一体结构，各个焊盘为第二金属走线层08中被第三绝缘层063、第二平坦层071以及第四绝缘层064上形成的第二通孔092暴露的部分，而第二金属走线层08中的走线为被第三绝缘层063、第二平坦层071以及第四绝缘层064覆盖保护的部分。
上述双层金属走线层的结构在制作过程中需要经过多次图案化工艺制程，具体地，例如包括：(1)对第一金属走线层05图案化；(2)对第一绝缘层061和第一平坦层071图案化；(3)对第二绝缘层062图案化；(4)对第二金属走线层08图案化；(5)对第三绝缘层063和第二平坦层072图案化；(6)对第四绝缘层064图案化。由此可见，双层金属走线层的制程复杂，可能导致产品良率较低，成本高。
为了克服上述技术问题，本公开实施例提供一种布线基板，如图5和图6所示，包括：呈阵列分布的多个功能单元31；每个功能单元31包括：
多个第一焊盘组311，多个第一焊盘组311沿第一方向F1间隔排布，每个第一焊盘组311包括沿第二方向F2间隔排列的第一子焊盘P1和第二子焊盘P2；
第二焊盘组312，第二焊盘组312沿第二方向F2位于多个第一焊盘组311的一侧，第二焊盘组312包括多个通道焊盘Ch、至少两个功能焊盘Gn，第二焊盘组312中的焊盘个数为偶数，以2*N的方式阵列间隔分布；
其中，多个通道焊盘Ch沿同一方向依次间隔设置成第一排3121、且分 别与相同数目的多个第一焊盘组311一一对应连接；至少两个功能焊盘Gn中的一个功能焊盘Gn位于第一排3121，且该功能焊盘Gn仅与多个通道焊盘Ch中的一个通道焊盘Ch相邻；至少两个功能道焊盘中的其余功能焊盘Gn沿同一方向间隔设置成第二排3122。
本公开实施例提供的布线基板中，包括呈阵列分布的多个相同的功能单元31；每个功能单元31包括多个第一焊盘组311和一个第二焊盘组312；多个第一焊盘组311沿第一方向F1间隔排布，第二焊盘组312沿第二方向F2位于多个第一焊盘组311的同一侧；第二焊盘组312中，多个通道焊盘Ch沿同一方向依次间隔设置成第一排3121、且分别与所在的功能单元31中相同数目的多个第一焊盘组311一一对应连接，能够使得与第一焊盘组311连接的走线、第一焊盘组311与第二焊盘组312之间连接的走线、以及与第二焊盘组312连接的走线沿第二方向F2依次排列、不交叠，有利于使得各条走线均设置在同一层；第二焊盘组312中，至少两个功能焊盘Gn中的一个功能焊盘Gn位于第一排3121，且该功能焊盘Gn仅与多个通道焊盘Ch中的一个通道焊盘Ch相邻，即第二焊盘组312的第一排3121的端部设置一个功能焊盘Gn，至少两个功能焊盘Gn中的其余功能焊盘Gn沿同一方向间隔设置成第二排3122，与相关技术中技术方案相比，第二焊盘组312中，增加了功能焊盘Gn的数目，并对功能焊盘Gn的位置进行了调整，同时可以调整功能焊盘Gn的所接收信号的类型，改变与第二焊盘组312连接的走线的形状以及延伸方向，可以实现布线基板中各条走线均设置在同一层，进而能够使得布线基板上的功能单元31和功能单元31连接的走线实现单层布线，能够大大简化制作布线基板的工艺制程，进而能够提高产品良率，并且能够减少掩膜板的使用量，大幅度降低制作成本。
具体地，如图7所示为图6中沿剖切线BB’形成的剖面图，布线基板包括依次层叠设置的衬底基板1、缓冲层2、金属走线层3以及绝缘层4。其中，布线基板的制作工艺中仅需经历2道mask工艺，具体包括：(1)对金属走线层3图案化形成金属走线；(2)对绝缘层4图案化形成开口41，通过绝缘层 4上的开口41可在金属走线的预设区域限定出功能单元31中的焊盘，像素单元可以通过开口41与金属走线裸露于开口41处的部分连接，像素单元可以包括多个发光元件和驱动元件，发光元件可以与第一焊盘组311连接，驱动元件可以与第二焊盘组312连接。由此可见，本公开中提供的布线基板的结构能够大大简化布线基板的工艺制程。
在实际应用中，发光元件的引脚呈矩形，宽边的尺寸在30～50μm之间，长边的尺寸在50～75μm之间，对应的第一焊盘组311中的第一子焊盘P1和第二子焊盘P2的长、宽的尺寸比发光元件引脚的长、宽尺寸分别大2～30μm；驱动元件的引脚呈矩形，宽边的尺寸一般在30～50μm之间，长边的尺寸在45～70μm之间，对应的第二焊盘组312中焊盘的长、宽的尺寸比驱动元件的引脚的长、宽尺寸分别大2～30μm，第一焊盘组311中第一子焊盘P1与第二子焊盘P2之间的间隙宽度d1可以为50～200μm，第二焊盘组312中两排之间的间隙宽度d2可以为50～200μm。由于第一焊盘组的位置分布决定了后续发光元件的位置分布，而发光元件的位置分布对显示效果有决定性的影响，所以当第一焊盘组311的位置确定后，第二焊盘组312的位置不仅要考虑走线的设计要求，还要兼顾与第一焊盘组311之间的距离，第二焊盘组312与第一焊盘组311之间的距离d3大于等于100μm即可，能够满足修复发光元件的空间需求。
本公开实施例中，如图5和图6所示，上述布线基板可以包括沿第二方向F2排布的多个走线组32，多个走线组32的数目与功能单元31的列数相同，每组走线组32与一列功能单元31对应连接；具体地，每组走线组32包括多条连接线321、第一类走线322以及第二类走线323，连接线321用于将一列功能单元31中的通道焊盘Ch与第二子焊盘P2分别一一对应连接，第一类走线322与一列功能单元31中的功能焊盘Gn连接，第二类走线323与一列功能单元31中的第一子焊盘P1连接；其中，第一类走线322和第二类走线323沿第二方向F2排列且沿第一方向F1延伸，能够使得第一类走线322和第二类走线323的大致走向一致，避免第一类走线322和第二类走线323的相互 交叠，有利于各条走线均设置在同一层；第一类走线322中至少一条走线穿过一列功能单元31中第二焊盘组312的第一排3121与第二排3122之间的间隙设置，第二类走线323中至少一条走线穿过一列功能单元31中第一子焊盘P1与第二子焊盘P2之间的间隙设置，通过将第一类走线322和第二类走线323中的部分走线穿过焊盘之间的间隙设置，进而可以使得全部的走线组32中的各条走线均同层设置，简化布线基板的结构，降低制作难度，进而减少生产成本。
在实际应用中，如图6所示，第一类走线322和第二类走线323中两条相邻的走线之间的距离d4可以为5μm至100μm，具体可以根据实际情况设置。而第一类走线322和第二类走线323中走线的宽度根据不同的走线功能不同，走线需要的线宽也不相同，具体需要根据实际情况设置，在这里不做限制。
上述公开实施例中，一个功能单元31中第二焊盘组312的两排焊盘的延伸方向可以沿第一方向F1延伸，如图5和图6所示；或者，还可以沿第二方向F2延伸，如图8和图9所示，即将图5和图6中的第二焊盘组312逆时针旋转90度。根据第二焊盘组312中两排焊盘的延伸方向，需要适应性调整第二焊盘组312中各个焊盘的具体位置以及各个走线的具体走向，本领域技术人员可以根据本公开实施例的方式进行需要根据实际情况而定。
具体地，每个功能单元31中，多个通道焊盘Ch沿第二方向F2邻近多个第一焊盘组311中的第二子焊盘P2设置，可以使得连接第二子焊盘P2和通道焊盘Ch的连接线位于该功能单元31的第一焊盘组311与第二焊盘组312之间，通道焊盘Ch的排列顺序与对应的第一焊盘组311的排列顺序相配合，能够使得各组对应的第一焊盘组311中的第二子焊盘P2与第二焊盘组312中的通道焊盘Ch依次连接，各个连接走线321可以与第一类走线322和第二类走线323同层设置，且相互绝缘无交叉。
在实际应用中，一个功能单元31中具体可以包括用于与红色发光元件连接的第一焊盘组3111、用于与绿色发光元件连接的第一焊盘组3112和用于与蓝色发光元件连接的第一焊盘组3113，该功能单元31的第二焊盘组312包括 与第一焊盘组3111连接的第一通道焊盘Ch1、与第一焊盘组3112连接的第二通道焊盘Ch2、与第一焊盘组3113连接的第三通道焊盘Ch3。如图10所示，该功能单元31的第二焊盘组312中的两排沿第一方向F1延伸，则功能单元31中第二焊盘组312中的第一排3121位于第二焊盘组312邻近第一焊盘组311的一侧，可以使得第一通道焊盘Ch1、第二通道焊盘Ch2和第三通道焊盘Ch3邻近第一焊盘组311设置，第一焊盘组3111、第一焊盘组3112、第一焊盘组3113在第一方向F1上排列，第一通道焊盘Ch1、第二通道焊盘Ch2和第三通道焊盘Ch3在第一方向F1上的排列顺序与第一焊盘组3111、第一焊盘组3112和第一焊盘组3113在第一方向F1上的排列顺序相同，能够保证对应连接的三条连接线按照顺序排列，相互绝缘无交叉。例如，如图10所示，一个功能单元31中，第一焊盘组3111、第一焊盘组3112、第一焊盘组3113在第一方向F1上依次排列，则第二焊盘组312中第一通道焊盘Ch1、第二通道焊盘Ch1、第三通道焊盘Ch1在第一方向F1上依次排列；或者，如图11所示，将图10中的第一焊盘组3111和第一焊盘组3113的位置进行互换，则相应的第一通道焊盘Ch1和第三通道焊盘Ch3的位置也进行互换；或者，如图12所示，将图10中的第一通道焊盘3112和第一通道焊盘3113的位置进行互换，则相应的第二通道焊盘Ch2和第三通道焊盘Ch3的位置也进行互换；另外，如图13所示，第二焊盘组312的第一排3121中三个通道焊盘Ch的位置与功能焊盘Gn的位置也可以互换。具体地，多个第一焊盘组311和多个通道焊盘Ch的排列方式可以根据实际情况而定。
可选地，如图14所示，功能单元31的第二焊盘组312中两排焊盘的延伸方向也可以为第二方向F2，第二焊盘组312中的通道焊盘Ch可以位于第一排3121中邻近第一焊盘组311的位置，第一焊盘组3111、第一焊盘组3112、第一焊盘组3113在第一方向F1上依次排列，则第二焊盘组312中第一通道焊盘Ch1、第二通道焊盘Ch1、第三通道焊盘Ch1在第二方向F2上依次排列；或者，三个第一焊盘组之间的顺序可以互换，对应的三个通道焊盘Ch之间的位置也进行互换，达到排列顺序相同的目的。另外，如图15所示，第二焊盘 组312的第一排3121和第二排3122的上下位置也可以互换，相应的三个通道焊盘Ch的位置也需要对应调整。具体地，多个第一焊盘组311和多个通道焊盘Ch的排列方式可以根据实际情况而定。
本公开实施例中，具体地，每个功能单元31中，如图16所示，至少两个功能焊盘Gn可以包括信号焊盘Vc、地址输入焊盘D-in、地址输出焊盘D-out以及至少一个接地焊盘GND；其中，信号焊盘Vc、地址输入焊盘D-in和地址输出焊盘D-out中的任意一个可以位于第二焊盘组312的第一排3121，地址输入焊盘D-in和地址输出焊盘D-out中至少一个仅与所在排的其他焊盘中的一个相邻，能够便于在第二焊盘组312的端部进行接线，有利于单层金属走线层3的布置。上述功能单元31的第二焊盘组312中，将相关技术中双层金属走线层3中数据信号焊盘Da、地址焊盘Uc的功能分别由地址输入焊盘D-in和地址输出焊盘D-out、数据信号焊盘Vc取代，相应的与第二焊盘组312对应连接的驱动元件的引脚的功能也需要被重新定义，可以通过对驱动元件内部的逻辑控制电路和功能进行调整，进而实现布线基板上单层金属走线层3的设置。
为了保证第二焊盘组与驱动元件连接时的稳定性，需要第二焊盘组312中的两排焊盘对称设置，因此，第二焊盘组312中至少一个接地焊盘GND可以包括两个，两个接地焊盘GND可以在第二焊盘组312的第二排3122中相邻设置，方便与对应的走线Gd连接。
具体地，如图16所示，图16中对应的布线基板上的具体布局结构可以如图5和图6所示，上述第一类走线322可以包括：信号线Vcc、接地线Gd、多条级联线L、地址线Addr；其中，信号线Vcc与对应的一列功能单元31中的所有信号焊盘Vc连接，接地线Gd与对应的一列功能单元31中的接地焊盘GND连接，多条级联线L用于将一列功能单元31中每相邻的两个功能单元31级联，级联线L的一端连接前一个功能单元31的地址输出焊盘D-out、另一端连接后一个功能单元31的地址输入焊盘D-in；地址线Addr与对应的一列功能单元31中首个功能单元31的地址输入焊盘D-in连接。
上述公开实施例中，与一列功能单元31的信号焊盘Vc连接的信号线Vcc用于提供包括地址信息和发光信息的数据，地址线Addr和多条级联线L用于提供特定的地址信息，通过功能单元31中焊盘功能和数量的调整结合对走线功能以及布局的调整，能够避免出现需要相互交叉设置的走线，能够实现第一类走线322与连接走线321同层设置，实现布线基板的单层布线。
具体地，具有上述布线基板的发光基板在上电正常显示前，通过地址线Addr和级联线L依次向驱动元件分配特定的地址信息，等到显示阶段，信号线Vcc中传输的信号为电力载波信号，即既包括了为驱动元件提供工作电压的电源信号，同时又加载有地址数据信号和发光数据信号，每个驱动元件从信号线Vcc传输的数据中匹配出与自己地址信息相同的发光数据，再经过驱动元件的内部处理和运算，通过连接线控制驱动元件与发光元件形成信号通路，从而让发光元件呈现特定灰阶的亮度，与相关技术中发光基板的驱动方式不同。
本公开实施例中，每个功能单元31中，第二焊盘组312的第一排3121和第二排3122的延伸方向可以朝向不同方向延伸，这样得到的布线基板的走线布局也不相同。
具体地，第二焊盘组312的第一排3121和第二排3122的延伸方向可以均为第一方向F1。在这种情况下，每个功能单元31中的焊盘以及走线布局可以按照如下结构设置。
其中，如图16所示，由于功能单元31的第二焊盘组312中的通道焊盘Ch需要邻近多个第一焊盘组311设置，则每个功能单元31中，信号焊盘Vc可以位于第二焊盘组312的第一排3121，与多个通道焊盘Ch位于同一排；信号线Vcc可以穿过第二焊盘组312中第一排3121和第二排3122之间的间隙设置；接地线Gd可以位于第二焊盘组312远离第一焊盘组311的一侧，能够避免信号线Vcc和接地线Gd与其他走线之间互相不干涉，实现同层设置。
具体地，如图17所示，在功能单元31的第二焊盘组312的第一排3121中，信号焊盘Vc与多个通道焊盘Ch的排列位置可以交换，具体信号焊盘Vc 与多个通道焊盘Ch的顺序在这里不做限制，可以根据实际情况而定，多个通道焊盘Ch的排列方式可以如上述任意技术方案中的一种，在这里不做限制，根据实际情况而定。
可选地，如图16和图17所示，第二焊盘组312中，地址输入焊盘D-in与地址输出焊盘D-out均仅与所在排的其他焊盘中的一个相邻，即地址输入焊盘D-in和地址输出焊盘D-out全部位于第二焊盘组312的第二排3122列端部；这样级联线L可以位于一列功能单元31中相邻的两个功能单元31之间，避免与其他走线发生干涉。
可选地，如图18所示，第二焊盘组312中，还可以设置为地址输入焊盘D-in与地址输出焊盘D-out中一个焊盘仅与所在排的其他焊盘中的一个相邻，即地址输入焊盘D-in与地址输出焊盘D-out中一个焊盘位于第二焊盘组312的第二排3122的端部，而另一个夹于两个焊盘之间；这样为了避免级联线L与其他走线相互之间发生干涉，则可以设置级联线L也穿过第二焊盘组312中第一排3121和第二排3122之间的间隙设置。
此种情况下，功能单元31的第二焊盘组312中各个焊盘的排列布局不仅可以设置为如图18所示，还可以为其他多种实施方式。例如，如图19所示，将图18中地址输入焊盘D-in和地址输出焊盘D-out位置进行互换；或者，如图20所示，将图18中接地焊盘GND的位置与地址输入焊盘D-in和地址输出焊盘D-out的位置进行互换；或者，如图21所示，将图20中地址输入焊盘D-in和地址输出焊盘D-out位置进行互换；或者，如图22所示，将图20中多个通道焊盘Ch的位置与信号焊盘Vc的位置进行互换；或者，如图23所示，将图22中地址输入焊盘D-in和地址输出焊盘D-out位置进行互换；或者，如图24所示，将图22中接地焊盘GND的位置与地址输入焊盘D-in和地址输出焊盘D-out的位置进行互换；或者，如图25所示，将图24中地址输入焊盘D-in和地址输出焊盘D-out位置进行互换。具体地，功能单元31的第二焊盘组312中各个焊盘的排列顺序可以根据实际情况而定，在这里不做限制。
本公开实施例中，每个功能单元31中，第二焊盘组312的第一排3121 和第二排3122的延伸方向也可以均为第二方向F2。在这种情况下，每个功能单元31中的焊盘以及走线布局可以按照如下结构设置。
其中，如图26和图27所示，图26中对应的布线基板上的具体布局结构可以如图8和图9所示，每个功能单元31中，地址输入焊盘D-in和地址输出焊盘D-out中的一个焊盘位于第二焊盘组312的第一排3121，即地址输入焊盘D-in和地址输出焊盘D-out中的一个需要设置在第二焊盘组312远离第一焊盘组311的端部；这样地址输入焊盘D-in和地址输出焊盘D-out中的另一个则位于第二焊盘组312中的第二排3122，级联线L可以位于一列功能单元31中相邻的两个功能单元31之间，能够避免级联线L与其他走线相互干涉。
可选地，如图26和图27所示，每个功能单元31中，可以设置至少一个接地焊盘GND与位于第二焊盘组312的第一排3121的功能焊盘Gn相邻；这样接地线Gd可以位于第二焊盘组312沿第二方向F2远离多个第一焊盘组311的一侧，避免与其他走线相互干涉；信号线Vcc可以穿过第二焊盘的第一排3121与第二排3122之间的间隙设置，避免与其他走线发生干涉。
具体地，如图26和图27所示，第二焊盘组312中信号焊盘Vc在第二排3122可以夹于两个焊盘之间，信号线Vcc可以从第二焊盘组312远离第一焊盘组311的一侧穿过第二焊盘组312的第一排3121和第二排3122之间的间隙，使得级联线L与信号线Vcc之间相互不干涉；或者，如图28所示，第二焊盘组312中信号焊盘Vc也可以位于第二排3122的端部，信号线Vcc可以从第二焊盘组312的第一排3121中功能焊盘Gn与通道焊盘Ch之间的间隙以及第二排3122与第一排3121之间的间隙穿过。
可选地，如图29所示，每个功能单元31中，也可以设置信号焊盘Vc与位于第二焊盘组312的第一排3121的功能焊盘Gn相邻；信号线Vcc可以位于第二焊盘组312沿第二方向F2远离多个第一焊盘组311的一侧；接地线Gd可以位于第二焊盘的第一排3121与第二排3122之间的间隙设置。
本公开实施例中，如图16、图18和图26所示，上述地址线Addr可以位于第二类走线323远离第二焊盘组312的一侧，地址线Addr可以通过位于功 能单元31阵列一侧的走线与一列功能单元31中的首个功能单元31的地址输入焊盘D-in连接。
在实际应用中，为了更好的实现各个走线的功能，上述级联线L、地址线Addr以及信号线Vcc的最小线宽尺寸可以为30μm，接地线Gd的最小线宽尺寸可以为150μm。为了更好的布局，可以将接地线Gd设置于第二焊盘组312远离第一焊盘组311的一侧，能够保证接地线Gd的线宽。信号线Vcc或者级联线L的最小线宽要求较小，能够使得信号线Vcc或者级联线L穿过第二焊盘组312中第一排3121和第二排3122之间的间隙设置，则穿过第二焊盘组312中间隙的信号线Vcc和级联线L可以包括位于第二焊盘组312所在区外的第一主体部和穿过第二焊盘组312的第一穿越部，由于第二焊盘组312中两排焊盘之间的间隙宽度尺寸有限，可以设置第一穿越部的线宽小于第一主体部的线宽，例如，如图30所示，第二焊盘组312中两排焊盘之间的间隙可以为50至200μm，则信号线Vcc或级联线L的第一主体部线宽d51可以设置为大于等于30μm，信号线Vcc或级联线L的第一穿越部的线宽d52可以设置为大于等于5μm；若信号线Vcc和级联线L同时位于第二焊盘组312的两排间隙之间，则信号线Vcc与级联线L之间的线距可以为5至20μm，具体尺寸可以根据实际工艺能力决定。
本公开实施例中，每个功能单元31中，多个第一焊盘组311分为两类，相同类的第一焊盘组311相邻设置；具体地，如图31和32所示，每个功能单元31可以包括用于与红色发光元件连接的第一焊盘组3111、与绿色发光元件连接的第一焊盘组3112、与蓝色发光元件连接的第一焊盘组3113，其中，发光元件一般为发光二极管(LED)，在实际应用中，绿色发光二极管和蓝色发光二极管的光电特性基本相同，而红色发光二极管的光电特性与蓝色发光二极管或绿色发光二极管的光电特性存在差异，因此红色发光二极管需要加载的电源电压与绿色发光二极管和蓝色发光二极管需要加载的电源电压不同，则可以将第一焊盘组3111作为第一类第一焊盘组，而将第一焊盘组3112和第一焊盘组3113作为第二类第一焊盘组，第一焊盘组3112和第一焊盘组3113 相邻设置；
具体地，如图31和图32所示，第二类走线323可以包括两条电源线，每条电源线与一列功能单元31中一类第一焊盘组311连接，其中一条电源线位于多个第一焊盘组311远离第二焊盘组312的一侧，另一条电源线穿过第一焊盘组311中第一子焊盘P1和第二子焊盘P2之间的间隙设置。
例如，第二类走线323可以包括第一电源线Ve和第二电源线Vf，第一电源线Ve与一列功能单元31中第一焊盘组3111的第一子焊盘P1相连接，第二电源线Vf与一列功能单元31中第一焊盘组3112和第一焊盘组3113相连接。其中，如图31所示，对应的布线基板上的具体布局结构可以如图5和图6所示，可以第一电源线Ve位于多个第一焊盘组311远离第二焊盘组312的一侧，第二电源线Vf穿过第一焊盘组311中第一子焊盘P1和第二子焊盘P2之间的间隙设置；或者，如图32所示，还可以第二电源线Vf位于多个第一焊盘组311远离第二焊盘组312的一侧，第一电源线Ve穿过第一焊盘组311中第一子焊盘P1和第二子焊盘P2之间的间隙设置。
在实际应用中，由于第一电源线Ve上记载的电压需要大于第二电源线Vf上加载的电压，第一电源线Ve的最小宽度可以为100μm，第二电源线Vf的最小宽度可以为50μm。穿过第一子焊盘P1和第二子焊盘P2之间间隙的电源线可以包括位于第一焊盘组311所在区域之外的第二主体部和位于第一子焊盘P1与第二子焊盘P2之间的第二穿越部，由于第一子焊盘P1与第二子焊盘P2之间的间隙宽度有限，可以设置第二穿越部的线宽小于第一主体部的线宽，例如，如图30所示，第二电源线Vf穿过第一子焊盘P1与第二子焊盘P2之间的间隙设置，则第二电源线Vf的第二主体部的线宽d61可以为100μm，第二电源线Vf的第二穿越部的线宽d62可以为大于等于20μm，具体地尺寸可以在这里不做限制，根据实际情况而定。
本公开实施例还提供一种发光基板，包括上述技术方案中提供的任意一种布线基板，还包括与第一焊盘组一一对应连接的多个发光元件以及与第二焊盘组一一对应连接的多个驱动元件。
本公开实施例提供的发光基板中，布线基板中只设置一层金属走线层，能够简化制作制程，能够大大简化制作工艺制程，进而能够提高产品良率，并且能够减少掩膜板的使用量，大幅度降低制作成本。
具体地，上述发光基板的制作过程可以为：
第一步：在衬底基板上通过溅射工艺制作缓冲层，能够减小下一步制作金属走线层对衬底基板的应力影响，从而减小衬底基板的翘曲度，衬底基板可以为玻璃基板；
第二步：通过溅射、清洗、涂胶、烘烤、曝光、显影、硬烤、刻蚀、剥离的工艺流程在缓冲层上方制作金属走线层，另外，此金属走线层也可以通过电镀工艺完成；
第三步：通过溅射、曝光、显影的工艺流程制作一层绝缘层；
第四步：对由金属走线层裸露于绝缘层上开口的部分进行化镍金处理；
第五步：在绝缘层上涂覆白油；
第六部：进行固晶等制程，即将像素单元中的发光元件和驱动元件通过开口与金属走线层中的焊盘连接。
其中，上述发光元件可以为次毫米发光二极管(微型发光二极管)，也可以为微型发光二极管(Micro LED)，此处不做限定。驱动元件可以为驱动芯片，根据实际情况设置，在这里不做限制。
本公开还提供一种显示装置，包括上述技术方案中提供的发光基板。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种布线基板，其中，包括：呈阵列分布的多个功能单元；每个所述功能单元包括：
    多个第一焊盘组，多个所述第一焊盘组沿第一方向间隔排布，每个所述第一焊盘组包括沿第二方向间隔排列的第一子焊盘和第二子焊盘；
    第二焊盘组，所述第二焊盘组沿第二方向位于所述多个第一焊盘组的一侧，所述第二焊盘组包括多个通道焊盘、至少两个功能焊盘，所述第二焊盘组中的焊盘个数为偶数，以2*N的方式阵列间隔分布；
    其中，所述多个通道焊盘沿同一方向依次间隔设置成第一排、且分别与相同数目的多个第一焊盘组一一对应连接；所述至少两个功能焊盘中的一个功能焊盘位于所述第一排，且该功能焊盘仅与所述多个通道焊盘中的一个通道焊盘相邻；所述至少两个功能道焊盘中的其余功能焊盘沿同一方向间隔设置成第二排。
  2. 根据权利要求1所述的布线基板，其中，还包括沿第二方向排布的多个走线组，所述多个走线组的数目与所述功能单元的列数相同，每组所述走线组与一列功能单元对应连接；
    每组所述走线组包括多条连接线、第一类走线以及第二类走线，所述多条连接线用于将一列功能单元中的通道焊盘与第二子焊盘一一对应连接，所述第一类走线与一列功能单元中的功能焊盘连接，所述第二类走线与一列功能单元中的第一子焊盘连接；
    其中，所述第一类走线和第二类走线沿第二方向排列且沿第一方向延伸，所述第一类走线中至少一条走线穿过一列功能单元中所述第二焊盘组的第一排与第二排之间的间隙设置，所述第二类走线中至少一条走线穿过一列功能单元中第一子焊盘与第二子焊盘之间的间隙设置，以使所述多个走线组中的各条走线同层设置。
  3. 根据权利要求2所述的布线基板，其中，每个所述功能单元中，所述 多个通道焊盘沿第二方向邻近所述多个第一焊盘组中的第二子焊盘设置，所述通道焊盘的排列顺序与对应的所述第一焊盘组的排列顺序相配合。
  4. 根据权利要求3所述的布线基板，其中，每个所述功能单元中，所述至少两个功能焊盘包括信号焊盘、地址输入焊盘、地址输出焊盘以及至少一个接地焊盘；
    所述信号焊盘、地址输入焊盘和所述地址输出焊盘中的任意一个位于所述第二焊盘组的第一排，所述地址输入焊盘和所述地址输出焊盘中至少一个仅与所在排的其他焊盘中的一个相邻。
  5. 根据权利要求4所述的布线基板，其中，所述第一类走线包括：
    信号线，所述信号线与对应的一列功能单元中的所有信号焊盘连接；
    接地线，所述接地线与对应的一列功能单元中的所述接地焊盘连接；
    多条级联线，所述多条级联线用于将一列功能单元中每相邻的两个功能单元级联，所述级联线的一端连接前一个功能单元的地址输出焊盘、另一端连接后一个功能单元的地址输入焊盘；
    地址线，所述地址线与对应的一列功能单元中首个功能单元的地址输入焊盘连接。
  6. 根据权利要求5所述的布线基板，其中，每个所述功能单元中，所述第二焊盘组的第一排和第二排的延伸方向均为第一方向。
  7. 根据权利要求6所述的布线基板，其中，每个所述功能单元中，所述信号焊盘位于所述第二焊盘组的第一排；
    所述信号线穿过所述第二焊盘组中第一排和第二排之间的间隙设置；
    所述接地线位于所述第二焊盘组远离所述第一焊盘组的一侧。
  8. 根据权利要求7所述的布线基板，其中，所述第二焊盘组中，所述地址输入焊盘与所述地址输出焊盘均仅与所在排的其他焊盘中的一个相邻；
    所述级联线位于一列功能单元中相邻的两个功能单元之间。
  9. 根据权利要求7所述的布线基板，其中，所述第二焊盘组中，所述地址输入焊盘与所述地址输出焊盘中一个焊盘仅与所在排的其他焊盘中的一个 相邻；
    所述级联线穿过所述第二焊盘组中第一排和第二排之间的间隙设置。
  10. 根据权利要求5所述的布线基板，其中，每个所述功能单元中，所述第二焊盘组的第一排和第二排的延伸方向均为第二方向。
  11. 根据权利要求10所述的布线基板，其中，每个所述功能单元中，所述地址输入焊盘和所述地址输出焊盘中的一个焊盘位于所述第二焊盘组的第一排；
    所述级联线位于一列功能单元中相邻的两个功能单元之间。
  12. 根据权利要求11所述的布线基板，其中，每个所述功能单元中，所述至少一个接地焊盘与位于所述第二焊盘组的第一排的功能焊盘相邻；
    所述接地线位于所述第二焊盘组沿第二方向远离多个第一焊盘组的一侧；
    所述信号线穿过所述第二焊盘的第一排与第二排之间的间隙设置。
  13. 根据权利要求11所述的布线基板，其中，每个所述功能单元中，所述信号焊盘与位于所述第二焊盘组的第一排的功能焊盘相邻；
    所述信号线位于所述第二焊盘组沿第二方向远离多个第一焊盘组的一侧；
    所述接地线位于所述第二焊盘的第一排与第二排之间的间隙设置。
  14. 根据权利要求5-13任一项所述的布线基板，其中，所述地址线位于所述第二类走线远离所述第二焊盘组的一侧。
  15. 根据权利要求4-14任一项所述的布线基板，其中，所述第二焊盘组包括两个接地焊盘，所述两个接地焊盘相邻设置。
  16. 根据权利要求3-15任一项所述的布线基板，其中，每个所述功能单元中，所述多个第一焊盘组分为两类，相同类的第一焊盘组相邻设置；
    所述第二类走线包括两条电源线，每条所述电源线与一列功能单元中一类所述第一焊盘组连接，其中一条电源线位于所述多个第一焊盘组远离所述第二焊盘组的一侧，另一条电源线穿过所述第一焊盘组中第一子焊盘和第二子焊盘之间的间隙设置。
  17. 一种发光基板，其中，包括如权利要求1-16任一项所述的布线基板， 还包括与第一焊盘组一一对应连接的多个发光元件以及与第二焊盘组一一对应连接的多个驱动元件。
  18. 一种显示装置，其中，包括如权利要求17所述的发光基板。
PCT/CN2022/130968 2022-11-09 2022-11-09 一种布线基板、发光基板及显示装置 WO2024098302A1 (zh)

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