WO2023173497A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023173497A1
WO2023173497A1 PCT/CN2022/084132 CN2022084132W WO2023173497A1 WO 2023173497 A1 WO2023173497 A1 WO 2023173497A1 CN 2022084132 W CN2022084132 W CN 2022084132W WO 2023173497 A1 WO2023173497 A1 WO 2023173497A1
Authority
WO
WIPO (PCT)
Prior art keywords
pin
data selection
light
lamp group
signal
Prior art date
Application number
PCT/CN2022/084132
Other languages
English (en)
French (fr)
Inventor
刘净
邓红照
崔正波
白一晨
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to JP2022521062A priority Critical patent/JP2024519561A/ja
Priority to US17/765,588 priority patent/US20240055418A1/en
Publication of WO2023173497A1 publication Critical patent/WO2023173497A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, and specifically to a display panel.
  • Mini LED LED also known as “sub-millimeter light-emitting diode” refers to a display screen composed of LEDs with a grain (chip) size of 50 microns to 200 microns, which is between Micro LED and small-pitch displays. It is widely used in Mini LED direct display and Mini LED backlight displays.
  • the metal wiring methods are two-layer or above metal wiring methods.
  • ground wiring, partition channel wiring, and power cables are arranged on different layers.
  • Such wiring methods will cause different metal layers to The problem of short circuit occurs occasionally, that is, it is easy to short-circuit, causing higher costs and other problems.
  • Embodiments of the present application provide a display panel to solve the problem of easy short circuits in the prior art when ground wiring, partition channel wiring, and power lines are arranged on two or more layers.
  • the present application provides a display panel, wherein the display panel includes:
  • Ground signal traces are spaced apart from the power lines, and the ground signal traces and the power lines are arranged along the first direction;
  • a driver chip disposed between the power line and the ground signal line, and connected to the ground signal line;
  • a light-emitting lamp group is arranged between the ground signal trace and the power line, and one end of the light-emitting lamp group is connected to the power line;
  • Partitioned channel wiring is provided between the power line and the ground signal wiring, and the partitioned channel wiring connects the other end of the light-emitting lamp group to the driver chip;
  • the power lines, the partition channel wiring and the ground signal wiring are arranged on the same layer.
  • the light-emitting lamp groups include multiple light-emitting lamp groups arranged along the first direction
  • the partition channel wiring includes multiple
  • the driving A plurality of data selection pins are provided in the chip.
  • a plurality of the data selection pins are provided along the first direction and/or a second direction intersecting the first direction. Each of the data selection pins passes through One of the partition channel wirings is connected to one of the luminous lamp groups.
  • the luminescent lamp group includes a first luminescent lamp group and a second luminescent lamp group
  • the driver chip includes a first data selection pin and a second data selection pin
  • the partition channel wiring includes a first partition channel wiring and a second partition channel wiring
  • the first light-emitting lamp group and the second light-emitting lamp group are arranged along the first direction;
  • the first data selection pin and the second data selection pin are arranged along the first direction;
  • first luminous lamp group and the first data selection pin are connected through the first partition channel wiring
  • second luminous lamp group is connected to the second zoning channel wiring through the second partition channel wiring.
  • Data select pin connection
  • the luminescent lamp group further includes a third luminescent lamp group and a fourth luminescent lamp group
  • the driver chip is further provided with a third data selection pin and a fourth data selection pin. Pins, the partition channel wiring also includes the third partition channel wiring and the fourth partition channel wiring;
  • the first light-emitting lamp group, the second light-emitting lamp group, the third light-emitting lamp group and the fourth light-emitting lamp group are arranged along the first direction;
  • the first data selection pin and the third data selection pin are arranged in a row along the second direction, and the first data selection pin is located on a side of the third data selection pin close to the power line. ;
  • the second data selection pin and the fourth data selection pin are arranged in another column along the second direction, and the second data selection pin is located at a side of the fourth data selection pin close to the power line. side;
  • a third light-emitting lamp group and a third data selection pin are connected through a third partition channel wiring, and a fourth light-emitting lamp group and a fourth data selection pin are connected. Connected through a wiring of the fourth partition channel.
  • the driver chip includes a first part and a second part connected to the first part, and the first part is located at an end of the driver chip close to the power line,
  • the first data selection pin, the second data selection pin, the third data selection pin and the fourth data selection pin are located on the first part;
  • the driver chip includes a ground signal tube The ground signal pin is connected to the ground signal trace, and the ground signal pin is arranged on the second part.
  • the driver chip is provided with two power signal pins, and the two power signal pins are provided on the second part along the first direction, so
  • the display panel includes a driver chip power trace, and the driver chip power trace is disposed between adjacent driver chips for connecting the power signal pins of the driver chip.
  • the driver chip is provided with a stage transmission signal input pin and a stage transmission signal output pin.
  • the stage transmission signal input pin and the stage transmission signal output pin are Arranged on the second part along the first direction, the display panel also includes a driver chip signal trace, the driver chip signal trace is arranged between adjacent driver chips for connecting adjacent driver chips.
  • the level transmission signal input pin and the level transmission signal output pin of the driver chip are provided with a stage transmission signal input pin and a stage transmission signal output pin.
  • the driver chip is provided with at least one data signal pin, the data signal pin is provided on the second part, and the display panel includes a data transmission trace. , the data transmission line is connected to the data signal pin.
  • the number of the data signal pins is one, and one of the data signal pins and the ground signal pin are arranged along the first direction, and the data transmission The trace extends along the first direction and is located on a side of the data signal pin away from the ground signal trace.
  • this application also provides a display panel, which includes:
  • the ground signal wiring is spaced apart from the power line;
  • a driver chip disposed between the power line and the ground signal line, and connected to the ground signal line;
  • a light-emitting lamp group is arranged between the ground signal trace and the power line, and one end of the light-emitting lamp group is connected to the power line;
  • Partitioned channel wiring is provided between the power line and the ground signal wiring, and the partitioned channel wiring connects the other end of the light-emitting lamp group to the driver chip;
  • the power lines, the partition channel wiring and the ground signal wiring are arranged on the same layer.
  • the light-emitting lamp groups include a plurality of light-emitting lamp groups arranged along the first direction
  • the partition channel wiring includes a plurality of lines
  • the driver chip has A plurality of data selection pins are provided, and a plurality of the data selection pins are arranged along the first direction and/or a second direction intersecting the first direction, and each of the data selection pins passes through a
  • the partition channel wiring is connected to one of the luminous lamp groups.
  • the luminescent lamp group includes a first luminescent lamp group and a second luminescent lamp group
  • the driver chip includes a first data selection pin and a second data selection pin
  • the partition channel wiring includes a first partition channel wiring and a second partition channel wiring
  • the first light-emitting lamp group and the second light-emitting lamp group are arranged along the first direction;
  • the first data selection pin and the second data selection pin are arranged along the first direction;
  • first luminous lamp group and the first data selection pin are connected through the first partition channel wiring
  • second luminous lamp group is connected to the second zoning channel wiring through the second partition channel wiring.
  • Data select pin connection
  • the luminescent lamp group further includes a third luminescent lamp group and a fourth luminescent lamp group
  • the driver chip is further provided with a third data selection pin and a fourth data selection pin. Pins, the partition channel wiring also includes the third partition channel wiring and the fourth partition channel wiring;
  • the first luminous lamp group, the second luminous lamp group, the third luminous lamp group and the fourth luminous lamp group are arranged along the first direction, and the first luminous lamp group and the third luminous lamp group
  • the light-emitting lamp group, the second light-emitting lamp group and the fourth light-emitting lamp group are located on opposite sides of the driver chip;
  • the first data selection pin and the third data selection pin are arranged in a row along the second direction, and the first data selection pin is located on a side of the third data selection pin close to the power line. ;
  • the second data selection pin and the fourth data selection pin are arranged in another column along the second direction, and the second data selection pin is located at a side of the fourth data selection pin close to the power line. side.
  • a third light-emitting lamp group and a third data selection pin are connected through a third partition channel wiring, and a fourth light-emitting lamp group and a fourth data selection pin are connected. Connected through a wiring of the fourth partition channel.
  • the driver chip includes a first part and a second part connected to the first part, and the first part is located at an end of the driver chip close to the power line,
  • the first data selection pin, the second data selection pin, the third data selection pin and the fourth data selection pin are located on the first part;
  • the driver chip includes a ground signal tube The ground signal pin is connected to the ground signal trace, and the ground signal pin is arranged on the second part.
  • the driver chip is provided with two power signal pins, and the two power signal pins are provided on the second part along the first direction, so
  • the display panel includes a driving chip power supply trace, and the driving chip power supply trace is disposed between adjacent chips for connecting the power signal pins of the driving chip.
  • the driver chip is provided with a stage transmission signal input pin and a stage transmission signal output pin.
  • the stage transmission signal input pin and the stage transmission signal output pin are Arranged on the second part along the first direction, the display panel also includes a driver chip signal trace, the driver chip signal trace is arranged between adjacent driver chips for connecting adjacent driver chips.
  • the level transmission signal input pin and the level transmission signal output pin of the driver chip are provided with a stage transmission signal input pin and a stage transmission signal output pin.
  • the driver chip is provided with at least one data signal pin, the data signal pin is provided on the second part, and the display panel includes a data transmission trace. , the data transmission line is connected to the data signal pin.
  • the number of the data signal pins is one, and one of the data signal pins and the ground signal pin are arranged along the first direction along the data transmission path.
  • the line extends along the first direction and is located on a side of the data signal pin away from the ground signal trace.
  • the number of the data signal pins is two, and the two data signal pins are arranged along the first direction.
  • the ground signal pin is located in the same column as the stage transmission signal input pin and the stage transmission signal output pin;
  • ground signal pin and the data signal pin are located in the same column; or
  • the ground signal pin and the power signal pin are located in the same column.
  • the display panel includes a power cord, a light-emitting lamp group, a driver chip, a partition channel wiring and a ground signal wiring.
  • the ground signal wiring and the power line are spaced apart;
  • the driver chip is arranged between the power line and the ground. between the signal traces and connected to the ground signal trace;
  • the light-emitting lamp group is set between the driver chip and the power line, and one end of it is connected to the power line;
  • the partition channel line is set between the power line and the ground signal line , and connects the other end of the light-emitting lamp group to the driver chip, in which the power lines, partition channel lines and ground signal lines are arranged on the same layer.
  • the power lines, partition channel wiring and ground signal wiring are set on the same layer, which can avoid short circuits caused by the power lines, partition channel wiring and ground signal wiring being arranged on different layers. problem, thereby improving the performance of the display panel.
  • FIG. 1 is a first schematic plan view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic plan view of a light-emitting lamp group of a display panel provided by an embodiment of the present application.
  • Figure 3 is a second schematic plan view of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application provides a display panel .
  • the display panel includes a power cord, a light-emitting lamp group, a driver chip, partitioned channel wiring, and a ground signal wiring.
  • the ground signal wiring is spaced parallel to the power line; the driver chip is placed between the power line and the ground signal wiring, and is connected to the ground signal wiring.
  • the ground signal wiring is connected; the light-emitting lamp group is set between the driver chip and the power line, and one end thereof is connected to the power line; the partition channel wiring is set between the power line and the ground signal line, and it connects the light-emitting lamp group The other end is connected to the driver chip, in which the power lines, partition channel lines and ground signal lines are arranged on the same layer.
  • the power lines, partition channel wiring and ground signal wiring are set on the same layer, which can avoid short circuits caused by the power lines, partition channel wiring and ground signal wiring being arranged on different layers. problem, thereby improving the performance of the display panel.
  • FIG. 1 is a first schematic plan view of a display panel provided by an embodiment of the present application.
  • the display panel 10 includes a power line VLED, a light-emitting lamp group 100, a driver chip 200, a partitioned channel line 300, and a ground signal line GND.
  • the ground signal line GND and the power line VLED are spaced apart.
  • the driver chip 200 is disposed between the power line VLED and the ground signal line GND, and is connected to the ground signal line GND.
  • the light-emitting lamp group 100 is disposed between the driver chip 200 and the power line VLED, and one end thereof is connected to the power line VLED.
  • the partition channel wiring is set between the power line VLED and the ground signal trace GND, and connects the other end of the light-emitting lamp group 100 to the driver chip 200.
  • the power line VLED, the partition channel trace and the ground signal trace GND Same layer settings.
  • the power line VLED and the ground signal line GND are arranged in parallel.
  • the power line VLED is used to input the power signal of the external driving element into the light-emitting lamp group 100 .
  • the ground signal trace GND is a ground trace.
  • the partitioned channel wiring 300 is used to transmit signals in the driver chip 200 to the light emitting lamp group 100 .
  • the size of the driver chip 200 is less than 1500*1500um.
  • the light-emitting lamp group 100 is provided with LED lights, and the number of LED lights may be 1, 2, 4, 6, 8, 10, 12, 14 or 16, etc.
  • the distance between LED lights is not limited.
  • the LED light can be a Mini LED light.
  • the plurality of light-emitting lamp groups 100 are arranged along the first direction Y.
  • the partition channel wiring 300 includes multiple lines.
  • the plurality of driving chips 200 are arranged along the first direction Y.
  • Each driver chip 200 is provided with multiple data selection pins.
  • the plurality of data selection pins are arranged in two rows along the second direction X intersecting the first direction Y.
  • Each data selection pin is connected to a light-emitting lamp group 100 through a partitioned channel trace 300.
  • the lighting lamp group 100 includes a first lighting lamp group 110 and a second lighting lamp group 120 .
  • the light-emitting lamp group 100 is located between the power line VLED and the partition channel wiring 300 .
  • the driver chip 200 is disposed between the light-emitting lamp group 100 and the ground signal line GND.
  • the driver chip 200 includes a first data selection pin CH1 and a second data selection pin CH2.
  • the partitioned channel trace 300 includes a first partitioned channel trace 310 and a second partitioned channel trace 320 .
  • the first light-emitting lamp group 110 and the second light-emitting lamp group 120 are arranged along the first direction Y, and the first light-emitting lamp group 110 and the second light-emitting lamp group 120 are located on the same side of the driving chip 200 .
  • the first data selection pin CH1 and the second data selection pin CH2 are arranged along the first direction Y.
  • Each first light-emitting lamp group 110 is connected to a first data selection pin CH1 through a first partition channel line 310 .
  • Each second light-emitting lamp group 120 is connected to a second data selection pin CH2 through a second partition channel wiring 320 .
  • the first partition channel trace 310 and the second partition channel trace 320 are located between the power line VLED and the ground signal trace GND.
  • the first partition channel trace 310 includes a portion of the first partition channel trace 310 extending along the first direction Y and a portion of the first partition channel trace 310 extending along the second direction X.
  • the first partition channel trace 310 extends along the second direction X.
  • the channel trace 310 is connected to the first data selection pin CH1.
  • the second partition channel trace 320 includes a portion of the second partition channel trace 320 extending along the first direction Y and a portion of the second partition channel trace 320 extending along the second direction X.
  • the second partition channel trace 320 extends along the second direction X.
  • the channel trace 320 is connected to the second data selection pin CH2.
  • the lighting lamp group 100 further includes a third lighting lamp group 130 and a fourth lighting lamp group 140 .
  • the driver chip 200 is also provided with a third data selection pin CH3 and a fourth data selection pin CH4.
  • the partitioned channel trace 300 also includes a third partitioned channel trace 330 and a fourth partitioned channel trace 340 .
  • the first light-emitting lamp group 110, the second light-emitting lamp group 120, the third light-emitting lamp group 130 and the fourth light-emitting lamp group 140 are arranged along the first direction Y.
  • the first light-emitting lamp group 110 and the third light-emitting lamp group 130 and the second light-emitting lamp group 120 and the fourth light-emitting lamp group 140 are located on opposite sides of the driving chip 200 .
  • the first data selection pin CH1 and the third data selection pin CH3 are arranged in a row along the second direction X.
  • the first data selection pin CH1 is located on the side of the third data selection pin CH3 close to the power line VLED.
  • Each first light-emitting lamp group 110 is connected to a first data selection pin CH1 through a first partition channel line 310 .
  • Each third light-emitting lamp group 130 is connected to a third data selection pin CH3 through a third partition channel line 330.
  • the second data selection pin CH2 and the fourth data selection pin CH4 are arranged in another column along the second direction X.
  • the second data selection pin CH2 is located on the side of the fourth data selection pin CH4 close to the power line VLED.
  • a fourth light-emitting lamp group 140 is connected to a fourth data selection pin CH4 through a fourth partition channel line 340.
  • the first partition channel wire 310 is located between the third partition channel wire 330 and the power line VLED, and the first partition channel wire 310 is close to the side of the first light emitting lamp group 110 .
  • the third partition channel trace 330 includes a portion of the third partition channel trace 330 extending along the first direction Y and a portion of the third partition channel trace 330 extending along the second direction X.
  • the third partition channel trace 330 extending along the first direction Y is connected to the third data selection pin CH3.
  • Each fourth partition channel trace 340 includes a portion of the fourth partition channel trace 340 extending along the first direction Y and a portion of the fourth partition channel trace 340 extending along the second direction X.
  • the fourth partition channel trace 340 extending along the first direction Y is connected to the fourth data selection pin CH4.
  • the fourth partition channel trace 340 is located on the side of the second partition channel trace 320 away from the power line VLED.
  • the arrangement positions of the third light-emitting lamp group 130, the first light-emitting lamp group 110, the second light-emitting lamp group 120 and the fourth light-emitting lamp group 140 can also be exchanged in other order, and the corresponding pins can also be exchanged. And the wiring is also interchanged.
  • only one of the third luminescent lamp group 130 and the fourth luminescent lamp group 140 may be provided in the display panel 10 .
  • the display panel 10 may be provided with only one of the third partition channel wire 330 and the fourth partition channel wire 340 .
  • the driver chip 200 may be provided with only one of the third data selection pin CH3 and the fourth data selection pin CH4.
  • first partition channel trace 310 and the second partition channel trace 320, the third partition channel trace 330 and the fourth partition channel trace 340 are arranged parallel and spaced apart.
  • the driver chip 200 includes a first part and a second part connected to the first part.
  • the first part is located at the end of the driver chip 200 close to the power line VLED.
  • the first data selection pin CH1, the second data selection pin CH2, the third data selection pin CH3 and the fourth data selection pin CH4 are located on the first part.
  • the driver chip 200 includes a ground signal pin GND.
  • the ground signal pin GND is connected to the ground signal trace GND.
  • the ground signal pin GND is provided on the second part.
  • the first data selection pin CH1, the third data selection pin CH3 and the ground signal pin GND are arranged in a row along the second direction X, or the second data selection pin CH2 and the fourth data selection pin CH4
  • the ground signal pins GND are sequentially arranged in a row along the second direction X, or the ground signal pins GND form a single row along the second direction X or along the first direction Y.
  • the driver chip 200 is provided with two power signal pins Vcc. Two power signal pins Vcc are arranged on the second part along the first direction.
  • the display panel 10 includes driver chip power traces 400 .
  • the driver chip power trace 400 is disposed between adjacent driver chips 200 and is used to connect the power signal pin Vcc of the driver chip 200 .
  • the two power signal pins Vcc include a first power signal pin Vcc and a second power signal pin Vcc.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc and the ground signal pin GND are sequentially arranged in a row along the second direction
  • the selection pin CH4 and the second power signal pin Vcc are sequentially arranged in a row along the second direction X.
  • first data selection pin CH1, the third data selection pin CH3 and the first power signal pin Vcc are sequentially arranged in a row along the second direction X
  • the second power signal pin Vcc and the ground signal pin GND are sequentially arranged in a row along the second direction X.
  • the first power signal pin Vcc and the second power signal pin Vcc are sequentially arranged in a row along the first direction Y.
  • the first power signal pin Vcc and the second power signal pin Vcc of adjacent driver chips 200 are connected through the driver chip power trace 400 .
  • the driver chip power trace 400 is located between the fourth partition channel trace 340 and the ground signal trace GND.
  • the driver chip 200 is provided with a level transmission signal input pin Si and a level transmission signal output pin So.
  • the stage transmission signal input pin Si and the stage transmission signal output pin So are arranged on the second part along the first direction Y.
  • the display panel 10 also includes driver chip signal traces 600 .
  • the driver chip signal wiring 600 is disposed between adjacent driver chips 200 and is used to connect the level transmission signal input pin Si and the level transmission signal output pin So of the adjacent driver chips 200 .
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the stage transmission signal output pin So and the ground signal pin GND are sequentially arranged in a row along the second direction X
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the stage transmission signal input pin Si and the ground signal pin GND are sequentially arranged in a row along the second direction X.
  • the stage transmission signal output pin So and the stage transmission signal input pin Si are sequentially arranged in a row along the first direction Y.
  • the stage transmission signal output pin So, the ground signal pin GND and the stage transmission signal input pin Si are arranged in a row along the first direction Y, that is, the ground signal pin GND and the stage transmission signal input pin Si and the stage transmission signal input pin Si are arranged in a row along the first direction Y.
  • the signal output pin So is located in the same column.
  • the level transmission signal input pin Si and the level transmission signal output pin So of the adjacent driver chip 200 Connected through driver chip signal trace 600.
  • the driver chip signal trace 600 is located between the driver chip power trace 400 and the ground signal trace GND.
  • the driver chip power traces 400, the data transmission traces 500, and the driver chip signal traces 600 extend along the first direction Y and are arranged in parallel.
  • the driver chip 200 is provided with at least one data signal pin Data.
  • the data signal pin Data is set on the second part.
  • the display panel includes data transmission traces 500 .
  • the data transmission line 500 is connected to the data signal pin Data.
  • the number of data signal pins Data is one.
  • a data signal pin Data and a ground signal pin GND are arranged along the first direction Y.
  • the data transmission trace 500 extends along the first direction Y and is located on the side of the data signal pin Data away from the ground signal trace GND.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the stage transmission signal output pin So and the ground signal pin GND are sequentially arranged in a row along the second direction X.
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the stage transmission signal input pin Si and the data signal pin Data are sequentially arranged in a row along the second direction X. That is, the ground signal pin GND and the data signal pin Data are located in the same column.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the stage transmission signal output pin So and the data signal pin Data are sequentially arranged in a row along the second direction X.
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the stage transmission signal input pin Si and the ground signal pin GND are sequentially arranged in a row along the second direction X, that is, grounded
  • the signal pin GND and the power signal pin Vcc are in the same column.
  • the data transmission trace 500 is located between the driver chip signal trace 600 and the ground signal trace GND. Each data transmission line 500 is connected to the data signal pins Data of multiple driver chips 200 .
  • the driver chip power traces 400, the data transmission traces 500, and the driver chip signal traces 600 extend along the first direction Y and are arranged in parallel.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the stage transmission signal output pin So and the ground signal pin GND constitute a plurality of first pins .
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the stage transmission signal input pin Si and the data signal pin Data constitute a plurality of second pins.
  • the first pin and the second pin are arranged symmetrically.
  • the pins provided on the first part are interchangeable.
  • the first power signal pin Vcc, the second power signal pin Vcc, the stage transmission signal output pin So and the stage transmission pin on the second part are interchangeable.
  • the positions of the signal input pin Si can be interchanged, that is, the positions of the first data selection pin CH1, the second data selection pin CH2, the third data selection pin CH3 and the fourth data selection pin CH4 can be interchanged.
  • the positions of the first data selection pin CH1, the second data selection pin CH2, the third data selection pin CH3 and the fourth data selection pin CH4 are interchanged, the corresponding first partition channel wiring 310,
  • the positions of the second partition channel trace 320, the third partition channel trace 330, and the fourth partition channel trace 340 are also swapped accordingly.
  • the positions of the first power signal pin Vcc, the second power signal pin Vcc, the stage transmission signal output pin So and the stage transmission signal input pin Si can be interchanged.
  • the positions of the driver chip power trace 400, the driver chip signal trace 600 and the data transmission trace 500 also change accordingly.
  • the data signal pin Data and the ground signal pin GND are interchangeable. When they are interchanged, the positions of the data transmission line 500 and the ground signal line GND are also interchanged.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the stage transmission signal output pin So and the ground signal pin GND are sequentially arranged along the second direction X.
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the stage transmission signal input pin Si and the data signal pin Data are sequentially arranged along the second direction X.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the stage transmission signal output pin So and the ground signal pin GND are located on the driver chip 200 close to the first light emitting lamp group 110 and the third Three light-emitting lamp groups 130 on one side.
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the stage transmission signal input pin Si and the data signal pin Data are located on the driver chip 200 close to the second light emitting lamp group 120 and the third Four luminous lamps 140 on one side.
  • the first data selection pin CH1 and the second data selection pin CH2 are symmetrically arranged.
  • the third data selection pin CH3 and the fourth data selection pin CH4 are arranged symmetrically.
  • the first power signal pin Vcc and the second power signal pin Vcc are symmetrically arranged.
  • the stage transmission signal input pin Si and the stage transmission signal output pin So are arranged symmetrically.
  • the first partition channel trace 310 is located between the power line VLED and the third partition channel trace 330 .
  • the driver chip power trace 400 is located on the side of the third partition channel trace 330 away from the power line VLED.
  • the second partition channel trace 320 is located between the power line VLED and the fourth partition channel trace 340.
  • the driver chip power trace 400 is located on the side of the fourth partition channel trace 340 away from the power line VLED.
  • the driver chip signal trace 600 is located on the side of the driver chip power trace 400 away from the power line VLED.
  • the data transmission trace 500 is located between the driver chip signal trace 600 and the ground signal trace GND.
  • the ground signal trace GND is located on the side of the driver chip signal trace 600 away from the power line VLED, and the first partition channel trace 310, the power line VLED, the third partition channel trace 330, the fourth partition channel trace 340, and the driver
  • the chip power supply trace 400, the data transmission trace 500, the driver chip signal trace 600, the second partition channel trace 320 and the ground signal trace GND are arranged on the same layer and at intervals.
  • the wiring 600, the second partition channel wiring 320 and the ground signal wiring GND are set to the same layer and spaced apart, and the corresponding pin positions are set to reduce wiring cross-wires, thereby avoiding the problem of easy short circuits, thereby improving The yield rate of the display panel 10 is improved and the cost is reduced.
  • the positive pole of the LED lamp power supply is transmitted to the light-emitting lamp group 100 through the power line VLED.
  • the driver chip 200 is a driver chip 200 that outputs a constant current source. After the data signal, power signal, ground signal and level transmission signal are transmitted to the driver chip 200, The data signal will be converted into each Output output current after being processed by the driver chip 200, and transmitted to each light-emitting lamp group so that it emits light normally, that is, the display panel 10 works.
  • FIG. 2 is a schematic plan view of the light-emitting lamp group 100 of the display panel 10 provided by an embodiment of the present application.
  • FIG. 3 is a second schematic plan view of the display panel 10 provided by an embodiment of the present application.
  • the LEDs in the light-emitting lamp group 100 can be arranged in two series or two in parallel.
  • the number of data signal pins Data is two.
  • the two data signal pins Data are arranged along the first direction Y.
  • the data signal pin Data includes a first data signal pin Data and a second data signal pin Data.
  • the first power signal pin Vcc, the second power signal pin Vcc, the stage transmission signal output pin So, the stage transmission signal input pin Si, the first data signal pin Data and the second data signal pin Data are located on the second Partially.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the first data signal pin Data and the stage transmission signal output pin So are sequentially arranged in a row along the second direction X.
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the second data signal pin Data, and the stage transmission signal input pin Si are sequentially arranged in a row along the second direction X.
  • the cascade signal output pin So, the ground signal pin GND and the cascade signal output pin So are sequentially arranged in a row along the first direction Y. That is, the first data signal pin Data and the second data signal pin Data are arranged symmetrically.
  • the data transmission line 500 is provided between two adjacent driver chips 200 .
  • the first data signal pin Data and the second data signal pin Data of two adjacent driving chips 200 are connected through a data transmission line 500 .
  • the driver chip 200 further includes an empty pin NG.
  • the empty pin NG is located in the first section.
  • the first data selection pin CH1, the empty pin NG, and the second data selection pin CH2 are sequentially arranged in a row along the first direction Y.
  • first power signal pin Vcc, the second power signal pin Vcc, the stage transmission signal output pin So, the stage transmission signal input pin Si, and the first data signal pin Data on the first part The positions of the second data signal pin Data can be interchanged, and the corresponding wiring positions can also be interchanged.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the first data signal pin Data, and the stage transmission signal output pin So are arranged in sequence along the second direction X.
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the second data signal pin Data, and the stage transmission signal input pin Si are sequentially arranged along the second direction X.
  • the empty pin NG and the ground signal pin GND are arranged in sequence along the second direction X, and the first data selection pin, the empty pin NG and the second data selection pin are arranged in sequence along the first direction Y.
  • the first data selection pin pin, the empty pin NG and the second data selection pin are located on the side of the driver chip 200 close to the power line VLED.
  • the cascade signal output pin So, the ground signal pin GND and the cascade signal input pin Si are arranged in sequence along the first direction Y.
  • the cascade signal output pin So, the ground signal pin GND and the cascade signal input pin Si Located on the side of the second part away from the power line VLED.
  • the first data selection pin CH1, the third data selection pin CH3, the first power signal pin Vcc, the first data signal pin Data and the level transmission signal output pin So are located on the driver chip 200 close to the first light emitting lamp group 110 side.
  • the second data selection pin CH2, the fourth data selection pin CH4, the second power signal pin Vcc, the second data signal pin Data and the stage transmission signal input pin Si are located on the driver chip 200 close to the second light emitting lamp group 120 side.
  • the data transmission trace 500 is located on the side of the driver chip power trace 400 away from the power line VLED, and is located between the data transmission trace 500 and the ground signal trace GND.
  • the second partition channel trace is located between the power line VLED and the fourth partition channel trace 340; the driver chip signal trace 600 is located between the data transmission trace 500 and the ground signal trace GND, and the first partition channel trace 310 , power line VLED, third partition channel trace 330, fourth partition channel trace 340, driver chip power trace 400, data transmission trace 500, driver chip signal trace 600, second partition channel trace 320 and grounding
  • the signal traces GND should be on the same layer and spaced apart.
  • the wiring 600, the second partition channel wiring 320 and the ground signal wiring GND are set to the same layer and spaced apart, and the corresponding pin positions are set to reduce wiring cross-wires, thereby avoiding the problem of easy short circuits, thereby improving
  • the yield rate of the display panel 10 is improved and the cost is reduced; at the same time, empty pins are provided in the driver chip 200 so that the pin arrangement of the driver chip 200 is balanced and symmetrical, simplifying the preparation process of the driver chip 200 and shortening the production cycle, thus cut costs.
  • the display panel 10 provided in this application can be a Mini LED backlight product or a Mini LED display screen product.
  • the display panel 10 includes a power line VLED, a light-emitting lamp group 100, a driver chip 200, a partitioned channel line 300, and a ground signal line GND.
  • the ground signal line GND is spaced apart from the power line VLED.
  • the driver chip 200 is arranged between the power line VLED and the ground signal line GND, and is connected to the ground signal line GND; the light-emitting lamp group 100 is arranged between the driver chip 200 and the power line VLED, and one end thereof is connected to the power line VLED.
  • the partition channel wiring is set between the power line VLED and the ground signal wiring GND, and connects the other end of the light-emitting lamp group 100 to the driver chip 200, wherein the power line VLED, the partitioning channel wiring and the ground signal wiring GND same layer setting.
  • the power line VLED, the partition channel wiring, and the ground signal trace GND are set on the same layer, and the arrangement design of the pins in the driver chip 200 is changed to avoid the power line VLED, the partition channel wiring Since the ground signal traces GND are arranged on different layers, short circuit problems may occur. This also reduces costs and improves the performance of the display panel 10 .
  • a display panel provided by the embodiments of the present application has been introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the methods and methods of the present application. Its core idea; at the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the ideas of this application. In summary, the content of this description should not be understood as a limitation of this application. .

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Abstract

一种显示面板(10)，包括电源线VLED、发光灯组(100)、分区通道走线(300)、驱动芯片(200)以及接地信号走线GND；驱动芯片(200)、发光灯组(100)以及分区通道走线(300)设置在间隔设置的电源线VLED和接地信号走线GND之间，驱动芯片(200)与接地信号走线GND连接；发光灯组(100)与电源线VLED连接；分区通道走线(300)将发光灯组(100)与驱动芯片(200)连接，电源线VLED、接地信号走线GND以及分区通道走线(300)同层设置。

Description

显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板。
 背景技术
迷你发光二极管（Mini LED）又名“次毫米发光二极管”，指由晶粒（芯片）尺寸在50微米至200微米的LED构成的显示屏，介于Micro LED和小间距显示之间。被广泛应用于Mini LED直显和Mini LED背光的显示屏中。
目前的产品中，金属走线方式都是两层及以上的金属走线方式，如接地走线、分区通道走线以及电源线等设置在不同层，这样设置的走线方式会使得不同金属层间出现易short的问题，即易短路，造成成本较高等问题。
 技术问题
本申请实施例提供一种显示面板，以解决现有技术中接地走线、分区通道走线以及电源线设置在两层及以上时，造成易短路的问题。
 技术解决方案
本申请提供一种显示面板，其中，所述显示面板包括：
电源线；
接地信号走线，与所述电源线间隔设置，所述接地信号走线与所述电源线沿第 一方向排列；
驱动芯片，设置在所述电源线与所述接地信号走线之间，并与所述接地信号走线连接；
发光灯组，设置在所述接地信号走线与所述电源线之间，所述发光灯组的一端与所述电源线连接；以及
分区通道走线，设置在所述电源线与所述接地信号走线之间，所述分区通道走线将所述发光灯组的另一端与所述驱动芯片连接；
其中，所述电源线、所述分区通道走线以及所述接地信号走线同层设置。
可选的，在本申请的一些实施例中，所述发光灯组包括多个，多个所述发光灯组沿所述第一方向排列，所述分区通道走线包括多条，所述驱动芯片中设置有多个数据选择管脚，多个所述数据选择管脚沿所述第一方向和/或与所述第一方向相交的第二方向设置，每一所述数据选择管脚通过一所述分区通道走线与一所述发光灯组连接。
可选的，在本申请的一些实施例中，所述发光灯组包括第一发光灯组和第二发光灯组，所述驱动芯片包括第一数据选择管脚和第二数据选择管脚，所述分区通道走线包括第一分区通道走线和第二分区通道走线；
所述第一发光灯组与所述第二发光灯组沿所述第一方向排列；
所述第一数据选择管脚和所述第二数据选择管脚沿所述第一方向排列；
其中，所述第一发光灯组与所述第一数据选择管脚通过所述第一分区通道走线连接，所述第二发光灯组通过所述第二分区通道走线与所述第二数据选择管脚连接。
可选的，在本申请的一些实施例中，所述发光灯组还包括第三发光灯组和第四发光灯组，所述驱动芯片还设置有第三数据选择管脚和第四数据选择管脚，所述分区通道走线还包括第三分区通道走线和第四分区通道走线；
所述第一发光灯组、所述第二发光灯组、所述第三发光灯组以及第四发光灯组沿所述第一方向排列；
所述第一数据选择管脚和所述第三数据选择管脚沿第二方向排成一列，所述第一数据选择管脚位于所述第三数据选择管脚靠近所述电源线的一侧；
所述第二数据选择管脚和所述第四数据选择管脚沿第二方向排成另一列，所述第二数据选择管脚位于所述第四数据选择管脚靠近所述电源线的一侧；
其中，一所述第三发光灯组与一所述第三数据选择管脚通过一所述第三分区通道走线连接，一所述第四发光灯组与一所述第四数据选择管脚通过一所述第四分区通道走线连接。
可选的，在本申请的一些实施例中，所述驱动芯片包括第一部分和与所述第一部分连接的第二部分，所述第一部分位于所述驱动芯片靠近所述电源线的端部，所述第一数据选择管脚、所述第二数据选择管脚、所述第三数据选择管脚以及所述第四数据选择管脚位于所述第一部分上；所述驱动芯片包括接地信号管脚，所述接地信号管脚与所述接地信号走线连接，所述接地信号管脚设置于所述第二部分上。
可选的，在本申请的一些实施例中，所述驱动芯片设置有两个电源信号管脚，所述两个电源信号管脚沿所述第一方向设置在所述第二部分上，所述显示面板包括驱动芯片电源走线，所述驱动芯片电源走线设置于相邻所述驱动芯片之间，用于连接所述驱动芯片的电源信号管脚。
可选的，在本申请的一些实施例中，所述驱动芯片设置有级传信号输入管脚以及级传信号输出管脚，所述级传信号输入管脚以及所述级传信号输出管脚沿所述第一方向设置在所述第二部分上，所述显示面板还包括驱动芯片信号走线，所述驱动芯片信号走线设置于相邻所述驱动芯片之间，用于连接相邻所述驱动芯片的所述级传信号输入管脚和所述级传信号输出管脚。
可选的，在本申请的一些实施例中，所述驱动芯片设置有至少一个数据信号管脚，所述数据信号管脚设置于所述第二部分上，所述显示面板包括数据传输走线，所述数据传输走线与所述数据信号管脚连接。
可选的，在本申请的一些实施例中，所述数据信号管脚的数量为一个，一个所述数据信号管脚与所述接地信号管脚沿所述第一方向设置，所述数据传输走线沿所述第一方向延伸，并位于所述数据信号管脚背离所述接地信号走线的一侧。
相应的，本申请还提供一种显示面板，所述显示面板包括：
电源线；
接地信号走线，与所述电源线间隔设置；
驱动芯片，设置在所述电源线与所述接地信号走线之间，并与所述接地信号走线连接；
发光灯组，设置在所述接地信号走线与所述电源线之间，所述发光灯组的一端与所述电源线连接；以及
分区通道走线，设置在所述电源线与所述接地信号走线之间，所述分区通道走线将所述发光灯组的另一端与所述驱动芯片连接；
其中，所述电源线、所述分区通道走线以及所述接地信号走线同层设置。
可选的，在本申请的一些实施例中，所述发光灯组包括多个，多个所述发光灯组沿第一方向排列，所述分区通道走线包括多条，所述驱动芯片中设置有多个数据选择管脚，多个所述数据选择管脚沿所述第一方向和/或与所述第一方向相交的第二方向设置，每一所述数据选择管脚通过一所述分区通道走线与一所述发光灯组连接。
可选的，在本申请的一些实施例中，所述发光灯组包括第一发光灯组和第二发光灯组，所述驱动芯片包括第一数据选择管脚和第二数据选择管脚，所述分区通道走线包括第一分区通道走线和第二分区通道走线；
所述第一发光灯组与所述第二发光灯组沿第一方向排列；
所述第一数据选择管脚和所述第二数据选择管脚沿所述第一方向排列；
其中，所述第一发光灯组与所述第一数据选择管脚通过所述第一分区通道走线连接，所述第二发光灯组通过所述第二分区通道走线与所述第二数据选择管脚连接。
可选的，在本申请的一些实施例中，所述发光灯组还包括第三发光灯组和第四发光灯组，所述驱动芯片还设置有第三数据选择管脚和第四数据选择管脚，所述分区通道走线还包括第三分区通道走线和第四分区通道走线；
所述第一发光灯组、所述第二发光灯组、所述第三发光灯组以及第四发光灯组沿所述第一方向排列，且所述第一发光灯组以及所述第三发光灯组与所述第二发光灯组以及所述第四发光灯组位于所述驱动芯片的相对两侧；
所述第一数据选择管脚和所述第三数据选择管脚沿第二方向排成一列，所述第一数据选择管脚位于所述第三数据选择管脚靠近所述电源线的一侧；
所述第二数据选择管脚和所述第四数据选择管脚沿第二方向排成另一列，所述第二数据选择管脚位于所述第四数据选择管脚靠近所述电源线的一侧。
其中，一所述第三发光灯组与一所述第三数据选择管脚通过一所述第三分区通道走线连接，一所述第四发光灯组与一所述第四数据选择管脚通过一所述第四分区通道走线连接。
可选的，在本申请的一些实施例中，所述驱动芯片包括第一部分和与所述第一部分连接的第二部分，所述第一部分位于所述驱动芯片靠近所述电源线的端部，所述第一数据选择管脚、所述第二数据选择管脚、所述第三数据选择管脚以及所述第四数据选择管脚位于所述第一部分上；所述驱动芯片包括接地信号管脚，所述接地信号管脚与所述接地信号走线连接，所述接地信号管脚设置于所述第二部分上。
可选的，在本申请的一些实施例中，所述驱动芯片设置有两个电源信号管脚，所述两个电源信号管脚沿所述第一方向设置在所述第二部分上，所述显示面板包括驱动芯片电源走线，所述驱动芯片电源走线设置于相邻所述芯片之间，用于连接所述驱动芯片的电源信号管脚。
可选的，在本申请的一些实施例中，所述驱动芯片设置有级传信号输入管脚以及级传信号输出管脚，所述级传信号输入管脚以及所述级传信号输出管脚沿所述第一方向设置在所述第二部分上，所述显示面板还包括驱动芯片信号走线，所述驱动芯片信号走线设置于相邻所述驱动芯片之间，用于连接相邻所述驱动芯片的所述级传信号输入管脚和所述级传信号输出管脚。
可选的，在本申请的一些实施例中，所述驱动芯片设置有至少一个数据信号管脚，所述数据信号管脚设置于所述第二部分上，所述显示面板包括数据传输走线，所述数据传输走线与所述数据信号管脚连接。
可选的，在本申请的一些实施例中，所述数据信号管脚的数量为一个，一个所述数据信号管脚与所述接地信号管脚沿所述第一方向设置所述数据传输走线沿所述第一方向延伸，并位于所述数据信号管脚背离所述接地信号走线的一侧。
可选的，在本申请的一些实施例中，所述数据信号管脚的数量为二个，二个所述数据信号引脚沿所述第一方向设置。
可选的，在本申请的一些实施例中，所述接地信号管脚与所述级传信号输入管脚以及所述级传信号输出管脚位于同一列；或者
所述接地信号管脚与所述数据信号管脚位于同一列；或者
所述接地信号管脚与所述电源信号管脚位于同一列。
 有益效果
本申请公开了一种显示面板，显示面板包括电源线、发光灯组、驱动芯片、分区通道走线以及接地信号走线，接地信号走线与电源线间隔设置；驱动芯片设置在电源线与接地信号走线之间，并与接地信号走线连接；发光灯组设置在驱动芯片与电源线之间，且其一端与电源线连接；分区通道走线设置在电源线与接地信号走线之间，且其将发光灯组的另一端与驱动芯片连接，其中，电源线、分区通道走线以及接地信号走线同层设置。在本申请中，将电源线、分区通道走线以及接地信号走线设置为同层设置，可以避免电源线、分区通道走线以及接地信号走线之间因设置在不同层，而导致出现短路问题，从而提高显示面板的性能。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的第一种平面示意图。
图2是本申请实施例提供的显示面板的发光灯组平面示意图。
图3是本申请实施例提供的显示面板的第二种平面示意图；
附图标记：
第一方向Y；第二方向X；显示面板10；发光灯组100；第一发光灯组110；第二发光灯组120；第三发光灯组130；第四发光灯组140；驱动芯片200；分区通道走线300；第一分区通道走线310；第二分区通道走线320；第三分区通道走线330；第四分区通道走线340；驱动芯片电源走线400；数据传输走线500；驱动芯片信号走线600。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。在本申请中，“反应”可以为化学反应或物理反应。
本申请实施例提供一种显示面板 。显示面板包括电源线、发光灯组、驱动芯片、分区通道走线以及接地信号走线，接地信号走线与电源线平行间隔设置；驱动芯片设置在电源线与接地信号走线之间，并与接地信号走线连接；发光灯组设置在驱动芯片与电源线之间，且其一端与电源线连接；分区通道走线设置在电源线与接地信号走线之间，且其将发光灯组的另一端与驱动芯片连接，其中，电源线、分区通道走线以及接地信号走线同层设置。
在本申请中，将电源线、分区通道走线以及接地信号走线设置为同层设置，可以避免电源线、分区通道走线以及接地信号走线之间因设置在不同层，而导致出现短路问题，从而提高显示面板的性能。
以下进行详细说明：
请参阅图1，图1是本申请实施例提供的显示面板的第一种平面示意图。显示面板10包括电源线VLED、发光灯组100、驱动芯片200、分区通道走线300以及接地信号走线GND。接地信号走线GND与电源线VLED间隔设置。驱动芯片200设置在电源线VLED与接地信号走线GND之间，并与接地信号走线GND连接。发光灯组100设置在驱动芯片200与电源线VLED之间，且其一端与电源线VLED连接。分区通道走线设置在电源线VLED与接地信号走线GND之间，且其将发光灯组100的另一端与驱动芯片200连接，其中，电源线VLED、分区通道走线以及接地信号走线GND同层设置。
在一实施例中，电源线VLED与接地信号走线GND平行设置。
电源线VLED用于将外驱动元件的电源信号输入发光灯组100中。接地信号走线GND为接地走线。分区通道走线300用于将驱动芯片200中的信号传输至发光灯组100。驱动芯片200的尺寸小于1500*1500um。
发光灯组100中设置有LED灯，LED灯的数量可以为1个、2个、4个、6个、8个、10个、12个、14个或16个等。LED灯之间的距离不限制。LED灯可以为Mini LED灯。
在一实施例中，发光灯组100的数量具有多个。多个发光灯组100沿第一方向Y排列。分区通道走线300包括多条。驱动芯片200具有多个。多个驱动芯片200沿第一方向Y排列。每一驱动芯片200中设置有多个数据选择管脚。多个数据选择管脚沿与第一方向Y相交的第二方向X排列成两排。每一数据选择管脚通过一分区通道走线300与一发光灯组100连接。
在一实施例中，发光灯组100包括第一发光灯组110和第二发光灯组120。发光灯组100位于电源线VLED与分区通道走线300之间。驱动芯片200设置于发光灯组100与接地信号走线GND之间。驱动芯片200包括第一数据选择管脚CH1和第二数据选择管脚CH2。分区通道走线300包括第一分区通道走线310和第二分区通道走线320。第一发光灯组110与第二发光灯组120沿第一方向Y排列，且第一发光灯组110与第二发光灯组120位于驱动芯片200的同一侧。第一数据选择管脚CH1和第二数据选择管脚CH2沿第一方向Y排列。每一第一发光灯组110与一第一数据选择管脚CH1通过一第一分区通道走线310连接。每一第二发光灯组120通过一第二分区通道走线320与一第二数据选择管脚CH2连接。第一分区通道走线310以及第二分区通道走线320位于电源线VLED与接地信号走线GND之间。第一分区通道走线310包括部分沿第一方向Y延伸的第一分区通道走线310和部分沿第二方向X延伸的第一分区通道走线310，沿第二方向X延伸的第一分区通道走线310与第一数据选择管脚CH1连接。第二分区通道走线320包括部分沿第一方向Y延伸的第二分区通道走线320和部分沿第二方向X延伸的第二分区通道走线320，沿第二方向X延伸的第二分区通道走线320与第二数据选择管脚CH2连接。
在一实施例中，发光灯组100还包括第三发光灯组130和第四发光灯组140。驱动芯片200还设置有第三数据选择管脚CH3和第四数据选择管脚CH4。分区通道走线300还包括第三分区通道走线330和第四分区通道走线340。第一发光灯组110、第二发光灯组120、第三发光灯组130以及第四发光灯组140沿第一方向Y排列。第一发光灯组110以及第三发光灯组130与第二发光灯组120以及第四发光灯组140位于驱动芯片200的相对两侧。第一数据选择管脚CH1和第三数据选择管脚CH3沿第二方向X排成一列。第一数据选择管脚CH1位于第三数据选择管脚CH3靠近电源线VLED的一侧。每一第一发光灯组110与一第一数据选择管脚CH1通过一第一分区通道走线310连接。每一第三发光灯组130与一第三数据选择管脚CH3通过一第三分区通道走线330连接。第二数据选择管脚CH2和第四数据选择管脚CH4沿第二方向X排成另一列。第二数据选择管脚CH2位于第四数据选择管脚CH4靠近电源线VLED的一侧。一第四发光灯组140与一第四数据选择管脚CH4通过一第四分区通道走线340连接。
具体的，第一分区通道走线310位于第三分区通道走线330与电源线VLED之间，且第一分区通道走线310靠近第一发光灯组110的一侧。第三分区通道走线330包括部分沿第一方向Y延伸的第三分区通道走线330和部分沿第二方向X延伸的第三分区通道走线330。沿第一方向Y延伸的第三分区通道走线330与第三数据选择管脚CH3连接。每一第四分区通道走线340包括部分沿第一方向Y延伸的第四分区通道走线340和部分沿第二方向X延伸的第四分区通道走线340。沿第一方向Y延伸的第四分区通道走线340与第四数据选择管脚CH4连接。第四分区通道走线340位于所述第二分区通道走线320远离电源线VLED的一侧。
需要说明的是，第三发光灯组130、第一发光灯组110、第二发光灯组120以及第四发光灯组140之间的排列位置也可以互换其他排列顺序，同时相应的管脚以及走线也互换。
在一实施例中，显示面板10中可以只设置有第三发光灯组130和第四发光灯组140中的一个。显示面板10中可以只设置有第三分区通道走线330和第四分区通道走线340中的一条。驱动芯片200中可以只设置有第三数据选择管脚CH3和第四数据选择管脚CH4中的一个。
在一实施例中，第一分区通道走线310和第二分区通道走线320、第三分区通道走线330和第四分区通道走线340之间平行且间隔设置。
在一实施例中，驱动芯片200包括第一部分和与第一部分连接的第二部分。第一部分位于驱动芯片200靠近电源线VLED的端部。第一数据选择管脚CH1、第二数据选择管脚CH2、第三数据选择管脚CH3以及第四数据选择管脚CH4位于第一部分上。驱动芯片200包括接地信号管脚GND。接地信号管脚GND与接地信号走线GND连接。接地信号管脚GND设置于第二部分上。具体的，第一数据选择管脚CH1、第三数据选择管脚CH3以及接地信号管脚GND依次沿第二方向X排列成一列，或者第二数据选择管脚CH2、第四数据选择管脚CH4以及接地信号管脚GND依次沿第二方向X排列成一列，或者接地信号管脚GND沿第二方向X或沿第一方向Y单独形成一列。
在一实施例中，驱动芯片200设置有两个电源信号管脚Vcc。两个电源信号管脚Vcc沿第一方向设置在第二部分上。显示面板10包括驱动芯片电源走线400。驱动芯片电源走线400设置于相邻驱动芯片200之间，用于连接驱动芯片200的电源信号管脚Vcc。具体的，两个电源信号管脚Vcc包括第一电源信号管脚Vcc和第二电源信号管脚Vcc。第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc以及接地信号管脚GND依次沿第二方向X排列成一列，第二数据选择管脚CH2、第四数据选择管脚CH4以及第二电源信号管脚Vcc依次沿第二方向X排列成一列。或者第一数据选择管脚CH1、第三数据选择管脚CH3以及第一电源信号管脚Vcc依次沿第二方向X排列成一列，第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc以及接地信号管脚GND依次沿第二方向X排列成一列。第一电源信号管脚Vcc和第二电源信号管脚Vcc依次沿第一方向Y排列成一列。相邻的驱动芯片200的第一电源信号管脚Vcc和第二电源信号管脚Vcc通过驱动芯片电源走线400连接。驱动芯片电源走线400位于第四分区通道走线340与接地信号走线GND之间。
在一实施例中，驱动芯片200设置有级传信号输入管脚Si以及级传信号输出管脚So。级传信号输入管脚Si以及级传信号输出管脚So沿第一方向Y设置在第二部分上。显示面板10还包括驱动芯片信号走线600。驱动芯片信号走线600设置于相邻驱动芯片200之间，用于连接相邻驱动芯片200的级传信号输入管脚Si和级传信号输出管脚So。具体的，第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、级传信号输出管脚So以及接地信号管脚GND依次沿第二方向X排列成一列，第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、级传信号输入管脚Si以及接地信号管脚GND依次沿第二方向X排列成一列。级传信号输出管脚So和级传信号输入管脚Si依次沿第一方向Y排列成一列。或者级传信号输出管脚So、接地信号管脚GND和级传信号输入管脚Si依次沿第一方向Y排列成一列，也即接地信号管脚GND与级传信号输入管脚Si以及级传信号输出管脚So位于同一列。相邻的驱动芯片200的级传信号输入管脚Si和级传信号输出管脚So。通过驱动芯片信号走线600连接。驱动芯片信号走线600位于驱动芯片电源走线400与接地信号走线GND之间。
在一实施例中，驱动芯片电源走线400、数据传输走线500以及驱动芯片信号走线600之间沿第一方向Y延伸且平行设置。
在一实施例中，驱动芯片200设置有至少一个数据信号管脚Data。数据信号管脚Data设置于第二部分上。显示面板包括数据传输走线500。数据传输走线500与数据信号管脚Data连接。具体的，数据信号管脚Data的数量为一个。一个数据信号管脚Data与接地信号管脚GND沿第一方向Y设置。数据传输走线500沿第一方向Y延伸，并位于数据信号管脚Data背离接地信号走线GND的一侧。进一步的，第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、级传信号输出管脚So以及接地信号管脚GND依次沿第二方向X排列成一列。第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、级传信号输入管脚Si以及数据信号管脚Data依次沿第二方向X排列成一列。也即接地信号管脚GND与数据信号管脚Data位于同一列。或者，第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、级传信号输出管脚So以及数据信号管脚Data依次沿第二方向X排列成一列。第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、级传信号输入管脚Si以及接地信号管脚GND依次沿第二方向X排列成一列，也即接地信号管脚GND与电源信号管脚Vcc位于同一列。数据传输走线500位于驱动芯片信号走线600与接地信号走线GND之间。每一数据传输走线500与多个驱动芯片200的数据信号管脚Data连接。
在一实施例中，驱动芯片电源走线400、数据传输走线500以及驱动芯片信号走线600沿第一方向Y延伸并平行设置。
在一实施例中，第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、级传信号输出管脚So以及接地信号管脚GND构成多个第一管脚。第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、级传信号输入管脚Si以及数据信号管脚Data构成多个第二管脚。第一管脚与第二管脚对称设置。
需要说明的是，设置在第一部分上的管脚之间可以互换，第二分部上的第一电源信号管脚Vcc、第二电源信号管脚Vcc、级传信号输出管脚So以及级传信号输入管脚Si的位置可以互换，也即，第一数据选择管脚CH1、第二数据选择管脚CH2、第三数据选择管脚CH3以及第四数据选择管脚CH4的位置可以互换，当第一数据选择管脚CH1、第二数据选择管脚CH2、第三数据选择管脚CH3以及第四数据选择管脚CH4的位置互换时，相应的第一分区通道走线310、第二分区通道走线320、第三分区通道走线330以及第四分区通道走线340的位置也跟着相应的互换。第一电源信号管脚Vcc、第二电源信号管脚Vcc、级传信号输出管脚So以及级传信号输入管脚Si的位置可以互换，当第一电源信号管脚Vcc、第二电源信号管脚Vcc、级传信号输出管脚So以及级传信号输入管脚Si的位置互换时，驱动芯片电源走线400、驱动芯片信号走线600以及数据传输走线500的位置也相应的改变。数据信号管脚Data与接地信号管脚GND可以互换，其互换的同时，数据传输走线500与接地信号走线GND的位置也同样互换。
作为示例，第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、级传信号输出管脚So以及接地信号管脚GND依次沿第二方向X排列。第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、级传信号输入管脚Si以及数据信号管脚Data依次沿第二方向X排列。第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、级传信号输出管脚So以及接地信号管脚GND位于驱动芯片200靠近第一发光灯组110以及第三发光灯组130的一侧。第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、级传信号输入管脚Si以及数据信号管脚Data位于驱动芯片200靠近第二发光灯组120以及第四发光灯组140的一侧。第一数据选择管脚CH1与第二数据选择管脚CH2对称设置。第三数据选择管脚CH3与第四数据选择管脚CH4对称设置。第一电源信号管脚Vcc与第二电源信号管脚Vcc对称设置。级传信号输入管脚Si与级传信号输出管脚So对称设置。
接着，第一分区通道走线310位于电源线VLED与第三分区通道走线330之间。驱动芯片电源走线400位于第三分区通道走线330远离电源线VLED的一侧。第二分区通道走线320位于电源线VLED与第四分区通道走线340之间。驱动芯片电源走线400位于第四分区通道走线340远离电源线VLED的一侧。驱动芯片信号走线600位于驱动芯片电源走线400远离电源线VLED的一侧。数据传输走线500位于驱动芯片信号走线600与接地信号走线GND之间。接地信号走线GND位于驱动芯片信号走线600远离电源线VLED的一侧，且第一分区通道走线310、电源线VLED、第三分区通道走线330、第四分区通道走线340、驱动芯片电源走线400、数据传输走线500、驱动芯片信号走线600、第二分区通道走线320以及接地信号走线GND同层且间隔设置。
在本申请中，将第一分区通道走线310、电源线VLED、第三分区通道走线330、第四分区通道走线340、驱动芯片电源走线400、数据传输走线500、驱动芯片信号走线600、第二分区通道走线320以及接地信号走线GND设置为同层且间隔设置，并设置相应的管脚位置，减少了布线的跨线，从而避免出现易短路的问题，从而提高显示面板10的良率，并降低成本。
工作原理：LED灯电源正极经电源线VLED传输至发光灯组100，驱动芯片200为输出恒流源的驱动芯片200，数据信号、电源信号、接地信号以及级传信号传输至驱动芯片200后，数据信号经过驱动芯片200处理会转变成每个Output输出电流，传输至每个发光灯组使得正常其发光，即使得显示面板10工作。
请参阅图2，图2是本申请实施例提供的显示面板10的发光灯组100平面示意图，图3是本申请实施例提供的显示面板10的第二种平面示意图。发光灯组100中的LED可以设置为两串或两并。
请参阅图3，需要说明的是，第二种结构与第一种结构的不同之处在于：
数据信号管脚Data的数量为二个。二个数据信号管脚Data沿第一方向Y设置。具体的，数据信号管脚Data包括第一数据信号管脚Data和第二数据信号管脚Data。第一电源信号管脚Vcc、第二电源信号管脚Vcc、级传信号输出管脚So、级传信号输入管脚Si、第一数据信号管脚Data以及第二数据信号管脚Data位于第二部分上。第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、第一数据信号管脚Data以及级传信号输出管脚So依次沿第二方向X排列成一列，第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、第二数据信号管脚Data以及级传信号输入管脚Si依次沿第二方向X排列成一列。级传信号输出管脚So、接地信号管脚GND以及级传信号输出管脚So依次沿第一方向Y排成一列。也即第一数据信号管脚Data与第二数据信号管脚Data对称设置。以及数据传输走线500设置于相邻的两个驱动芯片200之间。相邻两个驱动芯片200的第一数据信号管脚Data和第二数据信号管脚Data通过数据传输走线500连接。
在一实施例中，驱动芯片200还包括空管脚NG。空管脚NG位于第一部分。第一数据选择管脚CH1、空管脚NG以及第二数据选择管脚CH2依次沿第一方向Y排成一列。
需要说明的是，第一分部上的第一电源信号管脚Vcc、第二电源信号管脚Vcc、级传信号输出管脚So、级传信号输入管脚Si、第一数据信号管脚Data以及第二数据信号管脚Data的位置可以互换，同时相应的走线位置也互换。
作为示例，第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、第一数据信号管脚Data以及级传信号输出管脚So依次沿第二方向X排列。第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、第二数据信号管脚Data以及级传信号输入管脚Si依次沿第二方向X排列。空管脚NG与接地信号管脚GND依次沿第二方向X排列，且第一数据选择管脚、空管脚NG以及第二数据选择管脚依次沿第一方向Y排列，第一数据选择管脚、空管脚NG以及第二数据选择管脚位于驱动芯片200靠近电源线VLED的一侧。级传信号输出管脚So、接地信号管脚GND以及级传信号输入管脚Si依次沿第一方向Y排列，级传信号输出管脚So、接地信号管脚GND以及级传信号输入管脚Si位于第二部分远离电源线VLED的一侧。第一数据选择管脚CH1、第三数据选择管脚CH3、第一电源信号管脚Vcc、第一数据信号管脚Data以及级传信号输出管脚So位于驱动芯片200靠近第一发光灯组110的一侧。第二数据选择管脚CH2、第四数据选择管脚CH4、第二电源信号管脚Vcc、第二数据信号管脚Data以及级传信号输入管脚Si位于驱动芯片200靠近第二发光灯组120的一侧。数据传输走线500位于驱动芯片电源走线400远离电源线VLED的一侧，位于数据传输走线500与接地信号走线GND之间。第二分区通道走线位于电源线VLED与第四分区通道走线340之间；驱动芯片信号走线600位于数据传输走线500与接地信号走线GND之间，且第一分区通道走线310、电源线VLED、第三分区通道走线330、第四分区通道走线340、驱动芯片电源走线400、数据传输走线500、驱动芯片信号走线600、第二分区通道走线320以及接地信号走线GND同层且间隔设置。
在本申请中，将第一分区通道走线310、电源线VLED、第三分区通道走线330、第四分区通道走线340、驱动芯片电源走线400、数据传输走线500、驱动芯片信号走线600、第二分区通道走线320以及接地信号走线GND设置为同层且间隔设置，并设置相应的管脚位置，减少了布线的跨线，从而避免出现易短路的问题，从而提高显示面板10的良率，并降低成本；同时，在驱动芯片200中设置空管脚，使得驱动芯片200的管脚排布平衡对称，简化了驱动芯片200的制备工艺，缩短了生产周期，从而降低成本。
需要说明的是，本申请提供的显示面板10可以为Mini LED背光源产品或者为Mini LED显示屏产品。
本申请公开了一种显示面板10，显示面板10包括电源线VLED、发光灯组100、驱动芯片200、分区通道走线300以及接地信号走线GND，接地信号走线GND与电源线VLED间隔设置。驱动芯片200设置在电源线VLED与接地信号走线GND之间，并与接地信号走线GND连接；发光灯组100设置在驱动芯片200与电源线VLED之间，且其一端与电源线VLED连接；分区通道走线设置在电源线VLED与接地信号走线GND之间，且其将发光灯组100的另一端与驱动芯片200连接，其中，电源线VLED、分区通道走线以及接地信号走线GND同层设置。在本申请中，将电源线VLED、分区通道走线以及接地信号走线GND设置为同层设置，且改变驱动芯片200中的管脚的排布设计，可以避免电源线VLED、分区通道走线以及接地信号走线GND之间因设置在不同层，而导致出现短路问题，同时降低成本，从而提高显示面板10的性能。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    电源线；
    接地信号走线，与所述电源线间隔设置，所述接地信号走线与所述电源线沿第 一方向排列；
    驱动芯片，设置在所述电源线与所述接地信号走线之间，并与所述接地信号走线连接；
    发光灯组，设置在所述接地信号走线与所述电源线之间，所述发光灯组的一端与所述电源线连接；以及
    分区通道走线，设置在所述电源线与所述接地信号走线之间，所述分区通道走线将所述发光灯组的另一端与所述驱动芯片连接；
    其中，所述电源线、所述分区通道走线以及所述接地信号走线同层设置。
  2. 根据权利要求1所述的显示面板，其中，所述发光灯组包括多个，多个所述发光灯组沿所述第一方向排列，所述分区通道走线包括多条，所述驱动芯片中设置有多个数据选择管脚，多个所述数据选择管脚沿所述第一方向和/或与所述第一方向相交的第二方向设置，每一所述数据选择管脚通过一所述分区通道走线与一所述发光灯组连接。
  3. 根据权利要求1所述的显示面板，其中，所述发光灯组包括第一发光灯组和第二发光灯组，所述驱动芯片包括第一数据选择管脚和第二数据选择管脚，所述分区通道走线包括第一分区通道走线和第二分区通道走线；
    所述第一发光灯组与所述第二发光灯组沿所述第一方向排列；
    所述第一数据选择管脚和所述第二数据选择管脚沿所述第一方向排列；
    其中，所述第一发光灯组与所述第一数据选择管脚通过所述第一分区通道走线连接，所述第二发光灯组通过所述第二分区通道走线与所述第二数据选择管脚连接。
  4. 根据权利要求3所述的显示面板，其中，所述发光灯组还包括第三发光灯组和第四发光灯组，所述驱动芯片还设置有第三数据选择管脚和第四数据选择管脚，所述分区通道走线还包括第三分区通道走线和第四分区通道走线；
    所述第一发光灯组、所述第二发光灯组、所述第三发光灯组以及第四发光灯组沿所述第一方向排列；
    所述第一数据选择管脚和所述第三数据选择管脚沿第二方向排成一列，所述第一数据选择管脚位于所述第三数据选择管脚靠近所述电源线的一侧；
    所述第二数据选择管脚和所述第四数据选择管脚沿第二方向排成另一列，所述第二数据选择管脚位于所述第四数据选择管脚靠近所述电源线的一侧；
    其中，一所述第三发光灯组与一所述第三数据选择管脚通过一所述第三分区通道走线连接，一所述第四发光灯组与一所述第四数据选择管脚通过一所述第四分区通道走线连接。
  5. 根据权利要求4所述的显示面板，其中，所述驱动芯片包括第一部分和与所述第一部分连接的第二部分，所述第一部分位于所述驱动芯片靠近所述电源线的端部，所述第一数据选择管脚、所述第二数据选择管脚、所述第三数据选择管脚以及所述第四数据选择管脚位于所述第一部分上；所述驱动芯片包括接地信号管脚，所述接地信号管脚与所述接地信号走线连接，所述接地信号管脚设置于所述第二部分上。
  6. 根据权利要求5所述的显示面板，其中，所述驱动芯片设置有两个电源信号管脚，所述两个电源信号管脚沿所述第一方向设置在所述第二部分上，所述显示面板包括驱动芯片电源走线，所述驱动芯片电源走线设置于相邻所述驱动芯片之间，用于连接所述驱动芯片的电源信号管脚。
  7. 根据权利要求6所述的显示面板，其中，所述驱动芯片设置有级传信号输入管脚以及级传信号输出管脚，所述级传信号输入管脚以及所述级传信号输出管脚沿所述第一方向设置在所述第二部分上，所述显示面板还包括驱动芯片信号走线，所述驱动芯片信号走线设置于相邻所述驱动芯片之间，用于连接相邻所述驱动芯片的所述级传信号输入管脚和所述级传信号输出管脚。
  8. 根据权利要求7所述的显示面板，其中，所述驱动芯片设置有至少一个数据信号管脚，所述数据信号管脚设置于所述第二部分上，所述显示面板包括数据传输走线，所述数据传输走线与所述数据信号管脚连接。
  9. 根据权利要求8所述的显示面板，其中，所述数据信号管脚的数量为一个，一个所述数据信号管脚与所述接地信号管脚沿所述第一方向设置，所述数据传输走线沿所述第一方向延伸，并位于所述数据信号管脚背离所述接地信号走线的一侧。
  10. 一种显示面板，其中，所述显示面板包括：
    电源线；
    接地信号走线，与所述电源线间隔设置；
    驱动芯片，设置在所述电源线与所述接地信号走线之间，并与所述接地信号走线连接；
    发光灯组，设置在所述接地信号走线与所述电源线之间，所述发光灯组的一端与所述电源线连接；以及
    分区通道走线，设置在所述电源线与所述接地信号走线之间，所述分区通道走线将所述发光灯组的另一端与所述驱动芯片连接；
    其中，所述电源线、所述分区通道走线以及所述接地信号走线同层设置。
  11. 根据权利要求10所述的显示面板，其中，所述发光灯组包括多个，多个所述发光灯组沿第一方向排列，所述分区通道走线包括多条，所述驱动芯片中设置有多个数据选择管脚，多个所述数据选择管脚沿所述第一方向和/或与所述第一方向相交的第二方向设置，每一所述数据选择管脚通过一所述分区通道走线与一所述发光灯组连接。
  12. 根据权利要求10所述的显示面板，其中，所述发光灯组包括第一发光灯组和第二发光灯组，所述驱动芯片包括第一数据选择管脚和第二数据选择管脚，所述分区通道走线包括第一分区通道走线和第二分区通道走线；
    所述第一发光灯组与所述第二发光灯组沿所述第一方向排列；
    所述第一数据选择管脚和所述第二数据选择管脚沿所述第一方向排列；
    其中，所述第一发光灯组与所述第一数据选择管脚通过所述第一分区通道走线连接，所述第二发光灯组通过所述第二分区通道走线与所述第二数据选择管脚连接。
  13. 根据权利要求12所述的显示面板，其中，所述发光灯组还包括第三发光灯组和第四发光灯组，所述驱动芯片还设置有第三数据选择管脚和第四数据选择管脚，所述分区通道走线还包括第三分区通道走线和第四分区通道走线；
    所述第一发光灯组、所述第二发光灯组、所述第三发光灯组以及第四发光灯组沿所述第一方向排列；
    所述第一数据选择管脚和所述第三数据选择管脚沿第二方向排成一列，所述第一数据选择管脚位于所述第三数据选择管脚靠近所述电源线的一侧；
    所述第二数据选择管脚和所述第四数据选择管脚沿第二方向排成另一列，所述第二数据选择管脚位于所述第四数据选择管脚靠近所述电源线的一侧；
    其中，一所述第三发光灯组与一所述第三数据选择管脚通过一所述第三分区通道走线连接，一所述第四发光灯组与一所述第四数据选择管脚通过一所述第四分区通道走线连接。
  14. 根据权利要求13所述的显示面板，其中，所述驱动芯片包括第一部分和与所述第一部分连接的第二部分，所述第一部分位于所述驱动芯片靠近所述电源线的端部，所述第一数据选择管脚、所述第二数据选择管脚、所述第三数据选择管脚以及所述第四数据选择管脚位于所述第一部分上；所述驱动芯片包括接地信号管脚，所述接地信号管脚与所述接地信号走线连接，所述接地信号管脚设置于所述第二部分上。
  15. 根据权利要求14所述的显示面板，其中，所述驱动芯片设置有两个电源信号管脚，所述两个电源信号管脚沿所述第一方向设置在所述第二部分上，所述显示面板包括驱动芯片电源走线，所述驱动芯片电源走线设置于相邻所述驱动芯片之间，用于连接所述驱动芯片的电源信号管脚。
  16. 根据权利要求15所述的显示面板，其中，所述驱动芯片设置有级传信号输入管脚以及级传信号输出管脚，所述级传信号输入管脚以及所述级传信号输出管脚沿所述第一方向设置在所述第二部分上，所述显示面板还包括驱动芯片信号走线，所述驱动芯片信号走线设置于相邻所述驱动芯片之间，用于连接相邻所述驱动芯片的所述级传信号输入管脚和所述级传信号输出管脚。
  17. 根据权利要求16所述的显示面板，其中，所述驱动芯片设置有至少一个数据信号管脚，所述数据信号管脚设置于所述第二部分上，所述显示面板包括数据传输走线，所述数据传输走线与所述数据信号管脚连接。
  18. 根据权利要求17所述的显示面板，其中，所述数据信号管脚的数量为一个，一个所述数据信号管脚与所述接地信号管脚沿所述第一方向设置，所述数据传输走线沿所述第一方向延伸，并位于所述数据信号管脚背离所述接地信号走线的一侧。
  19. 根据权利要求17所述的显示面板，其中，所述数据信号管脚的数量为二个，二个所述数据信号管脚沿所述第一方向设置。
  20. 根据权利要求19所述的显示面板，其中，所述接地信号管脚与所述级传信号输入管脚以及所述级传信号输出管脚位于同一列；或者
    所述接地信号管脚与所述数据信号管脚位于同一列；或者
    所述接地信号管脚与所述电源信号管脚位于同一列。
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