WO2023065745A1 - 驱动芯片、驱动芯片组件及显示装置 - Google Patents

驱动芯片、驱动芯片组件及显示装置 Download PDF

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Publication number
WO2023065745A1
WO2023065745A1 PCT/CN2022/107154 CN2022107154W WO2023065745A1 WO 2023065745 A1 WO2023065745 A1 WO 2023065745A1 CN 2022107154 W CN2022107154 W CN 2022107154W WO 2023065745 A1 WO2023065745 A1 WO 2023065745A1
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WIPO (PCT)
Prior art keywords
wire
pin
voltage
driver chip
chip
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Application number
PCT/CN2022/107154
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English (en)
French (fr)
Inventor
李锦乐
李治国
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惠州视维新技术有限公司
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Publication of WO2023065745A1 publication Critical patent/WO2023065745A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present application belongs to the display field, and in particular relates to a driving chip and a display device.
  • LED display Light Emitting Diode, light-emitting diode
  • LED display is a display that directly uses array LED devices (such as LED chips, LED lamp beads) as display pixels. It has high brightness and long life. Long and other advantages.
  • LED displays generally have a built-in driver chip to drive the LED device to emit light. In the case of a single chip with limited driving capability, in order to improve the resolution, the LED display often adopts partition drive, which divides the display area of the display into multiple drive partitions. , each driver partition is driven by one or several driver chips.
  • each driver chip is usually powered separately, and a chip power supply line is usually provided on the edge of the PCB board, and each driver chip is connected to the chip power supply line, which causes PCB layout.
  • a chip power supply line is usually provided on the edge of the PCB board, and each driver chip is connected to the chip power supply line, which causes PCB layout.
  • Embodiments of the present application provide a driver chip, a driver chip component, and a display device, which can reduce problems such as wire intersections.
  • the embodiment of the present application provides a driver chip, including:
  • the voltage input pin is electrically connected to the voltage output pin through a first wire, and the voltage of the voltage input pin is equal to the voltage of the voltage output pin.
  • the driver chip further includes a load, the load is arranged on the first substrate, a voltage output point is arranged on the first wire, and the voltage output point is configured to output a voltage to the load .
  • the first wires are disposed on the surface of the first substrate; or, the first wires are disposed inside the first substrate.
  • the driver chip also includes:
  • the second ground pin is used for grounding
  • the first ground pin is connected to the second ground pin through a second wire
  • the first wire and the second wire are insulated from each other.
  • a ground point is provided on the second wire, and when the driver chip includes the load, the ground point is connected to the load.
  • the driver chip also includes:
  • the data input pin is used for receiving the first control signal
  • the data output pin is used to output the second control signal
  • the load includes a data storage unit
  • the data input pin is electrically connected to the data output pin through the data storage unit;
  • the first control signal includes the address of the driving chip, and the driving chip obtains the corresponding control signal of its own level through addressing, and the first control signal is processed by the data registering unit and output as the Second control signal.
  • the driver chip further includes a constant current output pin
  • the first substrate further includes a first end portion and a second end portion oppositely arranged, and the first wire and the second wire are both arranged on Between the first end and the second end, the constant current output pin is provided on the first end and/or the second end.
  • the load further includes a constant current control unit and a voltage detection unit
  • the data storage unit is electrically connected to the constant current control unit through the voltage detection unit
  • the constant current output pin is connected to the
  • the constant current control unit is electrically connected
  • the constant current control unit controls the current at the constant current output pin to be in the first preset range according to the control signal of the current stage
  • the voltage detection unit is used to detect the The voltage value at the constant current output pin is used to generate a feedback signal to control the voltage of the light-emitting element to be within a second preset range.
  • the driver chip further includes a load, the load is arranged on the first substrate, a voltage output point is arranged on the first wire, and the voltage output point configured to output a voltage to the load.
  • the first wires are disposed on the surface of the first substrate; or, the first wires are disposed inside the first substrate.
  • the driver chip further includes: a first ground pin, used for grounding;
  • the second ground pin is used for grounding
  • the first ground pin is connected to the second ground pin through a second wire
  • the first wire and the second wire are insulated from each other.
  • the driver chip further includes:
  • the data input pin is used for receiving the first control signal
  • the data output pin is used to output the second control signal
  • the load includes a data storage unit
  • the data input pin is electrically connected to the data output pin through the data storage unit;
  • the first control signal includes the address of the driving chip, and the driving chip obtains the corresponding control signal of its own level through addressing, and the first control signal is processed by the data registering unit and output as the Second control signal.
  • the driver chip further includes a constant current output pin
  • the first substrate further includes a first end and a second end oppositely arranged, and the first wire and the second wire is arranged between the first end and the second end, and the constant current output pin is arranged on the first end and/or the second end.
  • the embodiment of the present application provides a driver chip assembly, including a plurality of driver chips, the plurality of driver chips are adjacently arranged along the first direction, and the voltage output pin of one driver chip is connected to the other adjacent The voltage input pins of the driver chip are relatively arranged and electrically connected through the fourth wire;
  • the driver chip includes:
  • the voltage input pin is electrically connected to the voltage output pin through a first wire, and the voltage of the voltage input pin is equal to the voltage of the voltage output pin.
  • the driver chip when the driver chip includes a first ground pin and a second ground pin, the voltage output pin of one driver chip and the voltage input pin of another adjacent driver chip pass through the first ground pin and the second ground pin.
  • the five wires are electrically connected, and the fourth wire is spaced apart from the fifth wire.
  • the driver chip when the driver chip includes a data input pin and a data output pin, the data output pin of one driver chip is connected to the data input pin of another adjacent driver chip through a sixth wire Electrically connected, the sixth wire is spaced from the fifth wire, and the sixth wire is spaced from the fourth wire.
  • the driver chip assembly further includes a light emitting element.
  • the driver chip includes a constant current output pin, a first end and a second end, the light emitting element is electrically connected to the constant current output pin. connected, the first end of one driver chip is opposite to the first end of another adjacent driver chip;
  • the light emitting elements connected to the first ends of each of the driving chips are connected to the same power supply line of the light emitting elements, and/or the light emitting elements connected to the second ends of each of the driving chips are connected to the same power supply line. Lighting element power supply line.
  • an embodiment of the present application provides a display device, and the display device further includes a plurality of driving chip assemblies, and the driving chip assemblies are adjacently arranged along the second direction, and one of the driving chip assemblies is connected to the The light-emitting element electrically connected to the first end and the light-emitting element electrically connected to the second end in another adjacent driver chip assembly are connected to the same power supply line of the light-emitting element;
  • the driver chip assembly includes a plurality of driver chips, the plurality of driver chips are adjacently arranged along the first direction, and the voltage output pin of one driver chip is connected to the voltage input pin of another adjacent driver chip. Relatively arranged and electrically connected through the fourth wire; the driver chip includes:
  • the voltage input pin is electrically connected to the voltage output pin through a first wire, and the voltage of the voltage input pin is equal to the voltage of the voltage output pin.
  • the driver chip when the driver chip includes a first ground pin and a second ground pin, the voltage output pin of one driver chip is connected to the other adjacent driver chip.
  • the voltage input pin of the chip is electrically connected through a fifth wire, and the fourth wire is spaced apart from the fifth wire.
  • the driver chip when the driver chip includes a data input pin and a data output pin, the data output pin of one driver chip is connected to the other adjacent driver chip.
  • the data input pin is electrically connected through a sixth wire, the sixth wire is spaced from the fifth wire, and the sixth wire is spaced from the fourth wire.
  • the driver chip includes a first substrate and a voltage input pin and a voltage output pin provided on the first substrate, the voltage input pin and the voltage output pin are electrically connected through a first wire, and the voltage input pin The voltage is equal to the voltage at the voltage output pin.
  • the voltage output pin of one driver chip is electrically connected to the voltage input pin of another adjacent driver chip. After one driver chip is connected to the power supply, the electric energy can be transmitted to another through the first wire
  • the voltage input pin of the driver chip is used to make the input voltages of two adjacent driver chips equal.
  • the driver chip provided by the embodiment of the present application is provided with a voltage input pin, a voltage output pin and a first wire, and the normal power supply of the chip can be ensured by using the pins for electrical connection. Reduce problems such as trace crossing in PCB layout.
  • FIG. 1 is a schematic diagram of a first structure of a display device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a display device in the prior art.
  • FIG. 3 is a schematic structural diagram of a first driving chip provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of driver chips used in cascade.
  • FIG. 5 is a schematic structural diagram of a second driving chip provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a third driving chip provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a fourth driving chip provided by an embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of the load in the embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of a display device in an embodiment of the present application.
  • the LED display screen has a built-in driver chip to drive the LED device to emit light.
  • the number of LED devices that can be driven by the LED driver chip is limited.
  • LED displays often use partition drivers. Partition driving technology is to divide the display area of the display screen into multiple sub-areas, each sub-area is driven by one or several driver chips, and then each driver chip is connected to control each driver chip. The cascading of driver chips can control more LED devices to emit light, thereby realizing large-screen display or high-resolution display.
  • FIG. 1 is a schematic diagram of a first structure of a display device provided by an embodiment of the present application.
  • the display device 100 includes a second substrate 1 and a driving chip assembly 2 , the second substrate 1 includes a third surface 13 and a fourth surface 15 opposite to each other, and the driving chip assembly 2 includes a light emitting element 22 and a driving chip 21 .
  • the partition driving LED display generally needs to use a double-sided printed circuit board as the substrate, and the light-emitting element 22 and the driver chip 21 are soldered to the two sides of the printed circuit board respectively, and the circuit connection is realized through the conductive holes on the circuit board. .
  • the third surface 13 can be used as a display surface, and the light emitting element 22 is disposed on the third surface 13 .
  • the driving chips 21 are disposed on the fourth surface 15 , each driving chip 21 is electrically connected to a plurality of light emitting elements 22 , and each driving chip 21 controls a certain display area.
  • the driving chips 21 in the driving chip assembly 2 are adjacently arranged in the first direction X, and the display device 100 usually includes a plurality of driving chip assemblies 2, and the plurality of driving chip assemblies 2 are adjacently arranged in the second direction Y, so that the second substrate An array of driving chips 21 is formed on the 1, and each driving chip 21 is electrically connected.
  • FIG. 2 is a schematic structural diagram of a display device in the prior art.
  • the LED driver chips 31 are arranged in an array on the PCB board 3 (equivalent to the second substrate 1 in this application), and each LED driver chip 31 is electrically connected to realize centralized control of the array of LED driver chips 31 .
  • a chip power supply line 33 is usually arranged on the edge of the PCB 3 , and the power supply pins 32 of each LED driver chip 31 are electrically connected to the chip power supply line 33 . It is understandable that when the number of LED driver chips 31 is large, this power supply method will cause problems such as crossing traces in PCB layout, which will lead to a decrease in the reliability of the PCB 3 and an increase in manufacturing costs.
  • FIG. 3 is a schematic structural diagram of a first driving chip provided in an embodiment of the present application.
  • the embodiment of the present application provides a driving chip 21 , and the driving chip 21 includes a first substrate 213 , a voltage input pin Vi and a voltage output pin Vo.
  • the voltage input pin Vi is disposed on the first substrate 213
  • the voltage output pin Vo is disposed on the first substrate 213 .
  • the voltage input pin Vi is electrically connected to the voltage output pin Vo through the first wire L1, and the voltage of the voltage input pin Vi is equal to the voltage of the voltage output pin Vo.
  • driver chips 21 are used in cascade, the voltage output pin Vo of one driver chip 21 is electrically connected to the voltage input pin Vi of another adjacent driver chip 21, so that the input voltage of two adjacent driver chips 21 equal.
  • the driver chip 21 provided by the embodiment of the present application is provided with a voltage input pin Vi, a voltage output pin Vo and a first wire L1.
  • the voltage output pin Vo of a driver chip 21 is adjacent
  • the voltage input pin Vi of another driver chip 21 is electrically connected. After one driver chip 21 is powered on, the electric energy can be transmitted to the voltage input pin Vi of the other driver chip 21 through the first wire L1, so that the input voltages of two adjacent driver chips 21 are equal.
  • the driver chip 21 provided in the embodiment of the present application is provided with a voltage input pin Vi, a voltage output pin Vo, and a first wire L1, and the electrical connection of the pins can ensure the normal power supply of each driver chip 21. Setting chip power supply lines on the edge can reduce problems such as crossing lines in PCB layout.
  • the first substrate 213 includes a first surface 2131 and a second surface 2132
  • the driver chip 21 further includes a load 217
  • the load 217 is arranged on the first surface 2131 of the first substrate 213, the first The second surface 2132 of the substrate 213 is used to connect with the fourth surface 15 of the second substrate 1 .
  • the load 217 needs to be connected to a power source to realize various control functions.
  • a voltage output point P may be set on the first wire L1, and the voltage output point P is configured to output voltage to the load 217 .
  • the load 217 can also be directly electrically connected to the voltage input pin Vi.
  • FIG. 4 is a schematic structural diagram of driving chips used in cascade.
  • two adjacent driving chips 21 such as the first chip 21 a and the second chip 21 b ) are taken as an example for explanation.
  • the voltage output pin Vo of the first chip 21a is electrically connected to the voltage input pin Vi of the second chip 21b.
  • the electric energy can be transmitted to another adjacent drive chip 21 through the first wire L1 and the voltage output pin Vo, although the voltage input pin Vi of the second chip 21b It is connected to the first driver chip 21, but actually the voltage input pin Vi of the second chip 21b is connected to the power supply.
  • This kind of arrangement makes the two adjacent driver chips 21 structurally "connected” together, and electrically, the two adjacent driver chips 21 are connected in parallel, which can realize the centralized power supply of the driver chip 21 array and avoid In order to arrange additional power supply lines at the edge of the second substrate 1 .
  • the display screen technology is gradually developing towards a more personalized and humanized direction.
  • the driver chips 21 "connected in series” are convenient for "centralized power supply", there are also some functions in the display screen that need to be controlled separately.
  • special area Exemplarily, it is necessary to set a news scroll bar at the edge of the display screen, or display the time at the corner of the display screen. These special areas are different from the main display area and need to be controlled separately.
  • the chips that control the special areas can be individually powered and controlled.
  • a power supply pin 32 can be additionally provided on the driver chip 21 for controlling a special area for separate power supply. In order to facilitate wiring, the voltage input pin Vi and the voltage output pin Vo of the driver chip 21 controlling the special area can still be electrically connected to the upper and lower driver chips 21 .
  • the arrangement position of the first wire L1 can affect many aspects such as the use, manufacture and wiring of the driving chip 21 .
  • the first wire L1 may be disposed on the first surface 2131 of the first substrate 213 .
  • the first wire L1 can also be disposed inside the first substrate 213 , for example, please refer to FIG. 5 , which is a schematic structural diagram of the second driving chip provided by the embodiment of the present application. Holes may be drilled inside the first substrate 213 , and then copper may be poured into the holes, so as to implement internal routing of the substrate. This arrangement does not occupy the surface area of the first substrate 213 , which can make the structure of the driving chip 21 compact and reduce the area of the driving chip 21 .
  • FIG. 6 is a schematic structural diagram of a third driving chip provided in an embodiment of the present application.
  • the driver chip 21 also includes a first ground pin G1 and a second ground pin G2 for grounding, the first ground pin G1 and the second ground pin G2 are connected through a second wire L2, and the load 217 can It is electrically connected with the first ground pin G1 or the second ground pin G2 to realize grounding.
  • a grounding point H may also be provided on the second wire L2, and the grounding point H is connected to the load 217, and the specific connection manner of the load 217 is not limited here.
  • the resistance of the first wire L1 between the voltage input pin Vi and the voltage output pin Vo needs to be as small as possible.
  • the voltage at the ground pin is not required to be equal.
  • elements such as resistors can be properly connected in series between the load 217 and the ground point H. Similar to the first wire L1 , the first ground pin G1 , the second ground pin G2 and the second wire L2 can also realize the structural “serial connection” of the driver chip 21 , thereby simplifying wiring.
  • the first wire L1 In order to prevent the second wire L2 from affecting the power supply of the first wire L1, the first wire L1 needs to be insulated from the second wire L2.
  • the first wire L1 and the second wire L2 may be arranged at intervals. It is also possible that the first wire L1 is disposed inside the first substrate 213 , and the second wire L2 is disposed on the first surface 2131 of the first substrate 213 .
  • ground point can also be set on the second substrate 1, and the ground pins (such as the first ground pin G1 and the second ground pin G2) on each driver chip 21 can be directly connected to the second substrate 1 through The ground point is electrically connected, such as welding the ground pin to the ground point on the second substrate 1 .
  • Each driving chip 21 corresponds to a grounding point on the second substrate 1 . This grounding method can reduce wiring connections between the driving chips 21 and reduce short-circuit and other bad phenomena.
  • the driving chip 21 may also include a data input pin Di and a data output pin Do.
  • the data input pin Di is used to receive the first control signal, and the data output pin Do is used to output the second control signal.
  • the load 217 includes a data register unit 2171 , and the data input pin Di is electrically connected to the data output pin Do through the data register unit 2171 .
  • the driving chip 21 in the embodiment of the present application may use an addressing technique to acquire the corresponding control signal of the driving chip 21 at this stage.
  • the load 217 may also include an address memory, and the address of each driver chip 21 has been obtained and stored in the address memory when the driver chip 21 is powered on.
  • the first control signal includes the address of the driver chip.
  • the data input pin Di transmits the first control signal to the data register unit 2171 after receiving the first control signal, and each driver chip 21 obtains the first control signal through the address.
  • the control signal of the current stage that matches its own address will light up the light-emitting element 22 it controls.
  • the data registering unit 2171 processes the first control signal into a second control signal, and outputs the second control signal through the data output pin Do.
  • the driver chip 21 can also use other methods to obtain the control signal at this level. For example, after the first chip 21a receives the first control signal, it decodes the first control signal, and uses the decoded signal to light up the light-emitting element. twenty two. At the same time, the first chip 21a re-encodes the decoded signal and sends it to the second chip 21b, and the second chip 21b repeats the decoding and encoding process of the first chip 21a. With this cascading method, the control signal can be transmitted to all the driving chips 21 in sequence. Each driving chip 21 repeats the same process to realize the cascaded lighting of the light emitting elements 22 .
  • the data input pin Di of a driver chip 21 can be connected with the data output pin Di of the driver chip 21 of the upper stage.
  • the pin Do is electrically connected, and the data output pin Do can be electrically connected to the data input pin Di of the driver chip 21 of the next stage.
  • the first control signal is output by the upper-level driver chip, and the second control signal output by the current-level driver chip will be transmitted to the lower-level driver chip.
  • the setting of the data input pin Di and the data output pin Do can also make the driver chip 21 "serially connected", which can simplify wiring and avoid problems such as crossing wiring as much as possible.
  • FIG. 7 is a schematic structural diagram of a fourth driving chip provided in an embodiment of the present application.
  • the first substrate 213 also includes a first end portion 2133 and a second end portion 2134 oppositely disposed, and the first wire L1 and the second wire L2 are both arranged on the first end portion 2133 and the second end portion 2133 . between the two ends 2134 .
  • the first wire L1 and the second wire L2 are disposed at the middle portion of the driving chip 21 .
  • the driver chip 21 may include a first edge 2135 and a second edge 2136 oppositely arranged, and the first voltage input pin Vi, the first ground pin G1 and the data input pin Di are all arranged on the first edge 2135 , the voltage output pin Vo, the second ground pin G2 and the data output pin Do are all disposed on the second edge 2136 .
  • setting pins on the edge can shorten the wiring between two adjacent driver chips 21, facilitate the connection of the two driver chips 21, reduce the material of connecting wires, and save the cost of raw materials.
  • the constant current output pin 215 is provided on the first end portion 2133 and/or the second end portion 2134 , and the constant current output pin 215 is electrically connected to the light emitting element 22 . It can be understood that the constant current output pins 215 are arranged at both ends of the driver chip 21, and the first wire L1 and the second wire L2 are arranged in the middle part of the driver chip 21. The lines are concise and tidy, and problems such as crossover jumpers of lines on the second substrate 1 are minimized.
  • each driver chip 21 the number of constant current output pins 215 is multiple.
  • each driver chip 21 is provided with four constant current output pins 215, of which two constant current output pins 215 is disposed on the first end 2133, and the other two constant current output pins 215 are disposed on the second end 2134, and the four constant current output pins 215 can be symmetrically disposed.
  • FIG. 8 is a schematic structural diagram of the load in the embodiment of the present application.
  • the load 217 also includes a constant current control unit 2173 and a voltage detection unit 2172, the data storage unit 2171 and the constant current control unit 2173 are electrically connected through the voltage detection unit 2172, and a constant current output lead
  • the pin 215 is electrically connected to the constant current control unit 2173, and the constant current control unit 2173 controls the current at the constant current output pin 215 to be within a first preset range according to the control signal of the current stage.
  • the voltage detection unit 2172 is used to detect the voltage value at the constant current output pin 215, the voltage value detected by the voltage detection unit 2172 is compared with the set value and error amplified, and used as the power supply
  • the feedback signal is used to control the voltage value of the light emitting element 22 to ensure that the voltage of the light emitting element 22 is within the second preset range, and the power supply supplies power to the light emitting element 22 through the light emitting element power supply line L7. It can be understood that the brightness of the light emitting element 22 can be controlled by controlling the voltage and current of the light emitting element 22 .
  • the load 217 can also include a counting unit 2174 and a clock oscillating unit 2175, the base unit is electrically connected to the voltage detection unit 2172, one end of the clock oscillating unit 2175 is electrically connected to the technical unit, and the other end of the clock oscillating unit 2175 is connected to the
  • the data registers are electrically connected, so as to realize timing control in the circuit.
  • FIG. 9 is another schematic structural diagram of a display device in an embodiment of the present application.
  • the plurality of driver chips 21 are adjacently arranged along the first direction X, and the voltage output pin Vo of one driver chip 21 is connected to the voltage input pin of another adjacent driver chip 21. Vi is oppositely arranged and electrically connected through the fourth wire L4.
  • the voltage output pin Vo of one driver chip 21 is electrically connected to the voltage input pin Vi of another adjacent driver chip 21 through a fifth wire L5, and the fourth wire L4 is connected to the fifth wire L5. interval setting.
  • the data output pin Do of one driver chip 21 is electrically connected to the data input pin Di of another adjacent driver chip 21 through a sixth wire L6.
  • the second edge 2136 of a driver chip 21 can be set opposite to the first edge 2135 of the adjacent next-level driver chip 21, so as to avoid as far as possible the interference between the fourth wire L4, the fifth wire L5 and the sixth wire L6. cross. That is, the sixth wire L6 is spaced from the fifth wire L5 , and the sixth wire L6 is spaced from the fourth wire L4 .
  • the first end 2133 of one driving chip 21 is opposite to the first end 2133 of another adjacent driving chip 21, and the first end 2133 of one driving chip 21 is The two end portions 2134 are opposite to the second end portion 2134 of another adjacent driving chip 21 .
  • the first end 2133 and the second end 2134 are provided with a constant current output pin 215 , and the constant current output pin 215 is electrically connected to the light emitting element 22 .
  • the light-emitting element 22 connected to the first end 2133 of each driving chip 21 is connected to the same light-emitting element power supply line L7, and/or the light-emitting element 22 connected to the second end 2134 of each driving chip 21
  • the light emitting element 22 is connected to the power supply line L7 of the same light emitting element.
  • the driving chip assemblies 2 are adjacently arranged along the second direction Y, and the light-emitting element 22 electrically connected to the first end 2133 in one of the driving chip assemblies 2 is connected to the other adjacent one.
  • the light emitting elements 22 in the driving chip assembly 2 that are electrically connected to the second end portion 2134 are connected to the same light emitting element power supply line L7. It can be understood that the junction of the light-emitting elements 22 is beneficial to reduce the crossing of wires on the second substrate 1 and the like.

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  • Physics & Mathematics (AREA)
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Abstract

一种驱动芯片（21）、驱动芯片组件（2）及显示装置（100），驱动芯片（21）包括第一基板（213）以及设置于第一基板（213）的电压输入引脚（Vi）和电压输出引脚（Vo），电压输入引脚（Vi）与电压输出引脚（Vo）通过第一导线（L1）电连接，电压输入引脚（Vi）的电压等于电压输出引脚（Vo）的电压。

Description

驱动芯片、驱动芯片组件及显示装置
本申请要求于2021年10月20日提交中国专利局、申请号为202122530247.2、发明名称为“驱动芯片、驱动芯片组件及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于显示领域，尤其涉及一种驱动芯片及显示装置。
 背景技术
LED显示屏（Light Emitting Diode，发光二极管）深受广大消费者的喜爱，LED显示屏是直接将阵列LED器件（如LED芯片、LED灯珠）作为显示像素的显示屏，其具有亮度高、寿命长等优点。LED显示屏一般内置有驱动芯片来驱动LED器件发光，在单个芯片驱动能力有限的情况下，为提高分辨率，LED显示屏常采用分区驱动，分区驱动即将显示屏的显示区分成多个驱动分区，每个驱动分区由一个或若干个驱动芯片进行驱动。
 技术问题
多个驱动芯片需要级联使用，相关技术中，通常对各驱动芯片单独供电，在PCB板的边缘通常设置有一芯片供电线，各驱动芯片均与该芯片供电线连接，这造成了PCB排版中存在走线交叉等问题，会导致PCB板的可靠性下降及制造成本上升。
 技术解决方案
本申请实施例提供一种驱动芯片、驱动芯片组件及显示装置，可以减少走线交叉等问题。
第一方面，本申请实施例提供一种驱动芯片，包括：
第一基板；
电压输入引脚，设置于所述第一基板；
电压输出引脚，设置于所述第一基板；
其中，所述电压输入引脚与所述电压输出引脚通过第一导线电连接，所述电压输入引脚的电压等于所述电压输出引脚的电压。
可选的，所述驱动芯片还包括负载，所述负载设置于所述第一基板上，所述第一导线上设置有电压输出点，所述电压输出点被配置为向所述负载输出电压。
可选的，所述第一导线设置于所述第一基板的表面；或者，所述第一导线设置于所述第一基板的内部。
可选的，所述驱动芯片还包括：
第一接地引脚，用于接地；
第二接地引脚，用于接地，所述第一接地引脚与所述第二接地引脚通过第二导线连接，所述第一导线与所述第二导线相互绝缘。
可选的，所述第二导线上设置有接地点，当所述驱动芯片包括所述负载时，所述接地点与所述负载连接。
可选的，所述驱动芯片还包括：
数据输入引脚，用于接收第一控制信号；
数据输出引脚，用于输出第二控制信号，所述负载包括数据寄存单元，所述数据输入引脚通过所述数据寄存单元与所述数据输出引脚电连接；
其中，所述第一控制信号包括所述驱动芯片的地址，所述驱动芯片通过寻址来获取对应的本级控制信号，所述第一控制信号经所述数据寄存单元处理后输出为所述第二控制信号。
可选的，所述驱动芯片还包括恒流输出引脚，所述第一基板还包括相对设置的第一端部和第二端部，所述第一导线和所述第二导线均设置于所述第一端部和所述第二端部之间，所述第一端部和/或所述第二端部上设置有所述恒流输出引脚。
可选的，所述负载还包括恒流控制单元和电压侦测单元，所述数据寄存单元与所述恒流控制单元通过所述电压侦测单元电连接，所述恒流输出引脚与所述恒流控制单元电连接，所述恒流控制单元根据所述本级控制信号控制所述恒流输出引脚处的电流处于第一预设范围，所述电压侦测单元用于侦测所述恒流输出引脚处的电压值，所述电压值用于生成反馈信号以控制发光元件的电压处于第二预设范围。
可选的，根据上述所述的驱动芯片组件，所述驱动芯片还包括负载，所述负载设置于所述第一基板上，所述第一导线上设置有电压输出点，所述电压输出点被配置为向所述负载输出电压。
可选的，根据上述所述的驱动芯片组件，所述第一导线设置于所述第一基板的表面；或者，所述第一导线设置于所述第一基板的内部。
可选的，根据上述所述的驱动芯片组件，所述驱动芯片还包括：第一接地引脚，用于接地；
第二接地引脚，用于接地，所述第一接地引脚与所述第二接地引脚通过第二导线连接，所述第一导线与所述第二导线相互绝缘。
可选的，根据上述所述的驱动芯片组件，所述驱动芯片还包括：
数据输入引脚，用于接收第一控制信号；
数据输出引脚，用于输出第二控制信号，所述负载包括数据寄存单元，所述数据输入引脚通过所述数据寄存单元与所述数据输出引脚电连接；
其中，所述第一控制信号包括所述驱动芯片的地址，所述驱动芯片通过寻址来获取对应的本级控制信号，所述第一控制信号经所述数据寄存单元处理后输出为所述第二控制信号。
可选的，根据上述所述的驱动芯片组件，所述驱动芯片还包括恒流输出引脚，所述第一基板还包括相对设置的第一端部和第二端部，所述第一导线和所述第二导线设置于所述第一端部和所述第二端部之间，所述第一端部和/或所述第二端部上设置有所述恒流输出引脚。
第二方面，本申请实施例提供一种驱动芯片组件，包括多个驱动芯片，所述多个驱动芯片沿第一方向相邻设置，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚相对设置且通过第四导线电连接；所述驱动芯片包括：
第一基板；
电压输入引脚，设置于所述第一基板；
电压输出引脚，设置于所述第一基板；
其中，所述电压输入引脚与所述电压输出引脚通过第一导线电连接，所述电压输入引脚的电压等于所述电压输出引脚的电压。
可选的，当所述驱动芯片包括第一接地引脚、第二接地引脚时，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚通过第五导线电连接，所述第四导线与所述第五导线间隔设置。
可选的，当所述驱动芯片包括数据输入引脚、数据输出引脚时，一所述驱动芯片的数据输出引脚与相邻的另一所述驱动芯片的数据输入引脚通过第六导线电连接，所述第六导线与所述第五导线间隔设置，所述第六导线与所述第四导线间隔设置。
可选的，所述驱动芯片组件还包括发光元件，当所述驱动芯片包括恒流输出引脚、第一端部以及第二端部时，所述发光元件与所述恒流输出引脚电连接，一所述驱动芯片的所述第一端部与相邻的另一所述驱动芯片的第一端部相对设置；
其中，连接于各所述驱动芯片的第一端部上的发光元件汇接与同一发光元件供电线，和/或连接于各所述驱动芯片的第二端部上的发光元件汇接与同一发光元件供电线。
第三方面，本申请实施例提供一种显示装置，所述显示装置还包括多个驱动芯片组件，所述驱动芯片组件沿第二方向相邻设置，一所述驱动芯片组件中的与所述第一端部电连接的发光元件与相邻的另一所述驱动芯片组件中的与所述第二端部电连接的发光元件汇接于同一发光元件供电线；
所述驱动芯片组件包括多个驱动芯片，所述多个驱动芯片沿第一方向相邻设置，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚相对设置且通过第四导线电连接；所述驱动芯片包括：
第一基板；
电压输入引脚，设置于所述第一基板；
电压输出引脚，设置于所述第一基板；
其中，所述电压输入引脚与所述电压输出引脚通过第一导线电连接，所述电压输入引脚的电压等于所述电压输出引脚的电压。
可选的，根据上述所述的显示装置，当所述驱动芯片包括第一接地引脚、第二接地引脚时，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚通过第五导线电连接，所述第四导线与所述第五导线间隔设置。
可选的，根据上述所述的显示装置，当所述驱动芯片包括数据输入引脚、数据输出引脚时，一所述驱动芯片的数据输出引脚与相邻的另一所述驱动芯片的数据输入引脚通过第六导线电连接，所述第六导线与所述第五导线间隔设置，所述第六导线与所述第四导线间隔设置。
 有益效果
本申请实施例中，驱动芯片包括第一基板以及设置于第一基板的电压输入引脚和电压输出引脚，电压输入引脚与电压输出引脚通过第一导线电连接，电压输入引脚的电压等于电压输出引脚的电压。在驱动芯片级联使用时，一驱动芯片的电压输出引脚与相邻的另一驱动芯片的电压输入引脚电连接，一驱动芯片接入电源后，电能可以通过第一导线传输到另一驱动芯片的电压输入引脚，以使得两个相邻的驱动芯片的输入电压相等。本申请实施例提供的驱动芯片设置有电压输入引脚、电压输出引脚以及第一导线，利用引脚进行电连接即可保证芯片正常供电，不需要在PCB板的边缘设置芯片供电线，能够减少PCB排版中走线交叉等问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其有益效果显而易见。
图1为本申请实施例提供的显示装置的第一种结构示意图。
图2为现有技术中显示装置的结构示意图。
图3为本申请实施例提供的第一种驱动芯片的结构示意图。
图4为驱动芯片级联使用时的结构示意图。
图5为本申请实施例提供的第二种驱动芯片的结构示意图。
图6为本申请实施例提供的第三种驱动芯片的结构示意图。
图7为本申请实施例提供的第四种驱动芯片的结构示意图。
图8为本申请实施例中负载的结构示意图。
图9为本申请实施例中的显示装置的另一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
相关技术中，LED显示屏内置有驱动芯片来驱动LED器件发光，但是，LED驱动芯片所能驱动的LED器件数量有限。为了实现大规模的应用或者提高分辨率，LED显示屏常采用分区驱动。分区驱动技术即将显示屏的显示区分成多个子区，每个子区由一个或若干个驱动芯片进行驱动，然后，将各驱动芯片连接起来，再对各驱动芯片进行控制。驱动芯片的级联能够控制更多的LED器件发光，从而实现大屏显示或高分辨率显示。
请参阅图1，图1为本申请实施例提供的显示装置的第一种结构示意图。显示装置100包括第二基板1以及驱动芯片组件2，第二基板1包括相对设置的第三表面13和第四表面15，驱动芯片组件2中包含发光元件22和驱动芯片21。为实现分区驱动，分区驱动LED显示屏一般需采用双面印刷电路板作为基板，将发光元件22和驱动芯片21分别焊接在印刷电路板的两个面并通过电路板上的导电孔实现电路连接。因此，第三表面13可以作为显示面，发光元件22设置于第三表面13。驱动芯片21则设置于第四表面15，每一驱动芯片21与多个发光元件22电连接，每一驱动芯片21控制一定的显示区域。驱动芯片组件2内的驱动芯片21以第一方向X相邻设置，显示装置100通常包括多个驱动芯片组件2，多个驱动芯片组件2沿第二方向Y相邻设置，以在第二基板1上形成驱动芯片21阵列，各驱动芯片21电连接。
请参阅图2，图2为现有技术中显示装置的结构示意图。相关技术中，分区驱动时，LED驱动芯片31在PCB板3（相当于本申请中的第二基板1）呈阵列排布，各LED驱动芯片31电连接以实现LED驱动芯片31阵列的集中控制。LED驱动芯片31上通常仅设置有一个电源引脚32，需要对各LED驱动芯片31单独供电。在PCB板3的边缘通常设置有一芯片供电线33，各LED驱动芯片31的电源引脚32均与该芯片供电线33电连接。可以理解的是，当LED驱动芯片31数量较多时，该种供电方式会造成PCB排版中存走线交叉等问题，这会导致PCB板3的可靠性下降及制造成本上升。
请参阅图3，图3为本申请实施例提供的第一种驱动芯片的结构示意图。本申请实施例提供一种驱动芯片21，驱动芯片21包括第一基板213、电压输入引脚Vi以及电压输出引脚Vo。其中，电压输入引脚Vi设置于所述第一基板213，电压输出引脚Vo设置于所述第一基板213。电压输入引脚Vi与所述电压输出引脚Vo通过第一导线L1电连接，所述电压输入引脚Vi的电压等于所述电压输出引脚Vo的电压。在驱动芯片21级联使用时，一驱动芯片21的电压输出引脚Vo与相邻的另一驱动芯片21的电压输入引脚Vi电连接，以使得两个相邻的驱动芯片21的输入电压相等。
本申请实施例提供的驱动芯片21设置有电压输入引脚Vi、电压输出引脚Vo以及第一导线L1，在驱动芯片21级联使用时，一驱动芯片21的电压输出引脚Vo与相邻的另一驱动芯片21的电压输入引脚Vi电连接。一驱动芯片21接入电源后，电能可以通过第一导线L1传输到另一驱动芯片21的电压输入引脚Vi，以使得两个相邻的驱动芯片21的输入电压相等。本申请实施例提供的驱动芯片21设置有电压输入引脚Vi、电压输出引脚Vo以及第一导线L1，利用引脚进行电连接即可保证各驱动芯片21正常供电，不需要在PCB板的边缘设置芯片供电线，能够减少PCB排版中走线交叉等问题。
其中，所述第一基板213包括第一表面2131和第二表面2132，所述驱动芯片21还包括负载217，所述负载217设置于所述第一基板213的第一表面2131上，第一基板213的第二表面2132用于与第二基板1的第四表面15连接。可以理解的是，负载217需要接入电源以实现各种控制功能。示例性的，可以在所述第一导线L1上设置电压输出点P，所述电压输出点P被配置为向所述负载217输出电压。当然，负载217也可以直接与电压输入引脚Vi电连接。
可以理解的是，电压输入引脚Vi与电压输出引脚Vo通过第一导线L1直接连接，请参阅图4，图4为驱动芯片级联使用时的结构示意图。下面以相邻的两个驱动芯片21（如第一芯片21a和第二芯片21b）为例讲解说明。当驱动芯片21级联时，第一芯片21a的电压输出引脚Vo与第二芯片21b的电压输入引脚Vi电连接。第一芯片21a的电压输入引脚Vi接入电源后，电能能够通过第一导线L1和电压输出引脚Vo向相邻的另一驱动芯片21传输，第二芯片21b的电压输入引脚Vi虽然与第一驱动芯片21连接，但实际上第二芯片21b的电压输入引脚Vi接入了电源。该种设置使得相邻的两个驱动芯片21在结构上“串接”在一起，在电学上，相邻的两个驱动芯片21并联，能够在实现驱动芯片21阵列进行集中供电的同时，避免了在第二基板1的边缘设置额外的供电线。
需要说明的是，显示屏技术也逐渐朝着更加个性化、人性化的方向发展，“串接”在一起的驱动芯片21虽然方便进行“集中供电”，但是显示屏中也存在需要单独控制的特殊区域。示例性的，在显示屏的边缘需要设置新闻滚动条，或者在显示屏的角落显示时间等。这些特殊区域不同于主要的显示区域，需要对特殊区域进行单独控制，相应的，可以对控制特殊区域的芯片进行单独供电和控制。用于控制特殊区域的驱动芯片21上能够另外设置一个电源引脚32用于单独供电。为了便于走线，控制特殊区域的驱动芯片21的电压输入引脚Vi和电压输出引脚Vo仍然可以与上下级的驱动芯片21进行电连接。
可以理解的是，第一导线L1的设置位置能影响到驱动芯片21的使用、制造以及走线等诸多方面。为了便于制造加工，所述第一导线L1可以设置于所述第一基板213的第一表面2131。当然，所述第一导线L1也可以设置于所述第一基板213的内部，示例性的，请参阅图5，图5为本申请实施例提供的第二种驱动芯片的结构示意图。可以在第一基板213内部打孔，然后向孔中注铜，从而实现基板的内部走线。该种设置不占用第一基板213的表面积，能够使得驱动芯片21的结构紧凑，减小驱动芯片21面积。
请参阅图6，图6为本申请实施例提供的第三种驱动芯片的结构示意图。驱动芯片21还包括用于接地的第一接地引脚G1和第二接地引脚G2，所述第一接地引脚G1与所述第二接地引脚G2通过第二导线L2连接，负载217可以与第一接地引脚G1或者第二接地引脚G2电连接从而实现接地。当然，所述第二导线L2上也可以设置有接地点H，所述接地点H与所述负载217连接，此处对负载217接地的具体连接方式不做限制。可以理解的是，为了保证电压输入引脚Vi与电压输出引脚Vo处的电压相等，电压输入引脚Vi与电压输出引脚Vo之间的第一导线L1的电阻需要尽量小。在实现负载217接地时则不要求接地引脚处的电压相等，可以根据驱动芯片21上负载217实际的情况，适当地在负载217与接地点H之间串接电阻等元件。与第一导线L1类似的是，第一接地引脚G1、第二接地引脚G2以及第二导线L2也能实现驱动芯片21在结构上的“串接”，起到简化走线的作用。为了避免第二导线L2对第一导线L1的供电产生影响，第一导线L1需要与所述第二导线L2绝缘设置。示例性的，第一导线L1可以与第二导线L2间隔设置。也可以是第一导线L1设置在第一基板213内部，第二导线L2设置在第一基板213的第一表面2131。
需要说明的是，接地点也可以设置在第二基板1上，各驱动芯片21上的接地引脚（如第一接地引脚G1和第二接地引脚G2）可以直接与第二基板1通过接地点电连接，如将接地引脚与第二基板1上的接地点焊接。每一驱动芯片21均对应第二基板1上的一接地点，该种接地方式可以减少驱动芯片21之间的走线连接，减少短路等不良现象。
所述驱动芯片21还可以包括数据输入引脚Di和数据输出引脚Do。数据输入引脚Di用于接收第一控制信号，数据输出引脚Do用于输出第二控制信号。所述负载217包括数据寄存单元2171，所述数据输入引脚Di通过所述数据寄存单元2171与所述数据输出引脚Do电连接。
需要说明的是，本申请实施例中的驱动芯片21可以采用寻址技术获取该驱动芯片21相对应的本级控制信号。示例性的，负载217还可以包括地址存储器，各驱动芯片21的地址在驱动芯片21上电时已经取得并存储于地址储存器中。所述第一控制信号包括所述驱动芯片的地址，使用时，数据输入引脚Di接收第一控制信号后将第一控制信号传递至数据寄存单元2171，每个驱动芯片21通过地址来获取第一控制信号中符合自己地址的本级控制信号，从而将其所控制的发光元件22点亮。获取了本级控制信号后，数据寄存单元2171将第一控制信号处理为第二控制信号，并通过数据输出引脚Do将第二控制信号输出。
当然，驱动芯片21也可以采用其他方式获取本级控制信号，示例性的，第一芯片21a接收到第一控制信号后，将第一控制信号进行解码，并利用解码后的信号点亮发光元件22。同时，第一芯片21a将解码后的信号重新编码后发送到第二芯片21b，第二芯片21b重复第一芯片21a的解码和编码过程。采用该种级联方式，控制信号能够顺次传输至所有的驱动芯片21。各驱动芯片21均重复同样的处理过程，实现发光元件22的级联点亮。
为了实现对诸多“串接”在一起的驱动芯片21进行集中控制，在驱动芯片21的级联使用时，一驱动芯片21的数据输入引脚Di可以与上一级的驱动芯片21的数据输出引脚Do电连接，数据输出引脚Do可以与下一级的驱动芯片21的数据输入引脚Di电连接。可以理解的是，对于本级驱动芯片而言，第一控制信号由上级驱动芯片输出，本级驱动芯片输出的第二控制信号将传输至下级驱动芯片。在结构上，数据输入引脚Di和数据输出引脚Do的设置也能使得驱动芯片21“串接”，起到简化走线的作用，尽量避免走线交叉等问题。
请参阅图7，图7为本申请实施例提供的第四种驱动芯片的结构示意图。所述第一基板213还包括相对设置的第一端部2133和第二端部2134，所述第一导线L1和所述第二导线L2均设置于所述第一端部2133和所述第二端部2134之间。第一导线L1和第二导线L2设置于驱动芯片21的中间部分。
需要说明的是，驱动芯片21可以包括相对设置的第一边缘2135和第二边缘2136，第一电压输入引脚Vi、第一接地引脚G1以及数据输入引脚Di均设置于第一边缘2135，电压输出引脚Vo、第二接地引脚G2以及数据输出引脚Do均设置于第二边缘2136。在驱动芯片21级联时，边缘设置引脚可以缩短相邻两个驱动芯片21之间的走线，方便两个驱动芯片21的连接，减少连接导线的材料，节省原料成本。
第一端部2133和/或所述第二端部2134上设置有所述恒流输出引脚215，恒流输出引脚215与发光元件22电连接。可以理解的是，恒流输出引脚215设置于驱动芯片21的两端，第一导线L1、第二导线L2设置于驱动芯片21的中间部分，该种设置能够使得第二基板1上的走线简洁整齐，尽量减少第二基板1上走线的交叉跳线等问题。
其中，每一驱动芯片21中，恒流输出引脚215的数量为多个，示例性的，每一驱动芯片21上设置有四个恒流输出引脚215，其中两个恒流输出引脚215设置于第一端部2133，另外两个恒流输出引脚215设置于第二端部2134，四个恒流输出引脚215可以对称设置。
请参阅图8，图8为本申请实施例中负载的结构示意图。所述负载217还包括恒流控制单元2173和电压侦测单元2172，所述数据寄存单元2171与所述恒流控制单元2173通过所述电压侦测单元2172电连接，一所述恒流输出引脚215与所述恒流控制单元2173电连接，所述恒流控制单元2173根据所述本级控制信号控制所述恒流输出引脚215处的电流处于第一预设范围。所述电压侦测单元2172用于侦测所述恒流输出引脚215处的电压值，电压侦测单元2172侦测到的电压值与设定值比较并作误差放大后，作为供电电源的反馈信号用于控制发光元件22的电压值，以保证发光元件22的电压处于第二预设范围内，供电电源通过发光元件供电线L7向发光元件22供电。可以理解的是，通过对发光元件22的电压和电流的控制，能够控制发光元件22的亮度。
需要说明的是，负载217还可以包括计数单元2174和时钟震荡单元2175，基数单元与电压侦测单元2172电连接，时钟震荡单元2175的一端与技术单元电连接，时钟震荡单元2175的另一端与数据寄存器电连接，从而实现电路中时序的控制。数据寄存单元2171与恒流控制单元2173之间还可以具有其他功能的单元，比如补偿单元、矫正单元等，以使得对显示画面的控制更加精准。
请参阅图9，图9为本申请实施例中的显示装置的另一种结构示意图。驱动芯片组件2中，所述多个驱动芯片21沿第一方向X相邻设置，一所述驱动芯片21的电压输出引脚Vo与相邻的另一所述驱动芯片21的电压输入引脚Vi相对设置且通过第四导线L4电连接。一所述驱动芯片21的电压输出引脚Vo与相邻的另一所述驱动芯片21的电压输入引脚Vi通过第五导线L5电连接，所述第四导线L4与所述第五导线L5间隔设置。一所述驱动芯片21的数据输出引脚Do与相邻的另一所述驱动芯片21的数据输入引脚Di通过第六导线L6电连接。
其中，一驱动芯片21的第二边缘2136可以与相邻的下一级驱动芯片21的第一边缘2135相对设置，从而尽量避免第四导线L4、第五导线L5以及第六导线L6之间的交叉。即所述第六导线L6与所述第五导线L5间隔设置，所述第六导线L6与所述第四导线L4间隔设置。
驱动芯片组件2中，一所述驱动芯片21的所述第一端部2133与相邻的另一所述驱动芯片21的第一端部2133相对设置，一所述驱动芯片21的所述第二端部2134与相邻的另一所述驱动芯片21的第二端部2134相对设置。第一端部2133、第二端部2134上设置有恒流输出引脚215，恒流输出引脚215与发光元件22电连接。其中，连接于各所述驱动芯片21的第一端部2133上的发光元件22汇接与同一发光元件供电线L7，和/或连接于各所述驱动芯片21的第二端部2134上的发光元件22汇接与同一发光元件供电线L7。在显示装置100中，所述驱动芯片组件2沿第二方向Y相邻设置，一所述驱动芯片组件2中的与所述第一端部2133电连接的发光元件22与相邻的另一所述驱动芯片组件2中的与所述第二端部2134电连接的发光元件22汇接于同一发光元件供电线L7。可以理解的是，该种发光元件22的汇接有利于减少第二基板1上的走线交叉等状况。
以上对本申请实施例所提供的驱动芯片、驱动芯片组件以及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种驱动芯片，其中，包括：
    第一基板；
    电压输入引脚，设置于所述第一基板；
    电压输出引脚，设置于所述第一基板；
    其中，所述电压输入引脚与所述电压输出引脚通过第一导线电连接，所述电压输入引脚的电压等于所述电压输出引脚的电压。
  2. 根据权利要求1所述驱动芯片，其中，所述驱动芯片还包括负载，所述负载设置于所述第一基板上，所述第一导线上设置有电压输出点，所述电压输出点被配置为向所述负载输出电压。
  3. 根据权利要求1或2所述驱动芯片，其中，所述第一导线设置于所述第一基板的表面；或者，所述第一导线设置于所述第一基板的内部。
  4. 根据权利要求1所述的驱动芯片，其中，所述驱动芯片还包括：
    第一接地引脚，用于接地；
    第二接地引脚，用于接地，所述第一接地引脚与所述第二接地引脚通过第二导线连接，所述第一导线与所述第二导线相互绝缘。
  5. 根据权利要求4所述的驱动芯片，其中，所述第二导线上设置有接地点，当所述驱动芯片包括所述负载时，所述接地点与所述负载连接。
  6. 根据权利要求4所述的驱动芯片，其中，所述驱动芯片还包括：
    数据输入引脚，用于接收第一控制信号；
    数据输出引脚，用于输出第二控制信号，所述负载包括数据寄存单元，所述数据输入引脚通过所述数据寄存单元与所述数据输出引脚电连接；
    其中，所述第一控制信号包括所述驱动芯片的地址，所述驱动芯片通过寻址来获取对应的本级控制信号，所述第一控制信号经所述数据寄存单元处理后输出为所述第二控制信号。
  7. 根据权利要求6所述的驱动芯片，其中，所述驱动芯片还包括恒流输出引脚，所述第一基板还包括相对设置的第一端部和第二端部，所述第一导线和所述第二导线设置于所述第一端部和所述第二端部之间，所述第一端部和/或所述第二端部上设置有所述恒流输出引脚。
  8. 根据权利要求7所述的驱动芯片，其中，所述负载还包括恒流控制单元和电压侦测单元，所述数据寄存单元与所述恒流控制单元通过所述电压侦测单元电连接，所述恒流输出引脚与所述恒流控制单元电连接，所述恒流控制单元根据所述本级控制信号控制所述恒流输出引脚处的电流处于第一预设范围，所述电压侦测单元用于侦测所述恒流输出引脚处的电压值，所述电压值用于生成反馈信号以控制发光元件的电压处于第二预设范围。
  9. 一种驱动芯片组件，包括多个驱动芯片，所述多个驱动芯片沿第一方向相邻设置，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚相对设置且通过第四导线电连接；所述驱动芯片包括：
    第一基板；
    电压输入引脚，设置于所述第一基板；
    电压输出引脚，设置于所述第一基板；
    其中，所述电压输入引脚与所述电压输出引脚通过第一导线电连接，所述电压输入引脚的电压等于所述电压输出引脚的电压。
  10. 根据权利要求9所述的驱动芯片组件，其中，当所述驱动芯片包括第一接地引脚、第二接地引脚时，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚通过第五导线电连接，所述第四导线与所述第五导线间隔设置。
  11. 根据权利要求10所述的驱动芯片组件，其中，当所述驱动芯片包括数据输入引脚、数据输出引脚时，一所述驱动芯片的数据输出引脚与相邻的另一所述驱动芯片的数据输入引脚通过第六导线电连接，所述第六导线与所述第五导线间隔设置，所述第六导线与所述第四导线间隔设置。
  12. 根据权利要求11所述的驱动芯片组件，其中，所述驱动芯片组件还包括发光元件，当所述驱动芯片包括恒流输出引脚、第一端部以及第二端部时，所述发光元件与所述恒流输出引脚电连接，一所述驱动芯片的所述第一端部与相邻的另一所述驱动芯片的第一端部相对设置；
    其中，连接于各所述驱动芯片的第一端部上的发光元件汇接与同一发光元件供电线，和/或连接于各所述驱动芯片的第二端部上的发光元件汇接与同一发光元件供电线。
  13. 根据权利要求9所述的驱动芯片组件，其中，所述驱动芯片还包括负载，所述负载设置于所述第一基板上，所述第一导线上设置有电压输出点，所述电压输出点被配置为向所述负载输出电压。
  14. 根据权利要求9所述的驱动芯片组件，其中，所述第一导线设置于所述第一基板的表面；或者，所述第一导线设置于所述第一基板的内部。
  15. 根据权利要求9所述的驱动芯片组件，其中，所述驱动芯片还包括：第一接地引脚，用于接地；
    第二接地引脚，用于接地，所述第一接地引脚与所述第二接地引脚通过第二导线连接，所述第一导线与所述第二导线相互绝缘。
  16. 根据权利要求15所述的驱动芯片组件，其中，所述驱动芯片还包括：
    数据输入引脚，用于接收第一控制信号；
    数据输出引脚，用于输出第二控制信号，所述负载包括数据寄存单元，所述数据输入引脚通过所述数据寄存单元与所述数据输出引脚电连接；
    其中，所述第一控制信号包括所述驱动芯片的地址，所述驱动芯片通过寻址来获取对应的本级控制信号，所述第一控制信号经所述数据寄存单元处理后输出为所述第二控制信号。
  17. 根据权利要求16所述的驱动芯片组件，其中，所述驱动芯片还包括恒流输出引脚，所述第一基板还包括相对设置的第一端部和第二端部，所述第一导线和所述第二导线设置于所述第一端部和所述第二端部之间，所述第一端部和/或所述第二端部上设置有所述恒流输出引脚。
  18. 一种显示装置，所述显示装置还包括多个驱动芯片组件，所述驱动芯片组件沿第二方向相邻设置，一所述驱动芯片组件中的与所述第一端部电连接的发光元件与相邻的另一所述驱动芯片组件中的与所述第二端部电连接的发光元件汇接于同一发光元件供电线；
    所述驱动芯片组件包括多个驱动芯片，所述多个驱动芯片沿第一方向相邻设置，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚相对设置且通过第四导线电连接；所述驱动芯片包括：
    第一基板；
    电压输入引脚，设置于所述第一基板；
    电压输出引脚，设置于所述第一基板；
    其中，所述电压输入引脚与所述电压输出引脚通过第一导线电连接，所述电压输入引脚的电压等于所述电压输出引脚的电压。
  19. 根据权利要求18所述的显示装置，其中，当所述驱动芯片包括第一接地引脚、第二接地引脚时，一所述驱动芯片的电压输出引脚与相邻的另一所述驱动芯片的电压输入引脚通过第五导线电连接，所述第四导线与所述第五导线间隔设置。
  20. 根据权利要求19所述的显示装置，其中，当所述驱动芯片包括数据输入引脚、数据输出引脚时，一所述驱动芯片的数据输出引脚与相邻的另一所述驱动芯片的数据输入引脚通过第六导线电连接，所述第六导线与所述第五导线间隔设置，所述第六导线与所述第四导线间隔设置。
PCT/CN2022/107154 2021-10-20 2022-07-21 驱动芯片、驱动芯片组件及显示装置 WO2023065745A1 (zh)

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