WO2023028938A1 - 一种布线基板、显示基板和显示装置 - Google Patents

一种布线基板、显示基板和显示装置 Download PDF

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Publication number
WO2023028938A1
WO2023028938A1 PCT/CN2021/116166 CN2021116166W WO2023028938A1 WO 2023028938 A1 WO2023028938 A1 WO 2023028938A1 CN 2021116166 W CN2021116166 W CN 2021116166W WO 2023028938 A1 WO2023028938 A1 WO 2023028938A1
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WIPO (PCT)
Prior art keywords
pad
pads
power supply
group
ground
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Application number
PCT/CN2021/116166
Other languages
English (en)
French (fr)
Inventor
王杰
许邹明
田�健
刘纯建
吴信涛
雷杰
张建英
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112021008165.9T priority Critical patent/DE112021008165T5/de
Priority to US17/785,522 priority patent/US20240194842A1/en
Priority to PCT/CN2021/116166 priority patent/WO2023028938A1/zh
Priority to CN202180002413.1A priority patent/CN116325152A/zh
Priority to TW111133451A priority patent/TWI839835B/zh
Publication of WO2023028938A1 publication Critical patent/WO2023028938A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular to a wiring substrate, a display substrate and a display device.
  • Micro light-emitting diode (Mini LED) technology is approaching maturity.
  • major panel manufacturers are developing their own glass-based Mini LED display and backlight products. Since the active driving efficiency is higher, it can drive a larger area, and can achieve better brightness uniformity and contrast, so it has become the preferred driving circuit solution in large-size Mini LED backlight products.
  • the present disclosure provides a wiring substrate, a display substrate and a display device.
  • the wiring substrate includes:
  • a plurality of control regions are located on one side of the base substrate, each control region of the plurality of control regions extends along a first direction, and the plurality of control regions are arranged in sequence along a second direction , any one of the multiple control areas includes:
  • a plurality of drive circuit pad groups arranged in sequence along the first direction
  • a plurality of functional element pad groups each of the functional element pad groups is electrically connected to the drive circuit pad group;
  • a first connection line configured to cascade two adjacent drive circuit pad groups in the first direction
  • the orthographic projection of the first connection line on the base substrate and the orthographic projection of the signal line on the base substrate do not overlap each other.
  • the signal line includes a ground signal line and a power supply signal line; the ground signal line and the power supply signal line are respectively located on both sides of the drive circuit pad group;
  • the drive circuit pad group includes: a ground pad, and a power supply pad; the ground pad is located on a side of the power supply pad close to the ground signal line, and the ground pad is connected to the ground signal line Electrically connected, the power supply pad is electrically connected to the power supply signal line.
  • the wiring substrate has a bonding area;
  • the driving circuit pad group further includes: an input pad, and an output pad; the output pad is connected to the driving circuit pad group The center is located close to the pad group of the functional element.
  • the input pad, the output pad, the ground pad, the power supply pad are arranged differently.
  • the plurality of control areas include a first control area and a second control area adjacent in the second direction; Starting from a side close to the binding area, the pad groups are sequentially cascaded along the first direction; a plurality of drive circuit pad groups in the second control area start from a side away from the binding area, cascading in sequence along the first direction;
  • the drive circuit pad group farthest from the binding area in the first control area is cascaded with the drive circuit pad group farthest from the binding area in the second control area;
  • the output pads and the input pads are located in different rows; in the group of drive circuit pads in the second control area, the output The pads are located on the same row as the input pads.
  • the output pad is located in the same row as the power supply pad, and the output pad is connected to the ground pad. Disks are located in the same column;
  • the output pads are located in the same row as the input pads, and the output pads are located in the same column as the ground pads.
  • the output pad and the ground pad are located in the same row, and the output pad and the power supply pad Disks are located in the same column;
  • the output pads are located in the same row as the ground pads, and the output pads are located in the same column as the ground pads.
  • the first connection line includes: a first sub-connection part, and a second sub-connection part;
  • the orthographic projection of the first sub-connection part on the base substrate overlaps with the orthographic projection of the driving circuit pad group on the base substrate, and one end of the first sub-connection part is connected to the output pad The other end is electrically connected to the second sub-connection part; the other end of the second sub-connection part is electrically connected to the input pad of the driving circuit pad group at the next stage.
  • the main body direction of the first sub-connection part extends along the first direction
  • the orthographic projection of the first sub-connection part on the base substrate is located on the ground pad At the gap between the orthographic projection of the base substrate and the orthographic projection of the power supply pad on the substrate substrate.
  • the width of the first sub-connection portion in the second direction is one-fifth to half of the minimum distance between the ground pad and the power supply pad. one.
  • the minimum distance between the ground pad of the second control area and the power supply pad is greater than the distance between the ground pad of the first control area and the input pad. Minimum spacing between pads.
  • the wiring substrate includes: a second connection line; the drive circuit pad group farthest from the binding area in the first control area, and the second control area The driving circuit pad group farthest from the bonding area is cascaded through the second connecting wire.
  • the second control area includes the first drive circuit pad group farthest from the binding area, and the first functional element pad group farthest from the binding area;
  • the second connection line extends along the second direction and is located in a gap between the first drive circuit pad group and the first functional element pad group;
  • the second control area further includes: an output connection line electrically connecting the drive circuit pad group and the functional element pad group, and a bridge part of a different layer from the second connection line;
  • the output connection line includes: a first sub-output connection line and a second sub-output connection line extending along the first direction on the same layer as the second connection line; one end of the first output connection line is connected to The output pads of the first drive circuit pad group are electrically connected, one end of the second sub-output connection line is electrically connected to the first functional element pad group, and the first sub-output connection line The other end is electrically connected to the other end of the second sub-output connection line through the bridging portion.
  • the second control area includes the first drive circuit pad group farthest from the binding area, and the first functional element pad group farthest from the binding area;
  • the second connection line extends along the second direction and is located on a side of the first functional component pad group away from the first driving circuit pad group.
  • the arrangement of the input pads, the output pads, the ground pads, and the power supply pads in each of the drive circuit pad groups in the first control area is mirror-symmetrical to the arrangement of the input pads, the output pads, the ground pads, and the power supply pads in each of the driving circuit pad groups in the second control area.
  • the plurality of control regions include a third control region and a fourth control region adjacent in the second direction; wherein, in the third control region, a plurality of drive circuit pad groups Starting from the side close to the binding area, cascade sequentially along the first direction; in the fourth control region, starting from the side close to the binding area, a plurality of drive circuit pad groups along the The first direction is sequentially cascaded;
  • the power supply signal line connected to the third control area and the power supply signal line connected to the fourth control area are located between the ground signal line connected to the third control area and the fourth control area. area connected within the gap between the ground signal lines.
  • the third control area and the fourth control area are connected to the same power supply signal line.
  • the third control area and the fourth control area are arranged in mirror image symmetry as a whole.
  • the output pad is located in the same row as the power supply pad, and the output pad is connected to the ground pad. Disks are in the same column.
  • the wiring substrate further includes a power line located on the side of the functional element pad group away from the power supply signal line, and is electrically connected to the functional element pad group in the control area. on the same power cord as described.
  • the functional component pad group includes a plurality of sub-pad groups connected in series in sequence.
  • An embodiment of the present disclosure further provides a display substrate, which includes the wiring substrate provided in the embodiment of the present disclosure, and the functional element pad group includes a plurality of sub-pad groups connected in series in sequence;
  • the display substrate further includes a driving circuit that is bonded to the drive circuit pad group, and a light emitting element that is bonded to the element pad group.
  • the implementation of the present disclosure further provides a display device, which includes the display substrate as provided in the embodiment of the present disclosure.
  • FIG. 1A is one of the schematic top views of a wiring substrate provided by an embodiment of the present disclosure
  • FIG. 1B is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the left control area 2 in FIG. 1A;
  • FIG. 1C is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the right control area 2 in FIG. 1A;
  • Fig. 1D is an enlarged schematic diagram of the dotted line box X1 in Fig. 1A;
  • FIG. 1E is an enlarged schematic diagram of a dotted line box X2 in FIG. 1A;
  • FIG. 2A is the second schematic top view of a wiring substrate provided by an embodiment of the present disclosure
  • FIG. 2B is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the left control area 2 in FIG. 2A;
  • FIG. 2C is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the right control area 2 in FIG. 2A;
  • FIG. 2D is an enlarged schematic diagram of a dotted line box X3 in FIG. 2A;
  • FIG. 2E is an enlarged schematic diagram of a dotted line box X4 in FIG. 2A;
  • FIG. 3A is an enlarged layout at the dotted line circle B1 in FIG. 2D;
  • Fig. 3B is an enlarged layout at the dotted line circle B2 in Fig. 2E;
  • FIG. 3C is an enlarged schematic diagram of the dotted line coil B3 in FIG. 3B;
  • Fig. 4 is the enlarged schematic view of the dotted line box X8 in Fig. 1A;
  • FIG. 5 is the third schematic top view of the wiring substrate provided by the embodiment of the present disclosure.
  • FIG. 6A is a fourth schematic top view of a wiring substrate provided by an embodiment of the present disclosure.
  • FIG. 6B is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the left control area 2 in FIG. 6A;
  • FIG. 6C is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the right control area 2 in FIG. 6A;
  • Fig. 6D is an enlarged schematic diagram of the dotted line box X5 in Fig. 6A;
  • FIG. 6E is an enlarged schematic diagram of the dotted line box X6 in FIG. 6A;
  • FIG. 7A is a fifth schematic top view of a wiring substrate provided by an embodiment of the present disclosure.
  • FIG. 7B is an enlarged layout at the dotted line circle B3 in FIG. 7A;
  • FIG. 7C is the sixth schematic top view of the wiring substrate provided by the embodiment of the present disclosure.
  • FIG. 7D is an enlarged schematic diagram of FIG. 7C along the dotted line frame B4;
  • FIG. 7E is an enlarged schematic diagram of FIG. 7D at the dotted line frame B5;
  • FIG. 8 is a seventh schematic top view of a wiring substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is an eighth schematic top view of a wiring substrate provided by an embodiment of the present disclosure.
  • the present disclosure relates to a semiconductor product, specifically, a product including multiple components. Specifically, the multiple components are divided into different functional component areas, and at least one functional component area is controlled by a driver chip. The function of each pin and the working mode of the driver chip.
  • the product includes signal lines that provide electrical signals to the driver chip and the functional component area, and the connection between the driver chip and the functional component area, or between different driver chips. Wire.
  • circuits with different functions can be located in different layers, for example, signal lines and connecting lines are located in different film layers, so as to ensure that circuits with different functions have enough layout space, Ensure the stability and reliability of the electrical connection.
  • the lines in the product are distributed in different film layers, if the lines in different layers overlap in space, a capacitor (C) structure will be formed, and the lines in each layer have their own resistance (R).
  • R resistance
  • RC-delay transmission delay
  • the backplane includes The pad structure to be electrically connected to the functional element, but because it needs to be electrically connected to the functional element, its surface is exposed, and it is easy to be invaded by foreign objects and water vapor in the environment, and the pad structure is usually connected to a certain circuit.
  • the same layer and the same material are installed, which can easily lead to short circuit or failure of the circuit, which seriously affects the reliability of the product.
  • FIG. 1A is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the left control area 2
  • FIG. 1C is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the right control area 2 in FIG. 1A
  • FIG. The enlarged schematic diagram of box X1 is the enlarged schematic diagram of the dotted line box X2 in FIG. 1A, FIG.
  • FIG. 2B is the enlarged structural schematic diagram of the drive circuit pad group 21 in the left control area 2 in FIG. 2A
  • FIG. 2C is the enlarged schematic diagram of the right side in FIG. 2A
  • FIG. 2D is an enlarged schematic diagram of the dotted line frame X3 in FIG. 2A
  • FIG. 2E is an enlarged schematic diagram of the dotted line box X4 in FIG. 2A
  • FIG. 3A is a dotted line coil B1 in FIG. 2D
  • Figure 3B is an enlarged layout of the dotted line coil B2 in Figure 2E
  • Figure 3C is an enlarged schematic diagram of the dotted line coil B3 in Figure 3B
  • an embodiment of the present disclosure provides a wiring substrate, including:
  • any one of the multiple control areas 2 includes:
  • each drive circuit pad group 21 may include a plurality of pads for corresponding connection with multiple pins of the drive circuit.
  • the drive circuit includes input pins, output pins, ground pins, and power supply pins.
  • the drive circuit pad group can include input pads DI, output pads OUT, ground pads GND, and power pads PWR. .
  • the input pad DI is used for corresponding connection with the input pin
  • the output pad OUT is used for corresponding connection with the output pin
  • the ground pad GND is used for connection with the ground pin
  • the power supply pad PWR is used for connection with the power supply pin.
  • the pin corresponds to the connection.
  • the wiring substrate can provide the drive circuit with an address signal through the input pad DI, and provide the drive circuit with an operating voltage and transmit data signals through the power supply pad PWR.
  • the data signal can be used to control the working state of the corresponding functional element
  • the reference potential voltage is provided to the driving circuit through the grounding pad GND, and the driving circuit outputs the input pad DI of the next-level driving circuit through the output pad OUT in the first period. Transmitting the relay address signal, and forming a signal loop with the functional element in the second time period;
  • each functional component pad group 22 is electrically connected to the drive circuit pad group 21; specifically, each functional component pad group 22 may include multiple sub-pad groups;
  • the first connection line 24 is configured to cascade two adjacent drive circuit pad groups 21 in the first direction A1;
  • the orthographic projection of the first connection line 24 on the base substrate 1 and the orthographic projection of the signal line 23 on the base substrate 1 do not overlap each other.
  • the orthographic projection of the first connection line 24 on the base substrate 1 of the cascaded adjacent two drive circuit pad groups 21 does not overlap with the orthographic projection of the signal line 23 on the base substrate 1 , It can avoid the risk of bad short circuit if the first connection line 24 overlaps with the signal line 23 .
  • FIG. 1A and FIG. 2A are only for illustration. Two columns of control regions 2 are provided. In actual implementation, the wiring substrate may be provided with more control regions 2, which is not limited in the embodiments of the present disclosure.
  • the signal line 23 includes a ground signal line 231 and a power supply signal line 232;
  • the ground signal line 231 and the power supply signal line 232 are respectively located on two sides of the driving circuit pad group 21 .
  • the ground signal line 231 is located on the left side of the driving circuit pad group 21, and the power supply signal line 232 is located on the right side of the driving circuit pad group 21;
  • the driving circuit pad group 21 includes : grounding pad GND, and power supply pad PWR; as shown in FIG.
  • the ground pad GND is located on the side of the power supply pad PWR close to the ground signal line 231, and the ground pad GND is electrically connected to the ground signal line 231 , the power supply pad PWR is electrically connected to the power supply signal line 232 .
  • the ground pad GND is located on the side of the power supply pad PWR close to the ground signal line 231
  • the power supply pad PWR is located on the side of the ground pad GND close to the power supply signal line 232
  • in the driving circuit pad group 21 The grounding pad GND and the grounding signal line 231 are located nearby, and the power supply pad PWR and the power supplying signal line 232 are located nearby.
  • the pad GND is electrically connected to prevent the power supply signal line 232 from bypassing other structures or wiring to be electrically connected to the power supply pad PWR. When overlapped, it is more likely to cause a short circuit defect risk situation.
  • the wiring substrate has a binding area Y, and the binding area includes multiple Binding terminals, which are used to electrically connect with external control circuits, such as flexible circuit boards, printed circuit boards, programmable logic arrays, etc., and each signal line on the wiring substrate is electrically connected to the binding terminals to receive external control circuit input electrical signal.
  • the driving circuit pad group 21 further includes: an input pad DI, and an output pad OUT.
  • the output pad OUT of the driving circuit pad group 21 is electrically connected to the functional element pad group 22. connection, and at the same time electrically connected to the input pad DI of the next-level driving circuit pad group 21, and the input pad DI of the driving circuit pad group 21 is electrically connected to the output pad OUT of the upper-level driving circuit pad group 21.
  • the output pad OUT is located close to the functional element pad group 22 in the drive circuit pad group 21 .
  • the input pad DI, the output pad OUT, the ground pad GND, and the power supply pad PWR in each driving circuit pad group 21 are distributed in two rows and two columns, and the output pad OUT is located far away from the bonding area Y. one line. Since the functional component pad group 22 is usually located on the side of the driving circuit pad group 21 away from the binding area Y, in the embodiment of the present disclosure, the output pad OUT is located in two rows and two columns of the driving circuit pad group 21 away from the binding area.
  • One line of Y can facilitate the nearby connection between the driving circuit pad group 21 and the functional element pad group 22 , and avoid more windings when the driving circuit pad group 21 is connected to the functional element pad group 22 . In a possible implementation manner, as shown in FIG.
  • the grounding pad GND is located at the lower left of the two rows and two columns; for example, as shown in Figure 1C, in the drive circuit pad group 21 of the second control region 220, the output pad OUT is located at the upper left of the two rows and two columns, and the input pad DI is located at the upper right of two rows and two columns, the grounding pad GND is located at the lower left of two rows and two columns, and the power supply pad PWR is located at the lower right of two rows and two columns.
  • the drive circuit pad groups 21 in two adjacent control areas 2 The input pads DI, output pads OUT, ground pads GND, and power supply pads PWR are arranged in different ways, so that pads in different control areas 2 can have simple wiring when they are connected to corresponding signal lines. path to avoid generating more winding paths.
  • FIG. 1A, FIG. 1B, FIG. 1C, FIG. 1D, FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 3A, and FIG. The first control area 210 and the second control area 220 adjacent to each other in the two directions A2; wherein, the plurality of drive circuit pad groups 21 in the first control area 210 start from the side close to the bonding area Y, along the first direction A1 is sequentially cascaded; multiple driving circuit pad groups 21 in the second control area 220 start from the side away from the bonding area Y, and are sequentially cascaded along the first direction A1; the first control area 210 is farthest from the bonding area
  • the driving circuit pad group 21 of Y is cascaded with the driving circuit pad group 21 farthest from the binding area Y in the second control region 220; specifically, for example, taking the example shown in FIG.
  • the first A plurality of drive circuit pad groups 21 in the control area 210 start from the side close to the bonding area Y, and are sequentially cascaded upward along the first direction A1, and a plurality of drive circuit pad groups 21 in the second control area 220 start from the side farthest to Starting from one side of the bonding area Y, cascading down in sequence along the first direction A1, the uppermost driving circuit pad group 21 in the first control area 210 is connected to the uppermost driving circuit pad group 21 in the second control area 220
  • the group 21 is cascaded to form an addressing signal loop; in the driving circuit pad group 21 of the first control area 210, the output pad OUT and the input pad DI are located in different rows; the driving circuit pad group of the second control area 220 In 210, the output pads OUT and the input pads DI are located on the same row.
  • multiple drive circuit pad groups 21 in one control area 2 are connected to the same ground signal line 231, and multiple drive circuit pad groups 21 in one control area 2 are connected to the same ground signal line 231.
  • the power supply signal line 232 that is, the ground pad GND in the same row of drive circuit pad group 21 is electrically connected to the same ground signal line 231, and the power supply pad PWR in the same column of drive circuit pad group 21 is connected to the same power supply pad group 21.
  • the signal lines 232 are electrically connected, and they are respectively placed on both sides of the driving circuit pad group 21 in order to ensure sufficient wiring space for both.
  • the relative positional relationship of multiple signal lines 23 can be the same, that is, the arrangement of signal lines 23 in one control area 2 can be used as a repeating unit ;
  • the voltage drop IR drop
  • the ground signal The line 231 needs to meet the requirement of low impedance.
  • the line width and line thickness of the ground signal line 231 can be designed to be as large as possible, and low resistivity materials (such as copper or copper alloy) can be used together to achieve the effect of low resistance.
  • the output pad OUT and the power supply pad PWR are located in the same row.
  • the output pad OUT and the ground pad GND are located in the same column;
  • the driving circuit pad group 21 of the second control area 220 the output pad OUT and the input pad DI are located in the same row, and the output pad OUT and the ground pad GND in the same column.
  • the output pad OUT is located on the upper left of the two rows and two columns
  • the power supply pad PWR is located on the upper right of the two rows and two columns
  • the ground The pad GND is located at the lower left in two rows and two columns
  • the input pad DI is located at the lower right in two rows and two columns.
  • the ground pad GND is connected to the ground signal line 231 on the left side nearby
  • the power supply pad PWR is connected to the power supply signal line 232 on the right side nearby.
  • the input pad DI is connected to the output pad OUT of the upper driving circuit pad group 21 (that is, the driving circuit pad group 21 below the current driving circuit pad group 21), and the output pad OUT is connected to the next
  • the input pads DI of the level drive circuit pad group 21 (that is, the drive circuit pad group 21 above the current drive circuit pad group 21) are connected nearby, which has a relatively simple routing method, and the first connecting line 24 can be used without To bypass other connection lines (for example, if the power supply pad is on the upper left, the ground pad is on the lower right, the input pad is on the lower left, and the output pad is on the upper right, connect the ground pad to the ground connection line of the ground signal line) , resulting in the problem of overlapping the orthographic projection of the ground signal line GND on the base substrate 1, and other connection lines (for example, if the power supply pad is located on the upper left, the ground pad is located on the lower right, the input pad is located on the lower left, and the output pad is located on the lower left.
  • the output pad OUT is located at two The upper left of the two rows and two columns, the input pad DI is located at the upper right of the two rows and two columns, the ground pad GND is located at the lower left of the two rows and two columns, and the power supply pad PWR is located at the lower right of the two rows and two columns.
  • the ground pad GND is connected to the ground signal line 231 on the left side nearby, and the power supply pad PWR is connected to the power supply signal line 232 on the right side nearby.
  • the pad DI is connected to the output pad OUT of the upper-level driving circuit pad group 21 (that is, the driving circuit pad group 21 above the current driving circuit pad group 21), and the output pad OUT is connected to the next-level driving circuit.
  • the input pads DI of the pad group 21 (that is, the drive circuit pad group 21 below the current drive circuit pad group 21) are connected nearby, and have a relatively simple routing method, and the first connecting line 24 does not need to be bypassed.
  • connection lines for example, if the power supply pad is on the upper left, the ground pad is on the lower right, the input pad is on the lower left, and the output pad is on the upper right, connect the ground pad to the ground wire of the ground signal line, and connect the current input When connecting the pad and the output pad of the next-level drive circuit pad group), there will be a problem of overlapping with the ground signal line GND on the base substrate 1, and other connecting lines (for example, if the power supply welding When the pad is located on the upper left, the ground pad is located on the lower right, the input pad is located on the lower left, and the output pad is located on the upper right, the power supply connection line when the power supply pad is connected to the power supply signal line) is projected to cross on the substrate substrate 1 .
  • the output pad OUT of the first control region 210 is located in the same row as the ground pad GND, and the output pad OUT and the power supply pad PWR are located in the same row.
  • the output pad OUT and the ground pad GND are located in the same row, and the output pad OUT and the ground pad GND are located in the same column.
  • the ground pad GND is located on the upper left of the two rows and two columns
  • the output pad OUT I is located on the upper right of the two rows and two columns.
  • the input pad D is located at the lower left of the two rows and two columns
  • the power supply pad PWR is located at the lower right of the two rows and two columns.
  • the ground pad GND and The ground signal line 231 on its left side is connected to the nearest
  • the power supply pad PWR is connected to the power supply signal line 232 on its right side
  • the input pad DI is connected to the pad group 21 of the upper-level drive circuit (that is, the current drive circuit soldering pad group 21).
  • the output pad OUT of the drive circuit pad group 21) below the pad group 21 is connected nearby, and the output pad OUT is connected to the next-level drive circuit pad group 21 (that is, the drive circuit pad above the current drive circuit pad group 21).
  • the input pad DI of group 21) is connected nearby, and has a relatively simple wiring method, and the first connecting wire 24 may not need to bypass other connecting wires (for example, if the power supply pad is located at the upper left and the ground pad is located at the lower right, When the input pad is located at the lower left and the output pad is located at the upper right, when connecting the ground pad and the ground connection line of the ground signal line), there will be a problem of overlapping with the ground signal line GND on the base substrate 1 orthographic projection, and other connections line (for example, if the power supply pad is located on the upper left, the ground pad is located on the lower right, the input pad is located on the lower left, and the output pad is located on the upper right, when the power supply pad is connected to the power supply signal line, the power supply connection line) is on the substrate substrate 1
  • the grounding pad GND and the ground pad GND are located at the left
  • the ground signal line 231 on the side is connected to the nearest
  • the power supply pad PWR is connected to the power supply signal line 232 on the right side
  • the input pad DI is connected to the upper-level drive circuit pad group 21 (that is, the current drive circuit pad group 21
  • the output pad OUT of the upper driving circuit pad group 21) is connected nearby, and the output pad OUT is connected to the next-level driving circuit pad group 21 (that is, the driving circuit pad group 21 below the current driving circuit pad group 21)
  • the input pad DI of the input pad DI is connected nearby, and has a relatively simple wiring method, and the first connecting wire 24 may not need to bypass other connecting wires (for example, if the power supply pad is located at the upper left, the ground pad is located at the lower right, and the input pad When the output pad is located at the lower left and the output pad is located at the upper right, when the ground connection line connecting the ground pad and the
  • the first connection line 24 in at least one control area 2, for example, in the driving circuit pad group 21 of the second control area 220, the first connection line 24 includes: a first The sub-connection part 241, and the second sub-connection part 242; the orthographic projection of the first sub-connection part 241 on the base substrate 1 overlaps with the orthographic projection of the driving circuit pad group 21 on the base substrate 1, and the first sub-connection One end of the portion 241 is electrically connected to the output pad OUT, and the other end is electrically connected to the second sub-connection portion 242; Specifically, taking FIG.
  • the main body direction of the first sub-connection part 241 extends along the first direction A1, and one end of the first sub-connection part 241 in the direction extending along the first direction A1 is connected to the output pad OUT.
  • the other end is electrically connected to the second sub-connection part 242; the other end of the second sub-connection part 242 is electrically connected to the input pad DI of the pad group 21 of the next-level driving circuit.
  • the output pad OUT satisfies the requirement to the side away from the bonding region Y.
  • the first connection line 24 includes the The first sub-connection part 241 inside can make the first connection wire 24 have a shorter routing path, avoiding the connection with other connection wires (for example, as shown in FIG. 1A, connecting the ground pad GND and the ground signal line 231) line 251, or the power supply connection line 252) connecting the power supply pad PWR and the power supply signal line 232 crosses.
  • the main body direction of the first sub-connection portion 241 extends along the first direction A1, and the orthographic projection of the first sub-connection portion 241 on the base substrate 1 is located on the ground pad At the gap between the orthographic projection of GND on the base substrate 1 and the orthographic projection of the power supply pad PWR on the base substrate 1 .
  • the width h 1 of the first sub-connection portion 241 in the second direction A2 is five times the minimum distance h 2 between the ground pad GND and the power supply pad PWR. One-half to one-half. In this way, while ensuring a better connection effect, avoid contact with the ground pad GND and/or the power supply pad PWR.
  • the pitch of each pad in the second direction A2 is ⁇ 100 ⁇ m, and the pitch of each pad in the first direction A1 is ⁇ 50 ⁇ m; the first sub-connecting part 241 is in the second direction A2
  • the width h1 on the top depends on the spacing of the pads in the second direction A2. For example, the spacing of the pads in the second direction A2 is 100 ⁇ m, and the line width of the wiring can be 50 ⁇ m.
  • the minimum distance h 2 between the ground pad GND of the second control region 220 and the power supply pad PWR is greater than that of the ground pad of the first control region 210 .
  • the minimum distance h 1 between the pad GND and the power supply pad PWR is convenient for the first sub-connection portion 241 to be routed between the ground pad GND and the power supply pad PWR.
  • the wiring substrate includes: the second connection line 26 ;
  • the driving circuit pad group 210 farthest from the binding area Y in the second control area 220 is cascaded through the second connection line 26 .
  • FIG. 4 is an enlarged schematic diagram of the dotted line box X8 in FIG. 1A
  • the second control region 220 includes the The first drive circuit pad group 211, and the first functional element pad group 221 farthest from the bonding area Y; the second connection line 26 extends along the second direction A2, and is located between the first drive circuit pad group 211 and The gap between the pad groups 221 of the first functional element; referring to FIG. 1A or shown in FIG.
  • the second control area 220 also includes: a bridging portion 27 of a different layer from the second connection line 26, electrically connected to the driving circuit pad group 21 and the output connection line 28 of the functional element pad group 22; wherein, the output connection line 28 includes: the first sub-output connection line 281 and the second sub-output connection line 281 which are on the same layer as the second connection line 26 and extend along the first direction A1 Output connection line 282; one end of the first output connection line 281 is electrically connected to the output pad OUT of the drive circuit pad group 21, and one end of the second sub-output connection line 282 is electrically connected to the functional element pad group 22.
  • the other end of the output connection line 281 is electrically connected to the other end of the second sub-output connection line 282 through the bridge portion 27 . That is, at the intersection position where the second connection line 26 is connected to the output connection line 28 , the output connection line 28 is disconnected and bridged to conduction through the bridging portion 27 .
  • the second connection wire 26 is located in the gap between the drive circuit pad group 21 and the functional component pad group 22, and can have a shorter routing path to avoid more winding paths; in addition, The bridging part 27 can realize the connection to the output connection line 28 at the intersection position where the second connection line 26 is connected to the output connection line 28 .
  • the second control area 220 includes the first drive circuit pad group 211 farthest from the binding area Y, and the first functional component pad group 211 farthest from the binding area Y.
  • the pad set 221 ; the second connection line 26 extends along the second direction A2 and is located on the side of the first functional component pad set 221 away from the first drive circuit pad set 211 .
  • the output connecting lines 28 of 21 cross, other connecting lines (for example, the output connecting lines 28 connecting the functional element pad group 22 and the driving circuit pad 21 as shown in FIG. 1A ) need to be bridged.
  • FIG. 6B may be a schematic diagram of the driving circuit pad group 21 of the first control region 210 in FIG. 7C
  • FIG. 6B may be a diagram of 7C is a schematic diagram of the driving circuit pad groups 21 in the second control area 220.
  • the input pads DI, DI the input pads DI, DI
  • the arrangement of the output pad OUT, the ground pad GND, and the power supply pad PWR is consistent with the input pad DI, the output pad OUT, the ground pad GND, and the power supply pads in each drive circuit pad group 21 in the second control area 220.
  • the arrangement of the disk PWR is mirror-symmetrical.
  • FIG. 6A is a schematic diagram of the enlarged structure of the pad group 21.
  • FIG. 6C is a schematic diagram of the enlarged structure of the drive circuit pad group 21 in the right control area 2 in FIG. 6A.
  • FIG. 6D is an enlarged schematic diagram of the dotted line box X5 in FIG. 6A.
  • FIG. The enlarged schematic diagram of the wire frame X6, FIG. 7B is the enlarged layout of the dotted line circle B3 in FIG.
  • the plurality of control areas 2 include the third control area 230 and the fourth control area 240 adjacent in the second direction A2; wherein, A plurality of drive circuit pad groups 21 in the third control area 230 are cascaded in sequence along the first direction A1 from the side close to the bonding area Y; Starting from one side of the bonding area Y, cascading in sequence along the first direction A1, specifically, as shown in FIG. 6A or FIG.
  • each control area 2 starts from the side close to the binding area Y, and is sequentially cascaded along the first direction A1.
  • each control area As an independent addressing loop, the number of cascaded driving circuits is small, which can make the signal delay of the first-level driving circuit pad group 21 and the last-level driving circuit pad group 21 of the same addressing loop relatively low.
  • each signal line 23 can be different, for example, it can be set as a mirror image, that is, the arrangement of the signal lines 23 in every two adjacent control areas 2 can be used as a repeating unit.
  • the third control area 230 and the fourth control area 240 may both be provided with an independent power supply signal line 232, as shown in FIG. 6A; in a possible implementation, the third control The area 230 and the fourth control area 240 can also be connected to the same power supply signal line 232, as shown in FIG.
  • the orthographic projections of the traces overlap on the base substrate 1 , there is a risk of a short circuit.
  • the third control area 230 and the fourth control area 240 are symmetrical about the first axis Z parallel to the first direction A1, wherein the minimum distance between the first axis Z and the ground signal line 231 of the third control area 230, and The minimum distance between the first axis A and the ground signal line 231 of the fourth control area 240 is the same, that is, the combinations of the third control area 230 and the fourth control area 240 are mirror-symmetrical.
  • the arrangement position of each pad in the driving circuit pad group 21 of the third control area 230 is the same as that in the driving circuit pad group 21 of the fourth control area 240.
  • the arrangement positions of the pads are mirror-symmetric; the ground signal line 231 of the third control area 230 is mirror-symmetric to the ground signal line 231 of the fourth control area 240 .
  • the output pad OUT and the power supply pad PWR are located in the same row, and the output pad and the ground pad
  • the pads are located in the same column, that is, the output pad OUT is located in the upper left of two rows and two columns, the power supply pad PWR is located in the upper right of two rows and two columns, the ground pad GND is located in the lower left of two rows and two columns, and the input pad DI is located in the bottom right in two rows and two columns.
  • the output pad OUT is located at the upper right of the two rows and two columns, and the power supply pad PWR is located at the two rows.
  • the upper left of the two columns, the ground pad GND is located at the lower right of the two rows and two columns, and the input pad DI is located at the lower left of the two rows and two columns.
  • FIG. 7C is an enlarged schematic diagram of FIG. 7C along the dotted line frame B4, and FIG.
  • FIG. 7E 7D is an enlarged schematic diagram at the dotted line box B5, the third control area 230 and the fourth control area 240 can also be cascaded on the side away from the binding area Y, specifically, the third control area 230 is the farthest
  • the driving circuit pad group 21 in the binding area Y is cascaded with the driving circuit pad group 21 farthest from the binding area Y in the fourth control area 240 through the third connection line 29, and multiple driving circuits in the third control area 230
  • the circuit pad groups 21 are sequentially cascaded along the first direction A1 starting from the side close to the bonding area Y; the plurality of driving circuit pad groups 21 in the fourth control area 240 start from the side away from the bonding area Y, Cascaded sequentially along the first direction A1, for the fourth control region 240, the output pad OUT of the driving circuit pad group 21 can be electrically connected to the input pad DI of the next-level driving circuit pad group 21 through the first connection line 24.
  • the first connection line 24 includes the first connection line 24 includes: the third sub-connection part 243, and the fourth sub-connection part 244; the third sub-connection part 243 is on the base substrate 1
  • the orthographic projection of the driving circuit pad group 21 overlaps with the orthographic projection of the driving circuit pad group 21 on the base substrate 1, one end of the third sub-connection part 243 is electrically connected to the output pad OUT, and the other end is electrically connected to the fourth sub-connection part 244;
  • the other end of the four sub-connection parts 244 is electrically connected to the input pad DI of the next-level driving circuit pad group 21; specifically, the main body direction of the third sub-connection part 243 extends along the first direction A1, and the third sub-connection part
  • the orthographic projection of 243 on the base substrate 1 is located at the gap between the orthographic projection of the input pad DI on the base substrate 1 and the orthographic projection of the ground pad GND on the base substrate 1; specifically, the third sub-connection part
  • the pitch of each pad in the second direction A2 is ⁇ 100 ⁇ m, and the pitch of each pad in the first direction A1 is ⁇ 50 ⁇ m; the third sub-connecting part 243 is in the second direction A2
  • the width h4 depends on the spacing of the pads in the second direction A2. For example, the spacing of the pads in the second direction A2 is 100 ⁇ m, and the line width of the wiring can be 50 ⁇ m.
  • the wiring substrate further includes a power line 233 located on the side of the functional element pad group 22 away from the power supply signal line 232 , and the functional element pad group 22 in the same control area 2 is electrically It is connected to the same power line 233 to supply power to the functional element pad group 22 .
  • the wiring substrate further includes a ground connection line 251 connecting the ground pad PWR and the ground signal line 231, a power supply connection line 252 connecting the power supply pad PWR and the power supply signal line 232, and connecting the output pad OUT.
  • the output connection line 28 of the functional component pad group 22, the addressing signal line 234 electrically connected to the input pad DI of the first-level drive circuit pad group 21 of the same addressing circuit, and the input pad DI and the addressing signal line 234 are connected.
  • the addressing connection line 253 of the line 234, the feedback signal line 235 electrically connected to the output pad OUT of the last stage drive circuit pad group 21 of the same addressing loop, the feedback connection connecting the output pad OUT and the feedback signal line 235 line 254.
  • the power supply signal line 232 may specifically include a power supply extension line 2321 extending from the extension direction of the main body along the second direction A2 toward the side of the driving circuit pad group 21 .
  • the wiring substrate may include a first wiring layer, and a second wiring layer located on a side of the first wiring layer away from the base substrate 1 .
  • the ground signal line 231, the power supply signal line 232, the power supply extension line 2321, the power line 233, the addressing signal line 234, the feedback signal line 235, and the bridge part 27 can all be located on the same layer, specifically, they can all be located on the first wiring layer;
  • the first connecting line 24, the second connecting line 26, the grounding connecting line 251, the power supply connecting line 252, the addressing connecting line 253, the feedback connecting line 254, and the output connecting line 28 can all be located on the same layer, specifically, they can all be located on the first Second wiring layer.
  • the second wiring layer can mainly implement logic connection and signal transmission between pad groups 21 of different driving circuits.
  • the main materials of the first wiring layer and the second wiring layer may be the same, for example, both materials may be copper.
  • the traces of different layers can be connected through the via hole K at the position that needs to be connected.
  • the ground signal line 231 on the first trace layer is connected to the ground connection line 251 through the via hole K
  • the power supply connection line 252 is connected to the power supply extension line 2321 through the via K
  • the address connection line 253 is connected to the address signal line 234 through the via K
  • the feedback connection line 254 is connected to the feedback signal line 235 through the via K.
  • the functional element pad group 22 includes a plurality of sub-pad groups S0 serially connected in series, wherein FIG. 8 is a wiring structure diagram corresponding to FIG. 1A , schematically A plurality of sub-pad groups S0 included in the functional element pad group 22 are shown. Each sub-pad group S0 can subsequently be bonded and connected to a functional element.
  • an embodiment of the present disclosure also provides a display substrate, which includes the wiring substrate provided in the embodiment of the present disclosure, and the functional component pad group 22 includes a plurality of component pads S0 connected in series; the display substrate It also includes a driving circuit bound and connected to the driving circuit pad group 21, specifically, the driving circuit can be a micro integrated circuit chip; a light-emitting element bound and connected to each sub-pad group S0, specifically, the light-emitting element can be a MiniLED Or MicroLEDs.
  • the square box in the center represents the area where the pad group 22 of the functional element is located. It can be understood that since the functional element pad group 22 can be composed of multiple sub-pad groups, for the convenience of illustration and understanding of the embodiments of the present disclosure, the polygonal frame is the outermost sub-pad group in each functional element pad group 22.
  • the graph obtained by connecting pad groups sequentially, according to the number of sub-pad groups included in the functional element pad group 22 and the relative positional relationship of each sub-pad group, the number of sides and/or shape of the polygonal frame will change accordingly .
  • the polygonal frame does not indicate the area actually occupied by the functional component pad group 22 on the wiring substrate, that is, the actual area occupied by the functional component pad group 22 on the wiring substrate may be much smaller than the area occupied by the above-mentioned polygonal frame.
  • the multiple sub-pad groups in the functional component pad group 22, which are on the wiring substrate has substantially no overlap with the orthographic projection of the signal line in the first wiring layer on the wiring substrate; for example, the main body direction of the ground signal line 231 in the first wiring layer is along the first direction
  • the ground signal line 231 can be provided with an avoidance structure, so that the ground signal line 231 is everywhere in the second direction. Width varies slightly.
  • the driving circuit pad group 21 may include other pads except the input pad DI, the output pad OUT, the ground pad GND, and the power supply pad PWR.
  • the drive circuit pad group 21 includes pads other than the above four pads, the input pad DI, the output pad OUT, the ground pad GND, and the power supply pad PWR may not be strictly in accordance with the first direction A1 and the second direction.
  • Direction A2 is distributed in two rows and two columns, but the positions of the four can be connected in sequence to form a quadrilateral, that is, the input pad DI, the output pad OUT, the ground pad GND, and the power supply pad PWR are respectively located on the four sides of the quadrangle.
  • vertex, and its location is represented by, for example, “upper left”, “lower left”, “upper right” and “lower right” in the embodiment of the present disclosure, wherein the two pads located at “upper left” and “lower left” can be considered as the same Column settings, the two pads located at “upper right” and “lower right” can be considered as the same column setting, and the two pads located at “upper left” and “upper right” can be considered as the same row setting, and the two pads located at “lower left” and " The two pads on the lower right” can be considered as the same row setting.
  • the wiring substrate adopted by the embodiment of the present disclosure further includes an anti-static trace ESD located at the periphery, which is used for anti-static protection of the wiring substrate.
  • the anti-static routing ESD is located on the periphery of any signal line, any connecting line, any routing, and the pad group of the functional element, and the functional element of the drive circuit pad group, and forms a ring structure.
  • the two sides of the ESD anti-static routing Both ends are connected to the binding terminals in the binding region Y.
  • the anti-static wiring ESD may be located on the first wiring layer.
  • an embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure.
  • the orthographic projection of the first connection line 24 for cascading two adjacent driving circuit pad groups 21 on the base substrate 1, and the signal line 23 on the base substrate do not overlap each other, which can avoid the risk of a short circuit if the first connecting line 24 overlaps with the signal line 23 .

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Abstract

一种布线基板、显示基板和显示装置。所述布线基板包括：衬底基板（1）；多个控制区域（2），所述多个控制区域（2）位于所述衬底基板（1）的一侧，所述多个控制区域（2）的每个控制区域沿第一方向（A1）延伸，所述多个控制区域（2）沿第二方向（A2）依次排列，所述多个控制区域（2）的任意一个控制区域包括：多个驱动电路焊盘组（21），沿所述第一方向（A1）依次排列；多个功能元件焊盘组（22），每个所述功能元件焊盘组（22）与所述驱动电路焊盘组（21）电连接；多条信号线（23），其主体方向均沿所述第一方向（A1）延伸；第一连接线（24），被配置为级联在所述第一方向（A1）上相邻两个所述驱动电路焊盘组（21）；所述第一连接线（24）在所述衬底基板（1）的正投影与所述信号线（23）在所述衬底基板（1）的正投影互不交叠。

Description

一种布线基板、显示基板和显示装置 技术领域
本公开涉及半导体技术领域，尤其涉及一种布线基板、显示基板和显示装置。
背景技术
微发光二极管(Mini LED)技术趋近成熟，当前各大面板厂均在发展各自的玻璃基Mini LED的显示与背光产品。由于主动式驱动效率更高，能实现更大面积的驱动，并能实现更好的亮度均一性和对比度，因此在大尺寸Mini LED背光产品中成为首选的驱动电路方案。
发明内容
本公开提供一种布线基板、显示基板和显示装置。所述布线基板包括：
衬底基板；
多个控制区域，所述多个控制区域位于所述衬底基板的一侧，所述多个控制区域的每个控制区域沿第一方向延伸，所述多个控制区域沿第二方向依次排列，所述多个控制区域的任意一个控制区域包括：
多个驱动电路焊盘组，沿所述第一方向依次排列；
多个功能元件焊盘组，每个所述功能元件焊盘组与所述驱动电路焊盘组电连接；
多条信号线，其主体方向均沿所述第一方向延伸；
第一连接线，被配置为级联在所述第一方向上相邻两个所述驱动电路焊盘组；
所述第一连接线在所述衬底基板的正投影与所述信号线在所述衬底基板的正投影互不交叠。
在一种可能的实施方式中，所述信号线包括接地信号线和供电信号线； 所述接地信号线和所述供电信号线分别位于所述驱动电路焊盘组的两侧；
所述驱动电路焊盘组包括：接地焊盘，以及供电焊盘；所述接地焊盘位于所述供电焊盘靠近所述接地信号线的一侧，所述接地焊盘与所述接地信号线电连接，所述供电焊盘与所述供电信号线电连接。
在一种可能的实施方式中，所述布线基板具有绑定区；所述驱动电路焊盘组还包括：输入焊盘，以及输出焊盘；所述输出焊盘在所述驱动电路焊盘组中位于靠近所述功能元件焊盘组的位置。
在一种可能的实施方式中，相邻两个所述控制区域的所述驱动电路焊盘组内，所述输入焊盘、所述输出焊盘、所述接地焊盘、所述供电焊盘的排列方式不同。
在一种可能的实施方式中，多个所述控制区域包括在所述第二方向上相邻的第一控制区域和第二控制区域；其中，所述第一控制区域中多个驱动电路焊盘组从靠近所述绑定区的一侧开始，沿所述第一方向依次级联；所述第二控制区域中多个驱动电路焊盘组从远离所述绑定区的一侧开始，沿所述第一方向依次级联；
所述第一控制区域中最远离所述绑定区的所述驱动电路焊盘组，与所述第二控制区域中最远离所述绑定区的驱动电路焊盘组级联；
所述第一控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述输入焊盘位于不同行；所述第二控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述输入焊盘位于同一行。
在一种可能的实施方式中，所述第一控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述供电焊盘位于同一行，所述输出焊盘与所述接地焊盘位于同一列；
所述第二控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述输入焊盘位于同一行，所述输出焊盘与所述接地焊盘位于同一列。
在一种可能的实施方式中，所述第一控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述接地焊盘位于同一行，所述输出焊盘与所述供电焊盘位 于同一列；
所述第二控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述接地焊盘位于同一行，所述输出焊盘与所述接地焊盘位于同一列。
在一种可能的实施方式中，至少一个所述控制区域内，所述第一连接线包括：第一子连接部，以及第二子连接部；
所述第一子连接部在所述衬底基板的正投影与所述驱动电路焊盘组在所述衬底基板的正投影存在交叠，所述第一子连接部一端与所述输出焊盘电连接，另一端与所述第二子连接部电连接；所述第二子连接部的另一端与下一级所述驱动电路焊盘组的所述输入焊盘电连接。
在一种可能的实施方式中，所述第一子连接部的主体方向沿所述第一方向延伸，所述第一子连接部在所述衬底基板的正投影，位于所述接地焊盘在所述衬底基板的正投影与所述供电焊盘在所述衬底基板的正投影之间的间隙处。
在一种可能的实施方式中，所述第一子连接部在所述第二方向上的宽度，为所述接地焊盘与所述供电焊盘之间最小间距的五分之一至二分之一。
在一种可能的实施方式中，所述第二控制区域的所述接地焊盘与所述供电焊盘之间的最小间距，大于所述第一控制区域的所述接地焊盘与所述输入焊盘之间的最小间距。
在一种可能的实施方式中，所述布线基板包括：第二连接线；所述第一控制区域中最远离所述绑定区的所述驱动电路焊盘组，与所述第二控制区域中最远离所述绑定区的驱动电路焊盘组通过所述第二连接线级联。
在一种可能的实施方式中，所述第二控制区域包括最远离所述绑定区的第一驱动电路焊盘组，以及最远离所述绑定区的第一功能元件焊盘组；所述第二连接线沿所述第二方向延伸，且位于所述第一驱动电路焊盘组与所述第一功能元件焊盘组之间的间隙；
所述第二控制区域还包括：电连接所述驱动电路焊盘组和所述功能元件焊盘组的输出连接线，以及与所述第二连接线不同层的桥接部；
所述输出连接线包括：与所述第二连接线同层、且沿所述第一方向延伸的第一子输出连接线和第二子输出连接线；所述第一输出连接线的一端与所述第一驱动电路焊盘组的所述输出焊盘电连接，所述第二子输出连接线的一端与所述第一功能元件焊盘组电连接，所述第一子输出连接线的另一端与所述第二子输出连接线的另一端通过所述桥接部电连接。
在一种可能的实施方式中，所述第二控制区域包括最远离所述绑定区的第一驱动电路焊盘组，以及最远离所述绑定区的第一功能元件焊盘组；所述第二连接线沿所述第二方向延伸，且位于所述第一功能元件焊盘组远离所述第一驱动电路焊盘组的一侧。
在一种可能的实施方式中，所述第一控制区域中各所述驱动电路焊盘组内所述输入焊盘、所述输出焊盘、所述接地焊盘、所述供电焊盘的排列方式，与所述第二控制区域中各所述驱动电路焊盘组内所述输入焊盘、所述输出焊盘、所述接地焊盘、所述供电焊盘的排列方式呈镜像对称。
在一种可能的实施方式中，多个所述控制区域包括在第二方向上相邻的第三控制区域和第四控制区域；其中，所述第三控制区域中多个驱动电路焊盘组从靠近所述绑定区的一侧开始，沿所述第一方向依次级联；所述第四控制区域中多个驱动电路焊盘组从靠近所述绑定区的一侧开始，沿所述第一方向依次级联；
与所述第三控制区域连接的所述供电信号线和与所述第四控制区域连接的供电信号线，位于与所述第三控制区域连接的所述接地信号线和与所述第四控制区域连接的所述接地信号线之间的间隙内。
在一种可能的实施方式中，所述第三控制区域和所述第四控制区域连接同一根供电信号线。
在一种可能的实施方式中，所述第三控制区域和所述第四控制区域整体镜像对称设置。
在一种可能的实施方式中，所述第三控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述供电焊盘位于同一行，所述输出焊盘与所述接地焊盘位 于同一列。
在一种可能的实施方式中，所述布线基板还包括位于所述功能元件焊盘组远离所述供电信号线一侧的电源线，同一所述控制区域的所述功能元件焊盘组电连接于同一所述电源线。
在一种可能的实施方式中，所述功能元件焊盘组包括多个依次串联的多个子焊盘组。
本公开实施例还提供一种显示基板，其中，包括如本公开实施例提供的所述布线基板，所述功能元件焊盘组包括多个依次串联的多个子焊盘组；
所述显示基板还包括与所述驱动电路焊盘组绑定连接的驱动电路，与所述元件焊盘组绑定连接的发光元件。
本公开实施还提供一种显示装置，其中，包括如本公开实施例提供的所述的显示基板。
附图说明
图1A为本公开实施例提供的布线基板的俯视示意图之一；
图1B为图1A中左侧控制区域2的驱动电路焊盘组21放大结构示意图；
图1C为图1A中右侧控制区域2的驱动电路焊盘组21放大结构示意图；
图1D为图1A中虚线线框X1的放大示意图；
图1E为图1A中虚线线框X2的放大示意图；
图2A为本公开实施例提供的布线基板的俯视示意图之二；
图2B为图2A中左侧控制区域2的驱动电路焊盘组21放大结构示意图；
图2C为图2A中右侧控制区域2的驱动电路焊盘组21放大结构示意图；
图2D为图2A中虚线线框X3的放大示意图；
图2E为图2A中虚线线框X4的放大示意图；
图3A为图2D虚线线圈B1处的放大版图；
图3B为图2E虚线线圈B2处的放大版图；
图3C为图3B虚线线圈B3处的放大示意图；
图4为图1A中虚线线框X8处的放大示意图；
图5为本公开实施例提供的布线基板的俯视示意图之三；
图6A为本公开实施例提供的布线基板的俯视示意图之四；
图6B为图6A中左侧控制区域2的驱动电路焊盘组21放大结构示意图；
图6C为图6A中右侧控制区域2的驱动电路焊盘组21放大结构示意图；
图6D为图6A中虚线线框X5的放大示意图；
图6E为图6A中虚线线框X6的放大示意图；
图7A为本公开实施例提供的布线基板的俯视示意图之五；
图7B为图7A中虚线线圈B3处的放大版图；
图7C为本公开实施例提供的布线基板的俯视示意图之六；
图7D为图7C沿虚线线框B4的放大示意图；
图7E为图7D在虚线线框B5处的放大示意图；
图8为本公开实施例提供的布线基板的俯视示意图之七；
图9为本公开实施例提供的布线基板的俯视示意图之八。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者 机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
本公开涉及半导体产品，具体地，为包括多个元器件的产品，具体的，多个元器件分别划分至不同的功能元件区，至少一个功能元件区被一颗驱动芯片控制，根据驱动芯片的各个引脚的功能以及驱动芯片的工作模式，产品中包括向驱动芯片和功能元件区分别提供电信号的信号线，以及将驱动芯片与功能元件区，或者不同驱动芯片之间实现电气连接的连接线。
可以理解的是，为了便于布图设计，可以将具有不同功能的线路分别位于不同层，例如，将信号线和连接线分别位于不同的膜层，从而确保不同功能线路具有足够的排布空间，保证电气连接的稳定性和可靠性。但是，由于产品中的线路分布在不同的膜层，位于不同层的线路如果在空间上存在交叠就会形成电容(C)结构，而各层线路自身又存在电阻(R)，一方面，在R和C的共同作用下，会导致线路产生严重的传输延迟(RC-delay)；另一方面，不同层线路之间虽然有绝缘层间隔，但是由于工艺制程等影响，也可能会出现短路的问题。
对于包括功能元件的半导体产品，一些情况下，是需要在背板上制作完包括线路的各个膜层后，再将功能元件与背板相连接固定；因此在设置功能元件之前，背板上包括待与功能元件电连接的焊盘结构，但其由于需要与功能元件实现电气连接，故其表面为裸露的状态，很容易受到环境中异物和水汽的侵入，而焊盘结构通常与某一线路同层同材料设置，进而极易引发线路短路或者失效，严重影响产品的信赖性。
有鉴于此，参见图1A、图1B、图1C、图1D、图1E、图2A、图2B、图2C、图2D、图2E、图3A、图3B、图3C所示，其中，图1B为图1A中左侧控制区域2的驱动电路焊盘组21放大结构示意图，图1C为图1A中右侧 控制区域2的驱动电路焊盘组21放大结构示意图，图1D为图1A中虚线线框X1的放大示意图，图1E为图1A中虚线线框X2的放大示意图，图2B为图2A中左侧控制区域2的驱动电路焊盘组21放大结构示意图，图2C为图2A中右侧控制区域2的驱动电路焊盘组21放大结构示意图，图2D为图2A中虚线线框X3的放大示意图，图2E为图2A中虚线线框X4的放大示意图，图3A为图2D虚线线圈B1处的放大版图，图3B为图2E虚线线圈B2处的放大版图，图3C为图3B虚线线圈B3处的放大示意图，本公开实施例提供一种布线基板，包括：
衬底基板1；
多个控制区域2，多个控制区域2位于衬底基板1的一侧，多个控制区域2的每个控制区域沿2第一方向A1延伸，多个控制区域2沿第二方向A2依次排列，多个控制区域2的任意一个控制区域2包括：
多个驱动电路焊盘组21，沿第一方向A1依次排列；具体的，每个驱动电路焊盘组21可以包括多个焊盘，用于与驱动电路的多个引脚对应连接。例如，驱动电路包括输入引脚、输出引脚、接地引脚和供电引脚，相应地，驱动电路焊盘组可以包括输入焊盘DI，输出焊盘OUT，接地焊盘GND，供电焊盘PWR。具体的，输入焊盘DI用于与输入引脚对应连接，输出焊盘OUT用于与输出引脚对应连接，接地焊盘GND用于与接地引脚连接，供电焊盘PWR用于与供电引脚对应连接。布线基板可以通过输入焊盘DI为驱动电路提供地址信号，通过供电焊盘PWR为驱动电路提供工作电压并传输数据信号。其中，数据信号可以用于控制对应功能元件的工作状态，通过接地焊盘GND为驱动电路提供参考电位电压，驱动电路通过输出焊盘OUT在第一时段内向下一级驱动电路的输入焊盘DI传递中继地址信号，以及在第二时段内与功能元件构成信号回路；
多个功能元件焊盘组22，每个功能元件焊盘组22与驱动电路焊盘组21电连接；具体的，每一功能元件焊盘组22内可以包括多个子焊盘组；
多条信号线23，其主体方向均沿第一方向A1延伸；
第一连接线24，被配置为级联在第一方向A1上相邻两个驱动电路焊盘组21；
第一连接线24在衬底基板1的正投影与信号线23在衬底基板1的正投影互不交叠。
本公开实施例中，级联相邻两个驱动电路焊盘组21的第一连接线24在衬底基板1的正投影，与信号线23在衬底基板1的正投影互不交叠，可以避免若第一连接线24与信号线23发生交叠时会产生短路不良的风险。
需要说明的是，图1A、图2A为了清晰地示意本公开实施例中驱动电路焊盘组21、功能元件焊盘组22、信号线23、第一连接线24的设置方式，仅是示出了两列控制区域2，在具体实施时，布线基板可以设置更多数量的控制区域2，本公开实施例不以此为限。
在一种可能的实施方式中，参见图1A、图1B、图1C、图1D、图2A、图2B、图2C、图2D所示，信号线23包括接地信号线231和供电信号线232；接地信号线231和供电信号线232分别位于驱动电路焊盘组21的两侧。具体的，例如，如图1A或图2A中，接地信号线231位于驱动电路焊盘组21的左侧，供电信号线232位于驱动电路焊盘组21的右侧；驱动电路焊盘组21包括：接地焊盘GND，以及供电焊盘PWR；结合图1D或图2D所示，接地焊盘GND位于供电焊盘PWR靠近接地信号线231的一侧，接地焊盘GND与接地信号线231电连接，供电焊盘PWR与供电信号线232电连接。本公开实施例中，接地焊盘GND位于供电焊盘PWR靠近接地信号线231的一侧，供电焊盘PWR位于接地焊盘GND靠近供电信号线232的一侧，驱动电路焊盘组21中，接地焊盘GND与接地信号线231就近设置，供电焊盘PWR与供电信号线232就近设置，整体布线简洁，无较多绕线，可以避免接地信号线231需绕过其它结构或走线与接地焊盘GND电连接，避免供电信号线232需绕过其它结构或走线与供电焊盘PWR电连接，同时，也可以避免第一连接线24需要绕过其它结构或走线，与信号线产生交叠时，较容易发生短路不良风险的情形。在一种可能的实施方式中，结合图1A、图1B、图1C、图1D、图 2A、图2B、图2C、图2D所示，布线基板具有绑定区Y，绑定区包括多个绑定端子，其用于与外部控制电路，例如柔性电路板、印刷电路板、可编程逻辑阵列等电连接，而布线基板上的各信号线与绑定端子电连接，以接收外部控制电路输入的电信号。驱动电路焊盘组21还包括：输入焊盘DI，以及输出焊盘OUT。具体的，结合图1A、图1D、图1E、图2A、图2D、图2E所示，每一控制区域2中，驱动电路焊盘组21的输出焊盘OUT与功能元件焊盘组22电连接，同时与下一级驱动电路焊盘组21的输入焊盘DI电连接，驱动电路焊盘组21的输入焊盘DI与上一级驱动电路焊盘组21的输出焊盘OUT电连接。输出焊盘OUT在驱动电路焊盘组21中位于靠近功能元件焊盘组22的位置。例如，每个驱动电路焊盘组21中的输入焊盘DI，输出焊盘OUT，接地焊盘GND，供电焊盘PWR呈两行两列分布，且输出焊盘OUT位于远离绑定区Y的一行。由于功能元件焊盘组22通常位于驱动电路焊盘组21远离绑定区Y的一侧，本公开实施例中，输出焊盘OUT位于驱动电路焊盘组21两行两列中远离绑定区Y的一行，可以方便驱动电路焊盘组21与功能元件焊盘组22就近连接，避免驱动电路焊盘组21与功能元件焊盘组22连接时，产生较多的绕线。在一种可能的实施方式中，结合图1B和图1C所示，在第二方向A2上相邻的两个控制区域2，其驱动电路焊盘组21内，输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR的排列方式不同。具体的，例如，如图1B中，第一控制区域210的驱动电路焊盘组21内，输出焊盘OUT位于两行两列中的左上，供电焊盘PWR位于两行两列中的右上，接地焊盘GND位于两行两列中的左下；例如，如图1C中，第二控制区域220的驱动电路焊盘组21内，输出焊盘OUT位于两行两列中的左上，输入焊盘DI位于两行两列中的右上，接地焊盘GND位于两行两列中的左下，供电焊盘PWR位于两行两列中的右下。本公开实施例中，在接地焊盘GND与接地信号线231就近设置，供电焊盘PWR与供电信号线232就近设置的情形下，使相邻两个控制区域2中驱动电路焊盘组21内的输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR的排列方式不同，可以使不同控制区域2的焊 盘在与对应的信号线连接时，均可以具有简洁的走线路径，避免产生较多的绕线路径。
在一种可能的实施方式中，参见图1A、图1B、图1C、图1D、图2A、图2B、图2C、图2D、图3A、图3B所示，多个控制区域2包括在第二方向A2上相邻的第一控制区域210和第二控制区域220；其中，第一控制区域210中多个驱动电路焊盘组21从靠近绑定区Y的一侧开始，沿第一方向A1依次级联；第二控制区域220中多个驱动电路焊盘组21从远离绑定区Y的一侧开始，沿第一方向A1依次级联；第一控制区域210中最远离绑定区Y的驱动电路焊盘组21，与第二控制区域220中最远离绑定区Y的驱动电路焊盘组21级联；具体的，例如，以图1A所示为例，左侧的第一控制区域210中多个驱动电路焊盘组21从靠近绑定区Y的一侧开始，沿第一方向A1依次向上级联，第二控制区域220中多个驱动电路焊盘组21从最远离绑定区Y的一侧开始，沿第一方向A1依次级联向下，第一控制区域210中最上方的驱动电路焊盘组21，与第二控制区域220中最上方的驱动电路焊盘组21级联，组成一条寻址信号回路；第一控制区域210的驱动电路焊盘组21内，输出焊盘OUT与输入焊盘DI位于不同行；第二控制区域220的驱动电路焊盘组210内，输出焊盘OUT与输入焊盘DI位于同一行。如此，对于每两列控制区域2级联形成一条寻址信号回路的布线基板，通过对不同控制区域2的驱动电路焊盘组210设计各焊盘的位置关系，可以实现使焊盘在与对应的信号线连接时，具有简洁的走线路径，避免产生较多的绕线路径。
具体的，结合图1A、图2A所示，一个控制区域2中的多个驱动电路焊盘组21连接相同的接地信号线231，一个控制区域2中的多个驱动电路焊盘组21连接相同的供电信号线232，即同一列驱动电路焊盘组21中的接地焊盘GND与同一根接地信号线231电连接，而同一列驱动电路焊盘组21中的供电焊盘PWR与同一根供电信号线232电连接，为了保证二者都有充裕的布线空间，因此将其分别置于驱动电路焊盘组21的两侧。
具体的，结合图1A、图2A所示，每个控制区域2中，多个信号线23的 相对位置关系可以相同，即一个控制区域2中的信号线23的排布方式可以作为一个重复单元；此外，对于所有信号线23，压降(IR drop)会导致连接同一信号线23不同位置处的器件(例如，可以包括驱动电路，发光元件)接收到的信号幅值存在偏差，因此接地信号线231需要满足低阻抗的要求。实际布图时，可以将接地信号线231的线宽和线厚设计的尽可能大，再配合低电阻率材料(例如铜或者铜合金)，实现低电阻的效果。在一种可能的实施方式中，参见图1A、图1B、图1C、图1D所示，第一控制区域210的驱动电路焊盘组21内，输出焊盘OUT与供电焊盘PWR位于同一行，输出焊盘OUT与接地焊盘GND位于同一列；第二控制区域220的驱动电路焊盘组21内，输出焊盘OUT与输入焊盘DI位于同一行，输出焊盘OUT与接地焊盘GND位于同一列。具体的，如图1B所示，第一控制区域210的驱动电路焊盘组21内，输出焊盘OUT位于两行两列中的左上，供电焊盘PWR位于两行两列中的右上，接地焊盘GND位于两行两列中的左下，输入焊盘DI位于两行两列中的右下。如此，可以使第一控制区域210的驱动电路焊盘组21内，接地焊盘GND与位于其左侧的接地信号线231就近连接，供电焊盘PWR与位于其右侧的供电信号线232就近连接，输入焊盘DI与上一级驱动电路焊盘组21(也即当前驱动电路焊盘组21下方的驱动电路焊盘组21)的输出焊盘OUT就近连接，输出焊盘OUT与下一级驱动电路焊盘组21(也即当前驱动电路焊盘组21上方的驱动电路焊盘组21)的输入焊盘DI就近连接，具有较简洁的走线方式，第一连接线24可以无需因要绕过其它连接线(例如，若供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接接地焊盘与接地信号线的接地连接线)时，产生与接地信号线GND在衬底基板1上正投影重叠的问题，以及与其它连接线(例如，若供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接供电焊盘与供电信号线连接时供电连接线)在衬底基板1上正投影交叉的问题；第二控制区域220的驱动电路焊盘组21内，输出焊盘OUT位于两行两列中的左上，输入焊盘DI位于两行两列中的右上，接地焊盘GND位于两行 两列中的左下，供电焊盘PWR位于两行两列中的右下，如此，可以使第二控制区域220的驱动电路焊盘组21内，接地焊盘GND与位于其左侧的接地信号线231就近连接，供电焊盘PWR与位于其右侧的供电信号线232就近连接，输入焊盘DI与上一级驱动电路焊盘组21(也即当前驱动电路焊盘组21上方的驱动电路焊盘组21)的输出焊盘OUT就近连接，输出焊盘OUT与下一级驱动电路焊盘组21(也即当前驱动电路焊盘组21下方的驱动电路焊盘组21)的输入焊盘DI就近连接，具有较简洁的走线方式，第一连接线24可以无需因要绕过其它连接线(例如，若供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接接地焊盘与接地信号线的接地连接线，以及连接当前输入焊盘与下一级驱动电路焊盘组的输出焊盘的连接线)时，产生与接地信号线GND在衬底基板1上正投影重叠的问题，以及与其它连接线(例如，若供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接供电焊盘与供电信号线连接时的供电连接线)在衬底基板1上正投影交叉的问题。
在一种可能的实施方式中，参见图2B、图2C、图2D所示，第一控制区域210的输出焊盘OUT与接地焊盘GND位于同一行，输出焊盘OUT与供电焊盘PWR位于同一列；第二控制区域220的驱动电路焊盘组21内，输出焊盘OUT与接地焊盘GND位于同一行，输出焊盘OUT与接地焊盘GND位于同一列。具体的，如图2B所示，第一控制区域210的驱动电路焊盘组21内，接地焊盘GND位于两行两列中的左上，输出焊盘OUT I位于两行两列中的右上，输入焊盘D位于两行两列中的左下，供电焊盘PWR位于两行两列中的右下，如此，可以使第一控制区域220的驱动电路焊盘组21内，接地焊盘GND与位于其左侧的接地信号线231就近连接，供电焊盘PWR与位于其右侧的供电信号线232就近连接，输入焊盘DI与上一级驱动电路焊盘组21(也即当前驱动电路焊盘组21下方的驱动电路焊盘组21)的输出焊盘OUT就近连接，输出焊盘OUT与下一级驱动电路焊盘组21(也即当前驱动电路焊盘组21上方的驱动电路焊盘组21)的输入焊盘DI就近连接，具有较简洁的走线方式， 第一连接线24可以无需因要绕过其它连接线(例如，若供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接接地焊盘与接地信号线的接地连接线)时，产生与接地信号线GND在衬底基板1上正投影重叠的问题，以及与其它连接线(例如，若供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接供电焊盘与供电信号线连接时供电连接线)在衬底基板1上正投影交叉的问题；第二控制区域220的驱动电路焊盘组21内，输出焊盘OUT位于两行两列中的左上，输入焊盘DI位于两行两列中的右上，接地焊盘GND位于两行两列中的左下，供电焊盘PWR位于两行两列中的右下，如此，可以使第二控制区域220的驱动电路焊盘组21内，接地焊盘GND与位于其左侧的接地信号线231就近连接，供电焊盘PWR与位于其右侧的供电信号线232就近连接，输入焊盘DI与上一级驱动电路焊盘组21(也即当前驱动电路焊盘组21上方的驱动电路焊盘组21)的输出焊盘OUT就近连接，输出焊盘OUT与下一级驱动电路焊盘组21(也即当前驱动电路焊盘组21下方的驱动电路焊盘组21)的输入焊盘DI就近连接，具有较简洁的走线方式，第一连接线24可以无需因要绕过其它连接线(例如，若供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接接地焊盘与接地信号线的接地连接线，以及连接当前输入焊盘与下一级驱动电路焊盘组的输出焊盘的连接线)时，产生与接地信号线GND在衬底基板1上正投影重叠的问题，以及与其它连接线(例如，供电焊盘位于左上，接地焊盘位于右下，输入焊盘位于左下，输出焊盘位于右上时，连接供电焊盘与供电信号线连接时的供电连接线)在衬底基板1上正投影交叉的问题。
在一种可能的实施方式中，参见图3B和图3C所示，至少一个控制区域2内，例如，第二控制区域220的驱动电路焊盘组21内，第一连接线24包括：第一子连接部241，以及第二子连接部242；第一子连接部241在衬底基板1的正投影与驱动电路焊盘组21在衬底基板1的正投影存在交叠，第一子连接部241一端与输出焊盘OUT电连接，另一端与第二子连接部242电连接；第 二子连接部242的另一端与下一级驱动电路焊盘组21的输入焊盘DI电连接。具体的，以图3C所示为例，第一子连接部241的主体方向沿第一方向A1延伸，第一子连接部241在沿第一方向A1延伸方向上的一端与输出焊盘OUT电连接，另一端与第二子连接部242电连接；第二子连接部242的另一端与下一级驱动电路焊盘组21的输入焊盘DI电连接。本公开实施例中，对于第二控制区域220由从远离绑定区Y的一侧向靠近绑定区Y一侧的级联方式，输出焊盘OUT在满足向远离绑定区Y一侧需与功能元件焊盘组22连接，向靠近绑定区Y一侧需与下一级驱动电路焊盘组21的输入焊盘DI连接，通过使第一连接线24包括位于动电路焊盘组21内的第一子连接部241，可以使第一连接线24具有较短的走线路径，避免与其它连接线(例如，如图1A中，连接接地焊盘GND与接地信号线231的接地连接线251，或者，连接供电焊盘PWR与供电信号线232的供电连接线252)交叉。
在一种可能的实施方式中，结合图3C所示，第一子连接部241的主体方向沿第一方向A1延伸，第一子连接部241在衬底基板1的正投影，位于接地焊盘GND在衬底基板1的正投影与供电焊盘PWR在衬底基板1的正投影之间的间隙处。
在一种可能的实施方式中，结合图3C所示，第一子连接部241在第二方向A2上的宽度h 1，为接地焊盘GND与供电焊盘PWR之间最小间距h 2的五分之一至二分之一。如此，在保证具有较佳连接效果的同时，避免与接地焊盘GND和/或供电焊盘PWR接触。具体的，驱动电路焊盘组21内，各焊盘在第二方向A2上的间距≥100μm，各焊盘在第一方向A1上的间距≥50μm；第一子连接部241在第二方向A2上的宽度h1取决于各焊盘在第二方向A2上的间距，以各焊盘在第二方向A2上的间距为100μm间距为例，其走线线宽可以为50μm。
在一种可能的实施方式中，结合图1B和图1C所示，第二控制区域220的接地焊盘GND与供电焊盘PWR之间的最小间距h 2，大于第一控制区域210的接地焊盘GND与供电焊盘PWR之间的最小间距h 1。如此，在第二控制区 域220中，方便第一子连接部241在接地焊盘GND与供电焊盘PWR之间布线。
在一种可能的实施方式中，结合图1A或图2A所示，布线基板包括：第二连接线26；第一控制区域210中最远离绑定区Y的驱动电路焊盘组210，与第二控制区域220中最远离绑定区Y的驱动电路焊盘组210通过第二连接线26级联。
在一种可能的实施方式中，参见图1A、图2A和图4所示，其中，图4为图1A中虚线线框X8处的放大示意图，第二控制区域220包括最远离绑定区Y的第一驱动电路焊盘组211，以及最远离绑定区Y的第一功能元件焊盘组221；第二连接线26沿第二方向A2延伸，且位于第一驱动电路焊盘组211与第一功能元件焊盘组221之间的间隙；参见图1A或图4所示，第二控制区域220还包括：与第二连接线26不同层的桥接部27，电连接驱动电路焊盘组21和功能元件焊盘组22的输出连接线28；其中，输出连接线28包括：与第二连接线26同层、且沿第一方向A1延伸的第一子输出连接线281和第二子输出连接线282；第一输出连接线281的一端与驱动电路焊盘组21的输出焊盘OUT电连接，第二子输出连接线282的一端与功能元件焊盘组22电连接，第一子输出连接线281的另一端与第二子输出连接线282的另一端通过桥接部27电连接。即，第二连接线26与输出连接线28连接的交叉位置处，输出连接线28断开，并通过桥接部27桥接导通。本公开实施例中，第二连接线26位于驱动电路焊盘组21与功能元件焊盘组22之间的间隙，可以具有较短的走线路径，避免产生较多的绕线路径；另外，桥接部27可以实现第二连接线26与输出连接线28连接的交叉位置处，对输出连接线28的连接。
在一种可能的实施方式中，参见图5所示，第二控制区域220包括最远离绑定区Y的第一驱动电路焊盘组211，以及最远离绑定区Y的第一功能元件焊盘组221；第二连接线26沿第二方向A2延伸，且位于第一功能元件焊盘组221远离第一驱动电路焊盘组211的一侧。如此，在将第一控制区域210与第二控制区域220进行级联时，可以避免第二连接线26与其它连接线(例 如，连接第一功能元件焊盘组22与第一驱动电路焊盘21的输出连接线28)交叉时，需要对其它连接线(例如，如图1A中连接功能元件焊盘组22与驱动电路焊盘21的输出连接线28)进行桥接连接。
在一种可能的实施方式中，结合图7C、图6B、图6C所示，其中，图6B可以为图7C中第一控制区域210的驱动电路焊盘组21的示意图，图6B可以为图7C中第二控制区域220的驱动电路焊盘组21的示意图，对于相邻两列控制区域2级联的布线基板，第一控制区域210中各驱动电路焊盘组21内输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR的排列方式，与第二控制区域220中各驱动电路焊盘组21内输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR的排列方式呈镜像对称。
在一种可能的实施方式中，参见图6A、图6B、图6C、图6D、图6E、图7A、图7B所示，其中，图6B为图6A中左侧控制区域2的驱动电路焊盘组21放大结构示意图，图6C为图6A中右侧控制区域2的驱动电路焊盘组21放大结构示意图，图6D为图6A中虚线线框X5的放大示意图，图6E为图6A中虚线线框X6的放大示意图，图7B为图7A中虚线线圈B3处的放大版图；多个控制区域2包括在第二方向A2上相邻的第三控制区域230和第四控制区域240；其中，第三控制区域230中多个驱动电路焊盘组21从靠近绑定区Y的一侧开始，沿第一方向A1依次级联；第四控制区域240中多个驱动电路焊盘组21从靠近绑定区Y的一侧开始，沿第一方向A1依次级联，具体的，以图6A或图7A所示为例，第三控制区域230中多个驱动电路焊盘组21从靠近绑定区Y的下侧开始，沿第一方向A1依次向上级联；第四控制区域240中多个驱动电路焊盘组21从靠近绑定区Y的下侧开始，沿第一方向A1依次向上级联；与第三控制区域230连接的供电信号线232和与第四控制区域240连接的供电信号线232，位于与第三控制区域230连接的接地信号线231和与第四控制区域240连接的接地信号线231之间的间隙内。本公开实施例中，各个控制区域2均从靠近绑定区Y的一侧开始，沿第一方向A1依次级联，每一个控制区域2可以作为一条独立的寻址回路，在同样满足各焊盘 与对应信号线(或连接线)就近设置，使布线基板具有整体布线简洁，无较多绕线，较低短路不良风险优势的同时，相对于多个控制区域2级联，每一个控制区域作为一条独立的寻址回路，级联的驱动电路数量较少，可以使同一寻址回路的首级驱动电路焊盘组21与最后一级驱动电路焊盘组21的信号延迟量较低。
具体的，对于与第三控制区域230连接的供电信号线232和与第四控制区域240连接的供电信号线232，位于与第三控制区域230连接的接地信号线231和与第四控制区域240连接的接地信号线231之间的间隙内的情形，结合图6A、图7A所示，一个控制区域2中的多个驱动电路焊盘组21可以连接相同的接地信号线231和供电信号线232，即同一列驱动电路焊盘组21中的接地焊盘GND与同一根接地信号线231连接，而同一列驱动电路焊盘组21中的供电焊盘PWR与同一根供电信号线232连接，为了保证二者都有充裕的布线空间，因此将其分别置于驱动电路焊盘组21的两侧；每个控制区域2中，为了进一步优化布线空间，相邻的两个控制区域2中的多个信号线23的相对位置关系可以不同，例如可以为镜像设置，即每相邻两个控制区域2中的信号线23的排布方式可以作为一个重复单元。
在一种可能的实施方式中，第三控制区域230与第四控制区域240可以均设置有一条独立的供电信号线232，如图6A所示；在一种可能的实施方式中，第三控制区域230和第四控制区域240也可以是连接同一根供电信号线232，如图7A所示，如此，可以进一步简化布线基板的走线设置，避免较多走线容易发生绕线，以及较多走线在衬底基板1上正投影交叠时发生短路不良风险。
在一种可能的实施方式中，参见图6A、图6B、图6C、图6D、图6E、图7A、图7B所示，第三控制区域230和第四控制区域240整体镜像对称设置，具体的，关于第三控制区域230和第四控制区域240关于平行于第一方向A1的第一轴线Z对称，其中，第一轴线Z与第三控制区域230的接地信号线231的最小距离，和第一轴线A与第四控制区域240的接地信号线231 的最小距离相等，即第三控制区域230和第四控制区域240各个结合均呈镜像对称设置。具体的，例如，以图7A所示的布线基板为例，第三控制区域230的驱动电路焊盘组21内各焊盘的排列位置，与第四控制区域240的驱动电路焊盘组21内各焊盘的排列位置呈镜像对称；第三控制区域230的接地信号线231，与第四控制区域240的接地信号线231呈镜像对称。
在一种可能的实施方式中，参见图6B、图6C所示，第三控制区域230的驱动电路焊盘组21内，输出焊盘OUT与供电焊盘PWR位于同一行，输出焊盘与接地焊盘位于同一列，即，输出焊盘OUT位于两行两列中的左上，供电焊盘PWR位于两行两列中的右上，接地焊盘GND位于两行两列中的左下，输入焊盘DI位于两行两列中的右下。因第四控制区域240与第三控制区域240镜像对称设置，第四控制区域240的驱动电路焊盘组21内，输出焊盘OUT位于两行两列中的右上，供电焊盘PWR位于两行两列中的左上，接地焊盘GND位于两行两列中的右下，输入焊盘DI位于两行两列中的左下。
在一种可能的实施方式中，对于与第三控制区域230连接的供电信号线232和与第四控制区域240连接的供电信号线232，位于与第三控制区域230连接的接地信号线231和与第四控制区域240连接的接地信号线231之间的间隙内的情形，结合图7C、图7D和图7E所示，其中，图7D为图7C沿虚线线框B4的放大示意图，图7E为图7D在虚线线框B5处的放大示意图，第三控制区域230和第四控制区域240也可以在远离绑定区Y的一侧进行级联，具体的，第三控制区域230中最远离绑定区Y的驱动电路焊盘组21，与第四控制区域240中最远离绑定区Y的驱动电路焊盘组21通过第三连接线29级联，第三控制区域230中多个驱动电路焊盘组21从靠近绑定区Y的一侧开始，沿第一方向A1依次级联；第四控制区域240中多个驱动电路焊盘组21从远离绑定区Y的一侧开始，沿第一方向A1依次级联，对于第四控制区域240，驱动电路焊盘组21的输出焊盘OUT可以通过第一连接线24与下一级驱动电路焊盘组21的输入焊盘DI电连接；具体的，参见图7E所示，第一连接线24包括第一连接线24包括：第三子连接部243，以及第四子连接部244；第 三子连接部243在衬底基板1的正投影与驱动电路焊盘组21在衬底基板1的正投影存在交叠，第三子连接部243一端与输出焊盘OUT电连接，另一端与第四子连接部244电连接；第四子连接部244的另一端与下一级驱动电路焊盘组21的输入焊盘DI电连接；具体的，第三子连接部243的主体方向沿第一方向A1延伸，第三子连接部243在衬底基板1的正投影，位于输入焊盘DI在衬底基板1的正投影与接地焊盘GND在衬底基板1的正投影之间的间隙处；具体的，第三子连接部243在第二方向A2上的宽度h 4，为输入焊盘DI与接地焊盘GND之间最小间距h 5的五分之一至五分之四。如此，在保证具有较佳连接效果的同时，避免与输入焊盘DI和/或接地焊盘GND接触。具体的，驱动电路焊盘组21内，各焊盘在第二方向A2上的间距≥100μm，各焊盘在第一方向A1上的间距≥50μm；第三子连接部243在第二方向A2上的宽度h 4取决于各焊盘在第二方向A2上的间距，以各焊盘在第二方向A2上的间距为100μm间距为例，其走线线宽可以为50μm。
在一种可能的实施方式中，结合图1A所示，布线基板还包括位于功能元件焊盘组22远离供电信号线232一侧的电源线233，同一控制区域2的功能元件焊盘组22电连接于同一电源线233，为功能元件焊盘组22供电。
具体的，结合图1A所示，布线基板还包括连接接地焊盘PWR与接地信号线231的接地连接线251，连接供电焊盘PWR与供电信号线232的供电连接线252，连接输出焊盘OUT与功能元件焊盘组22的输出连接线28，与同一寻址回路的首级驱动电路焊盘组21的输入焊盘DI电连接的寻址信号线234，连接输入焊盘DI与寻址信号线234的寻址连接线253，与同一寻址回路的最后一级驱动电路焊盘组21的输出焊盘OUT电连接的反馈信号线235，连接输出焊盘OUT与反馈信号线235的反馈连接线254。
具体的，结合图1A所示，供电信号线232具体可以包括由主体延伸方向沿第二方向A2朝向驱动电路焊盘组21一侧延伸出的供电延伸线2321。
在具体实施时，布线基板可以包括第一走线层，以及位于第一走线层背离衬底基板1一侧的第二走线层。接地信号线231，供电信号线232，供电延 伸线2321，电源线233，寻址信号线234，反馈信号线235，桥接部27可以均位于同一层，具体可以均位于第一走线层；第一连接线24，第二连接线26、接地连接线251，供电连接线252，寻址连接线253，反馈连接线254，输出连接线28，可以均位于同一层，具体的，可以均位于第二走线层。第二走线层可以主要实现不同驱动电路焊盘组21之间的逻辑连接和信号传输。
具体的，结合图1A所示，第一走线层与第二走线层的主体材质可以相同，例如，材质可以均为铜。不同层的走线在需要连接的位置处，具体可以通过过孔K连接，具体的，例如，位于第一走线层的接地信号线231与接地连接线251通过过孔K连接，供电连接线252与供电延伸线2321通过过孔K连接，寻址连接线253与寻址信号线234通过过孔K连接，反馈连接线254与反馈信号线235通过过孔K连接。
在一种可能的实施方式中，参见图8所示，功能元件焊盘组22包括多个依次串联的多个子焊盘组S0，其中，图8为与图1A对应的走线结构图，示意出了功能元件焊盘组22包括的多个子焊盘组S0。每个子焊盘组S0后续可以与一个功能元件进行绑定连接。
基于同一发明构思，本公开实施例还提供一种显示基板，其中，包括如本公开实施例提供的布线基板，功能元件焊盘组22包括多个依次串联的多个元件焊盘S0；显示基板还包括与驱动电路焊盘组21绑定连接的驱动电路，具体的，驱动电路可以是微型集成电路芯片；与每个子焊盘组S0绑定连接的发光元件，具体地，发光元件可以是MiniLED或者MicroLED。
可以理解的是，在图1A、图1D、图1E、图2A、图2D、图2E、图5、图6A、图6D、图6E、图7A、图7C中，均以多边形框结构(图中为四边形框)代表功能元件焊盘组22所在区域。可以理解的是，由于功能元件焊盘组22可以有多个子焊盘组构成，为了便于示意和理解本公开实施例，该多边形框为将每个功能元件焊盘组22中最靠外侧的子焊盘组顺次连接得到的图形，根据功能元件焊盘组22所包括的子焊盘组的数量以及各子焊盘组的相对位置关系，多边形框的边数和/或形状会相应地变化。多边形框并不表示功能元件 焊盘组22在布线基板上实际占据的面积，即功能元件焊盘组22在布线基板上实际占据的面积可以远小于上述多边形框所占面积。
进一步地，如图3A、图3B、图7B、图8中可以看到，在布线基板上进行实际布图设计时，功能元件焊盘组22中的多个子焊盘组，其在布线基板上的正投影，与位于第一走线层中的信号线在布线基板上的正投影基本无交叠；例如第一走线层中的接地信号线231，其主体方向均沿所述第一方向延伸，但在布线基板上设置有功能元件焊盘组22中的任一个子焊盘组的位置处，接地信号线231可以设置避让结构，从而，接地信号线231各处在第二方向上的宽度略微存在差异。
可以理解的是，驱动电路焊盘组21可以包括除输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR以外的其他焊盘。当驱动电路焊盘组21包括上述四个以外的焊盘时，输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR之间可以不是严格按照沿第一方向A1和第二方向A2阵列地两行两列的分布，但可以将其四者所在位置顺次连接形成四边形，即输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR分别位于四边形的四个顶点，并以例如本公开实施例中的“左上”“左下”“右上”“右下”来代表其所在位置，其中，位于“左上”和“左下”的两个焊盘可以认为是同一列设置，位于“右上”和“右下”的两个焊盘可以认为是同一列设置，位于“左上”和“右上”的两个焊盘可以认为是同一行设置，位于“左下”和“右下”的两个焊盘可以认为是同一行设置。也就是说，本领域技术人员可以对本公开中所有实施例中，驱动电路焊盘组21中的输入焊盘DI、输出焊盘OUT、接地焊盘GND、供电焊盘PWR的具体位置进行调整，而不脱离本发明实施例的精神和范围。
在具体实施时，参见图9所示，本公开实施例通过的布线基板，还包括位于外围的防静电走线ESD，用于对布线基板进行防静电保护。具体的，防静电走线ESD位于任意信号线、任意连接线、任意走线以及功能元件焊盘组、驱动电路焊盘组功能元件的外围，并构成环状结构，防静电走线ESD的两端 均与绑定区Y中的绑定端子连接。具体的，防静电走线ESD可以位于第一走线层。
基于同一发明构思，本公开实施例还提供一种显示装置，其中，包括本公开实施例提供的显示基板。
本公开实施例中，在每个控制区域中，用于级联相邻两个驱动电路焊盘组21的第一连接线24在衬底基板1的正投影，与信号线23在衬底基板1的正投影互不交叠，可以避免若第一连接线24与信号线23发生交叠时会产生短路不良风险。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (23)

  1. 一种布线基板，其中，包括：
    衬底基板；
    多个控制区域，所述多个控制区域位于所述衬底基板的一侧，所述多个控制区域的每个控制区域沿第一方向延伸，所述多个控制区域沿第二方向依次排列，所述多个控制区域的任意一个控制区域包括：
    多个驱动电路焊盘组，沿所述第一方向依次排列；
    多个功能元件焊盘组，每个所述功能元件焊盘组与所述驱动电路焊盘组电连接；
    多条信号线，其主体方向均沿所述第一方向延伸；
    第一连接线，被配置为级联在所述第一方向上相邻两个所述驱动电路焊盘组；
    所述第一连接线在所述衬底基板的正投影与所述信号线在所述衬底基板的正投影互不交叠。
  2. 如权利要求1所述的布线基板，其中，所述信号线包括接地信号线和供电信号线；所述接地信号线和所述供电信号线分别位于所述驱动电路焊盘组的两侧；
    所述驱动电路焊盘组包括：接地焊盘，以及供电焊盘；所述接地焊盘位于所述供电焊盘靠近所述接地信号线的一侧，所述接地焊盘与所述接地信号线电连接，所述供电焊盘与所述供电信号线电连接。
  3. 如权利要求2所述的布线基板，其中，所述布线基板具有绑定区；所述驱动电路焊盘组还包括：输入焊盘，以及输出焊盘；，所述输出焊盘在所述驱动电路焊盘组中位于靠近所述功能元件焊盘组的位置。
  4. 如权利要求3所述的布线基板，其中，相邻两个所述控制区域的所述驱动电路焊盘组内，所述输入焊盘、所述输出焊盘、所述接地焊盘、所述供电焊盘的排列方式不同。
  5. 如权利要求3或4所述的布线基板，其中，多个所述控制区域包括在所述第二方向上相邻的第一控制区域和第二控制区域；其中，所述第一控制区域中多个驱动电路焊盘组从靠近所述绑定区的一侧开始，沿所述第一方向依次级联；所述第二控制区域中多个驱动电路焊盘组从远离所述绑定区的一侧开始，沿所述第一方向依次级联；
    所述第一控制区域中最远离所述绑定区的所述驱动电路焊盘组，与所述第二控制区域中最远离所述绑定区的驱动电路焊盘组级联；
    所述第一控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述输入焊盘位于不同行；所述第二控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述输入焊盘位于同一行。
  6. 如权利要求5所述的布线基板，其中，所述第一控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述供电焊盘位于同一行，所述输出焊盘与所述接地焊盘位于同一列；
    所述第二控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述输入焊盘位于同一行，所述输出焊盘与所述接地焊盘位于同一列。
  7. 如权利要求5所述的布线基板，其中，所述第一控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述接地焊盘位于同一行，所述输出焊盘与所述供电焊盘位于同一列；
    所述第二控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述接地焊盘位于同一行，所述输出焊盘与所述接地焊盘位于同一列。
  8. 如权利要求6或7所述的布线基板，其中，至少一个所述控制区域内，所述第一连接线包括：第一子连接部，以及第二子连接部；
    所述第一子连接部在所述衬底基板的正投影与所述驱动电路焊盘组在所述衬底基板的正投影存在交叠，所述第一子连接部一端与所述输出焊盘电连接，另一端与所述第二子连接部电连接；所述第二子连接部的另一端与下一级所述驱动电路焊盘组的所述输入焊盘电连接。
  9. 如权利要求8所述的布线基板，其中，所述第一子连接部的主体方向 沿所述第一方向延伸，所述第一子连接部在所述衬底基板的正投影，位于所述接地焊盘在所述衬底基板的正投影与所述供电焊盘在所述衬底基板的正投影之间的间隙处。
  10. 如权利要求9所述的布线基板，其中，所述第一子连接部在所述第二方向上的宽度，为所述接地焊盘与所述供电焊盘之间最小间距的五分之一至二分之一。
  11. 如权利要求10所述的布线基板，其中，所述第二控制区域的所述接地焊盘与所述供电焊盘之间的最小间距，大于所述第一控制区域的所述接地焊盘与所述输入焊盘之间的最小间距。
  12. 如权利要求5-11任一项所述的布线基板，其中，所述布线基板包括：第二连接线；所述第一控制区域中最远离所述绑定区的所述驱动电路焊盘组，与所述第二控制区域中最远离所述绑定区的驱动电路焊盘组通过所述第二连接线级联。
  13. 如权利要求12所述的布线基板，其中，所述第二控制区域包括最远离所述绑定区的第一驱动电路焊盘组，以及最远离所述绑定区的第一功能元件焊盘组；所述第二连接线沿所述第二方向延伸，且位于所述第一驱动电路焊盘组与所述第一功能元件焊盘组之间的间隙；
    所述第二控制区域还包括：电连接所述第一驱动电路焊盘组和所述第一功能元件焊盘组的输出连接线，以及与所述第二连接线不同层的桥接部；
    所述输出连接线包括：与所述第二连接线同层、且沿所述第一方向延伸的第一子输出连接线和第二子输出连接线；所述第一输出连接线的一端与所述驱动电路焊盘组的所述输出焊盘电连接，所述第二子输出连接线的一端与所述功能元件焊盘组电连接，所述第一子输出连接线的另一端与所述第二子输出连接线的另一端通过所述桥接部电连接。
  14. 如权利要求12所述的布线基板，其中，所述第二控制区域包括最远离所述绑定区的第一驱动电路焊盘组，以及最远离所述绑定区的第一功能元件焊盘组；所述第二连接线沿所述第二方向延伸，且位于所述第一功能元件 焊盘组远离所述第一驱动电路焊盘组的一侧。
  15. 如权利要求5所述的布线基板，其中，所述第一控制区域中各所述驱动电路焊盘组内所述输入焊盘、所述输出焊盘、所述接地焊盘、所述供电焊盘的排列方式，与所述第二控制区域中各所述驱动电路焊盘组内所述输入焊盘、所述输出焊盘、所述接地焊盘、所述供电焊盘的排列方式呈镜像对称。
  16. 如权利要求3或4所述的布线基板，其中，多个所述控制区域包括在第二方向上相邻的第三控制区域和第四控制区域；其中，所述第三控制区域中多个驱动电路焊盘组从靠近所述绑定区的一侧开始，沿所述第一方向依次级联；所述第四控制区域中多个驱动电路焊盘组从靠近所述绑定区的一侧开始，沿所述第一方向依次级联；
    与所述第三控制区域连接的所述供电信号线和与所述第四控制区域连接的供电信号线，位于与所述第三控制区域连接的所述接地信号线和与所述第四控制区域连接的所述接地信号线之间的间隙内。
  17. 如权利要求16所述的布线基板，其中，所述第三控制区域和所述第四控制区域连接同一根供电信号线。
  18. 如权利要求16或17所述的布线基板，其中，所述第三控制区域和所述第四控制区域整体镜像对称设置。
  19. 如权利要求18所述的布线基板，其中，所述第三控制区域的所述驱动电路焊盘组内，所述输出焊盘与所述供电焊盘位于同一行，所述输出焊盘与所述接地焊盘位于同一列。
  20. 如权利要求1-19任一项所述的布线基板，其中，所述布线基板还包括位于所述功能元件焊盘组远离所述供电信号线一侧的电源线，同一所述控制区域的所述功能元件焊盘组电连接于同一所述电源线。
  21. 如权利要求20所述的布线基板，其中，所述功能元件焊盘组包括多个依次串联的多个子焊盘组。
  22. 一种显示基板，其中，包括如权利要求1-21任一项所述的布线基板，所述功能元件焊盘组包括多个依次串联的多个子焊盘组；
    所述显示基板还包括与所述驱动电路焊盘组绑定连接的驱动电路，与所述元件焊盘组绑定连接的发光元件。
  23. 一种显示装置，其中，包括如权利要求22所述的显示基板。
PCT/CN2021/116166 2021-09-02 2021-09-02 一种布线基板、显示基板和显示装置 WO2023028938A1 (zh)

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