WO2022160220A1 - 布线基板、阵列基板和发光模组 - Google Patents

布线基板、阵列基板和发光模组 Download PDF

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Publication number
WO2022160220A1
WO2022160220A1 PCT/CN2021/074260 CN2021074260W WO2022160220A1 WO 2022160220 A1 WO2022160220 A1 WO 2022160220A1 CN 2021074260 W CN2021074260 W CN 2021074260W WO 2022160220 A1 WO2022160220 A1 WO 2022160220A1
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WIPO (PCT)
Prior art keywords
lead
sub
pad
via hole
input
Prior art date
Application number
PCT/CN2021/074260
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English (en)
French (fr)
Inventor
刘纯建
许邹明
王飞飞
曾琴
吴信涛
田�健
雷杰
王杰
占玉飞
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to GB2215723.4A priority Critical patent/GB2609810A/en
Priority to PCT/CN2021/074260 priority patent/WO2022160220A1/zh
Priority to US17/426,815 priority patent/US20230369233A1/en
Priority to CN202180000083.2A priority patent/CN115152334A/zh
Publication of WO2022160220A1 publication Critical patent/WO2022160220A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133611—Direct backlight including means for improving the brightness uniformity
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133612—Electrical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0274—Optical details, e.g. printed circuits comprising integral optical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a wiring substrate, an array substrate and a light-emitting module.
  • the Mini LED (mini light-emitting diode) backlight substrate adopts a direct-type design, and through the arrangement of a large number of Mini LEDs, regional dimming in a smaller range can be realized. Compared with the traditional backlight design, its optical performance is better, and it can be used in Better brightness uniformity and higher color contrast in a smaller mixing distance.
  • microchips suitable for Mini LED backlight substrates there are many different microchips suitable for Mini LED backlight substrates, but different microchips have different requirements for the wiring distribution of Mini LED backlight substrates, which leads to the need to develop backlight substrates corresponding to different microchips in a targeted manner, and Masks and intermediate substrates of different backlight substrates cannot be shared. This not only increases the development cycle and cost of different backlight substrates, but also is not conducive to simplifying the process.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a wiring substrate, an array substrate and a light-emitting module to reduce the cost of the light-emitting module.
  • a wiring substrate including a plurality of control regions distributed in an array, the plurality of control regions are arranged into a plurality of control region rows and a plurality of control region columns; any one of the control region columns includes At least two of the control areas arranged along a first direction, any one of the control area rows includes at least two of the control areas arranged along a second direction; the second direction is parallel to the plane where the wiring substrate is located and intersecting the first direction;
  • any one of the control regions includes four device regions distributed in an array, and the device regions are used to set functional devices that are electrically connected to each other; the four device regions in any one of the control regions are the first device region, a second device region, a third device region and a fourth device region; wherein the first device region is located in the first row in the first direction and in the first row in the second direction in the control region
  • the device region of the column; the second device region is the device region located in the first row in the first direction and in the second column in the second direction in the control region;
  • the third device region is In the control region, the device regions located in the second row in the first direction and in the first column in the second direction; the fourth device region is located in the control region in the first direction.
  • a second row the device regions located in the second column in the second direction;
  • the wiring substrate includes a base substrate, a first metal wiring layer and an insulating material layer that are stacked in sequence; the first metal wiring layer is provided with a driving lead extending along the first direction; in any one of the control regions In the column, the driving lead at least includes a first power supply voltage lead, a first input lead, a reference voltage lead, a second input lead and a second power supply voltage lead arranged in sequence along the second direction; the wiring substrate further has at least one signal channel extending along the first direction, and any one of the signal channels includes at least one of the control area columns; in any one of the signal channels, the drive lead further includes at least one address lead;
  • the control area includes a first control area; in one of the first control areas, the insulating material layer is provided with first power supply vias to sixth power supply vias, and first input vias to fourth input vias , the first reference via and the second reference via;
  • the first power supply vias to the third power supply vias are arranged in sequence along the first direction and respectively expose part of the first power supply voltage leads; the first power supply vias are located in the device area A (1,1) a side away from the device area A(2,1) or between the device area A(1,1) and the device area A(2,1); the second power supply The via hole is located between the device region A(1,1) and the device region A(2,1); the third power supply via hole is located in the device region A(2,1) away from the device region one side of A(1,1);
  • the fourth power supply via hole to the sixth power supply via hole are arranged in sequence along the first direction and respectively expose a partial area of the second power supply voltage lead; the fourth power supply via hole is located in the second device the side of the fourth device region away from the fourth device region or between the second device region and the fourth device region; the fifth power supply via is located in the second device region and the fourth device region between; the sixth power supply via is located on the side of the fourth device region away from the second device region;
  • the first input via hole and the second input via hole respectively expose a partial area of the first input lead; the first input via hole is located at the edge of the first device region away from the third device region and the edge of the third device region close to the first device region; the second input via hole is located on the side of the third device region away from the first device region;
  • the third input via hole and the fourth input via hole respectively expose partial regions of the second input lead; the third input via hole is located at the edge of the second device region away from the fourth device region between the fourth device region and the edge of the fourth device region close to the second device region; the fourth input via hole is located on the side of the fourth device region away from the second device region;
  • Both the first reference via hole and the second reference via hole expose a partial area of the reference voltage lead; along the first direction, the first reference via hole is located between the first device region and the Between the third device regions, the second reference via hole is located on a side of the third device region away from the first device region;
  • the insulating material layer is further provided with at least one address via hole exposing a partial area of the at least one address lead.
  • the first power via and the fourth power via are symmetric about a first axis of symmetry
  • the third power supply via hole and the sixth power supply via hole are symmetrical about the third symmetry axis; the first symmetry axis, the second symmetry axis and the third axis of symmetry extending along the first direction and coinciding with each other.
  • the first input via and the third input via are symmetric about a fourth axis of symmetry, and the second input via
  • the fifth input via is symmetric with respect to the sixth axis of symmetry; the fourth axis of symmetry and the fifth axis of symmetry extend along the first direction and coincide with each other.
  • the first power via and the fourth power via are located on the first device region and the first reference via hole
  • the second power supply via hole and the fifth power supply via hole are located between the third device region and the first reference via hole
  • the third power supply via hole The via hole and the sixth power supply via hole are located between the third device region and the second reference via hole.
  • the insulating material layer is further provided with a third reference via hole and a fourth reference via hole exposing a partial region of the reference voltage lead holes; the third reference via and the first reference via are symmetric about the sixth axis of symmetry, and the fourth reference hole and the second reference via are symmetrical about the seventh axis of symmetry; the first The sixth axis of symmetry and the seventh axis of symmetry extend along the first direction and coincide with each other.
  • the third reference via hole and the fourth reference via hole are located in the first control region. a side of the reference via hole and the second reference via hole away from the first power supply voltage lead;
  • the first power via, the first input via, the first reference via, the fourth power via, the third input via and The third reference vias form a first via group;
  • the third power vias, the second input vias, the second reference vias, the sixth power vias, and the fourth power vias The input via and the fourth reference via form a second via group;
  • the relative positions of the via holes in the first via hole group are the same as the relative positions of the via holes in the second via hole group.
  • the insulating material layer is further provided with a fifth reference via hole exposing a partial region of the reference voltage lead. Reference vias are located between four of the device regions.
  • the insulating material layer is further provided with a fifth input via hole exposing a partial region of the first input lead; In the first direction, the fifth input via hole is located between the first reference via hole and the third device region; the insulating material layer may further be provided with a third input via exposing a partial region of the second input lead.
  • Six input vias; the sixth input via and the fifth input via are symmetric about an eighth axis of symmetry, and the eighth axis of symmetry extends along the first direction.
  • control area further includes a second control area; in any one of the control area columns, the second control area is located in the second control area of each of the first control areas one side of the first direction;
  • the insulating material layer is provided with seventh power supply vias to tenth power supply vias, seventh input vias to tenth input vias, and sixth reference vias to tenth reference vias via;
  • Both the seventh power supply via hole and the eighth power supply via hole expose at least a partial area of the first power supply voltage lead
  • both the ninth power supply via hole and the tenth power supply via hole expose the second power supply via hole at least a partial area of a power supply voltage lead
  • the eighth power supply via hole is located on one side of the seventh power supply via hole in the first direction, and is located between the first device region and the third device region
  • the tenth power supply via hole is located on one side of the ninth power supply via hole in the first direction, and is located between the second device region and the fourth device region
  • Both the seventh input via hole and the eighth input via hole expose a partial area of the first input lead; the seventh input via hole is located at a part of the first device region away from the third device region; side; the eighth input via is located between the first device region and the third device region; the ninth input via and the tenth input via both expose the second input lead part of the area; the ninth input via is located on the side of the second device region away from the fourth device region; the tenth input via is located between the second device region and the fourth device region between;
  • the sixth reference via hole to the tenth reference via hole all expose the reference voltage lead part region; wherein the sixth reference via hole and the seventh reference via hole are arranged along the second direction and between the first device region and the third device region; the eighth reference via hole is located between the first device region and the third device region, and the ninth reference via hole is located in the between the second device region and the fourth device region, and the tenth reference via hole is located between the four device regions in the second control region.
  • the wiring substrate includes a fan-out area, and the first metal wiring layer is provided with a fan-out lead connected to each of the driving leads in the fan-out area; wherein, The driving leads are connected to the corresponding fan-out leads in the second control region.
  • the number of the address leads is not less than the number of the control area rows
  • the address via hole includes a first address via hole and a second address via hole; the first address via hole is arranged close to one end of the address lead, and at least one of the first address vias is arranged in any one of the signal channels.
  • the address vias further include third address vias; along the first direction, the first address vias and the third address vias are respectively distributed in Both ends of the wiring substrate; in one of the signal channels, the number of the address leads is at least two, the number of the third address vias is at least 1, and at least one of the first address vias and At least one of the third address via holes respectively exposes different of the address leads.
  • two of the address leads are arranged in one of the control area columns, and one of the first address via hole and one of the third address via hole are arranged; so The first address via exposes one of the address leads, and the third address via exposes the other address lead.
  • both ends of any one of the address leads are exposed by the first address via hole and the third address via hole, respectively.
  • the number of the second address vias is the same as the number of the control area rows, and each of the second address vias is provided in a one-to-one correspondence with each of the control area rows ;
  • Each of the second address via holes exposes different address leads respectively, and any one of the second address via holes is located in the corresponding row of the control area.
  • the number of the second address vias is the same as the number of the address leads and is arranged in a one-to-one correspondence, and any one of the second address vias is arranged in a one-to-one correspondence.
  • Address vias expose the corresponding address leads.
  • the first metal wiring layer further has a first voltage distribution line extending along the second direction, and each of the driving leads is located at all of the first voltage distribution lines.
  • the first power supply voltage lead and the second power supply voltage lead extend along the opposite direction of the first direction to connect with the first voltage distribution line, or the reference voltage lead is along the The opposite direction of the first direction extends to connect with the first voltage distribution line.
  • the first metal wiring layer further includes a second voltage distribution line extending along the second direction; wherein the first voltage distribution line is located at the second voltage between the distribution line and each of the driving leads.
  • an array substrate including the above-mentioned wiring substrate.
  • the array substrate further includes a second metal wiring layer and an insulating protective layer sequentially stacked on a side of the insulating material layer of the wiring substrate away from the base substrate, and includes Multiple functional devices and multiple microchips;
  • the second metal wiring layer includes a plurality of connecting leads, a plurality of device pad groups and a plurality of chip pad groups, the functional device is bound and connected to the device pad groups, and the microchip is connected to all the chip pad groups.
  • the chip pad group is bound and connected; the device pad group and the chip pad group are connected with the connection lead; at least part of the connection lead is connected to the connection lead through at least part of the via hole provided on the insulating material layer.
  • the first metal wiring layer is connected.
  • a device control circuit is provided in any one of the device regions, and the device control circuit includes one of the functional devices or a plurality of the functional devices that are electrically connected;
  • Connecting leads are connected; between the first end of the device control circuit in the third device area and the first power supply voltage lead, through the second power supply via hole or the third power supply via hole overlapping the connection lead is connected; between the first end of the device control circuit in the second device area and the second power supply voltage lead, through the connection lead that overlaps with the fourth power supply via hole connection; between the first end of the device control circuit in the fourth device area and the second power supply voltage lead, through the fifth power supply via hole or the sixth power supply via hole overlapping the Connection lead connections.
  • the array substrate in one of the control regions, is provided with four chip pad groups corresponding to the four device regions one-to-one;
  • the chip pad group includes a reference voltage sub-pad, an output sub-pad, a first input sub-pad and a second input sub-pad; the second end of the device control circuit in any one of the device regions is connected to all the The output sub-pads of the chip pad group corresponding to the device area are connected by the connecting leads;
  • each of the device regions is numbered sequentially, and the device region numbered 1 is located at one end of the signal channel in the first direction; the chips corresponding to each of the device regions
  • the pad groups are cascaded in sequence according to the numbering sequence of the device area; between the second input sub-pad of the chip pad group corresponding to the device area numbered 1 and one of the address leads, Connected through the connecting leads overlapping the address vias; the output sub-pads of the chip pad group corresponding to the device area numbered (n-1) are connected to the output sub-pads of the chip pad group numbered n
  • the second input sub-pads of the chip pad group corresponding to the device area are connected by the connection leads; n is a positive integer greater than 1 and not greater than the number of the device areas in one of the signal channels;
  • the reference voltage sub-pads of the chip pad group corresponding to the first device region and all the chip pad groups corresponding to the second device region are connected through the connection lead overlapping the first reference via hole; the chip pad group corresponding to the third device region Between the reference voltage sub-pad and the reference voltage sub-pad of the chip pad group corresponding to the fourth device region and the reference voltage lead, pass through all the overlapped with the second reference via hole.
  • the connection lead is connected; the first input sub-pad of the chip pad group corresponding to the first device area and the first input lead are connected by a hole that overlaps with the first input via hole.
  • connection lead is connected; the first input sub-pad of the chip pad group corresponding to the third device area and the first input lead are overlapped with the second input via hole
  • connection lead is connected; the first input sub-pad of the chip pad group corresponding to the second device area and the second input lead are connected by intersecting the third input via hole.
  • the connection leads of the stack are connected; between the first input sub-pad and the second input lead of the chip pad group corresponding to the fourth device area, through the fourth input via hole
  • the connecting leads that overlap are connected.
  • the array substrate in one of the control regions, is provided with four chip pad groups corresponding to the four device regions one-to-one;
  • the chip pad group includes a reference voltage sub-pad, an output sub-pad, a first input sub-pad and a second input sub-pad; the second end of the device control circuit in any one of the device regions is connected to all the The output sub-pads of the chip pad group corresponding to the device area are connected by the connecting leads;
  • each of the device regions is numbered sequentially, and the device region numbered 1 is located at one end of the signal channel in the first direction; the chips corresponding to each of the device regions
  • the pad groups are cascaded in sequence according to the numbering sequence of the device area; between the second input sub-pad of the chip pad group corresponding to the device area numbered 1 and one of the address leads, Connected through the connecting leads overlapping the address vias; the output sub-pads of the chip pad group corresponding to the device area numbered (n-1) are connected to the output sub-pads of the chip pad group numbered n
  • the second input sub-pads of the chip pad group corresponding to the device area are connected by the connection leads; n is a positive integer greater than 1 and not greater than the number of the device areas in one of the signal channels;
  • connection leads overlapped by the input via holes are connected; between the first input sub-pads of the chip pad group corresponding to the third device area and the first input leads, The connection leads overlapped by the two input vias are connected; between the first input sub-pad and the second input lead of the chip pad group corresponding to the second device area, through the connection with the The connection leads overlapped by the third input vias are connected; the connection between the first input sub-pad and the second input lead of the chip pad group corresponding to the fourth device area is connected to the connecting the connecting leads that the fourth input vias overlap;
  • the chip pad group corresponding to the first device region The reference voltage sub-pad and the reference voltage lead are connected through the connection lead overlapping the first reference via hole; all the chip pad groups corresponding to the third device region are connected.
  • the reference voltage sub-pad and the reference voltage lead are connected through the connection lead overlapping the second reference via hole; the chip pad group corresponding to the second device region.
  • the reference voltage sub-pad and the reference voltage lead are connected through the connection lead overlapping the third reference via hole; the reference of the chip pad group corresponding to the fourth device region
  • the voltage sub-pad and the reference voltage lead are connected through the connection lead that overlaps with the fourth reference via hole.
  • the die pad corresponding to the first device region when the wiring substrate includes the second control region, in any one of the second control regions, the die pad corresponding to the first device region
  • the chip pad group corresponding to the group and the second device region is located between the first device region and the second device region; and the chip pad group corresponding to the first device region is arranged close to the first device region , the chip pad group corresponding to the second device region is disposed close to the second device region; in the first direction, the chip pad group corresponding to the third device region is located in the first direction Between a device region and the third device region, the chip pad group corresponding to the fourth device region is between the second device region and the fourth device region;
  • the sixth reference via hole passes between the reference voltage sub-pad and the reference voltage lead
  • the overlapping connection leads are connected, and the first input sub-pad and the first input lead are connected through the connection leads that overlap with the seventh input via;
  • the seventh reference via hole passes between the reference voltage sub-pad and the reference voltage lead
  • the overlapping connection leads are connected, and the first input sub-pad and the second input lead are connected through the connection leads that overlap with the ninth input via;
  • the reference voltage sub-pad and the reference voltage lead pass through the eighth reference via hole
  • the overlapping connection leads are connected, and the first input sub-pad and the first input lead are connected through the connection lead that overlaps with the eighth input via;
  • the ninth reference via hole passes between the reference voltage sub-pad and the reference voltage lead
  • the overlapping connection leads are connected, and the first input sub-pad and the second input lead are connected through the connection leads that overlap with the tenth input via;
  • connection lead of the third device area is connected; between the first end of the device control circuit in the third device area and the first power supply voltage lead, through the connection overlapping with the eighth power supply via hole lead connection; the first end of the device control circuit in the second device area and the second power supply voltage lead are connected through the connection lead overlapping the ninth power supply via hole; the The first end of the device control circuit in the fourth device region and the second power supply voltage lead are connected through the connection lead that overlaps with the tenth power supply via hole.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions between the device areas;
  • the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; four of the device areas
  • the second end of the device control circuit inside the device is electrically connected to the four output sub-pads through the connecting leads in one-to-one correspondence;
  • the reference voltage sub-pad is located in the first direction of the address sub-pad one side;
  • the reference voltage sub-pad is located on one side of the address sub-pad in the first direction; the reference voltage sub-pad and the reference voltage lead are connected to each other through a connection between the reference voltage sub-pad and the reference voltage lead.
  • the connection lead overlapped by the second reference via is connected; one of the chip power supply sub-pad and the driving data sub-pad and the first input lead are connected with the first input via
  • the connecting lead that overlaps with the hole is connected, and the other is connected to the second input lead through the connecting lead that overlaps the third input via; the address sub-pad is connected to the address lead. are connected through the connecting leads overlapping with the address vias.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions between the device areas;
  • the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; four of the device areas
  • the second end of the device control circuit inside is electrically connected with the four output sub-pads through the connecting leads in one-to-one correspondence;
  • the reference voltage sub-pad and the reference voltage lead pass through the fifth reference via.
  • the connection leads overlapped by the holes are connected; one of the chip power sub-pads and the driving data sub-pads and the first input leads are connected through all the connection leads that overlap the first input vias.
  • the connection lead is connected, and the other is connected to the second input lead through the connection lead that overlaps the third input via hole; the address sub-pad and the address lead are connected to the Address vias overlap the connecting lead connections.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions between the device areas;
  • the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; four of the device areas
  • the second end of the device control circuit inside is electrically connected with the four output sub-pads through the connecting leads in one-to-one correspondence;
  • connection lead overlapping with the fifth input via between one of the chip power supply sub-pad and the driving data sub-pad and the first input lead connection, the other is connected to the second input lead through the connection lead overlapping the sixth input via; the address sub-pad and the address lead are connected to the address via The connecting leads that overlap are connected.
  • the device control circuit in the first device region when the wiring substrate includes the second control regions, in any one of the second control regions, the device control circuit in the first device region
  • the first end of the power supply voltage lead and the first power supply voltage lead are connected through the connection lead overlapping the seventh power supply via hole; the first end of the device control circuit in the third device area It is connected with the first power supply voltage lead through the connection lead overlapping the eighth power supply via hole; the first end of the device control circuit in the second device area is connected to the first end of the device control circuit in the second device area
  • the two power supply voltage leads are connected through the connecting lead overlapping the ninth power supply via hole; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead connected through the connecting leads overlapping the tenth power supply via hole; the second ends of the device control circuits in the four device regions are soldered to the four output sub-ports in a one-to-one correspondence.
  • the discs are connected by connecting leads;
  • the reference voltage sub-pad and the reference voltage lead are connected through the connection lead overlapping the tenth reference via hole; the chip power sub-pad and the driving data sub-pad One is connected to the first input lead through the connecting lead that overlaps the eighth input via, and the other is connected to the second input lead through a connection that overlaps the tenth input via.
  • the connection lead is connected; the address sub-pad and the address lead are connected through the connection lead that overlaps with the address via hole.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions Between the device areas;
  • the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a gate signal sub-pad, a relay signal sub-pad and four output sub-pads. pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads through the connecting leads in a one-to-one correspondence;
  • each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extending direction;
  • Chip pad groups are cascaded in sequence according to the numbering sequence of the control area; between the strobe signal sub-pads and the address leads of the chip pad group in the control area numbered 1, through The connection leads overlapping with the address vias are connected; the relay signal sub-pads of the chip pad group in the control area numbered (n-1) are connected to the relay signal sub-pads numbered n.
  • the gate signal sub-pads of the chip pad group in the control area are connected by the connecting wires;
  • n is a positive integer greater than 1 and not greater than the number of the control areas in one of the signal channels ;
  • the reference voltage sub-pad and the reference voltage lead are connected through the connection lead overlapping the second reference via hole; the chip power supply sub-pad is connected One of the pad and the driving data sub-pad is connected with the first input lead through the connection lead overlapping the first input via hole, and the other is connected with the second input lead Connected by the connection lead overlapping the third input via.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions Between the device areas;
  • the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a gate signal sub-pad, a relay signal sub-pad and four output sub-pads. pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads through the connecting leads in a one-to-one correspondence;
  • each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extending direction;
  • Chip pad groups are cascaded in sequence according to the numbering sequence of the control area; between the strobe signal sub-pads and the address leads of the chip pad group in the control area numbered 1, through The connection leads overlapping with the address vias are connected; the relay signal sub-pads of the chip pad group in the control area numbered (n-1) are connected to the relay signal sub-pads numbered n.
  • the gate signal sub-pads of the chip pad group in the control area are connected by the connection leads;
  • the reference voltage sub-pad and the reference voltage lead pass through the fifth reference via hole.
  • the overlapping connection leads are connected; one of the chip power supply sub-pad and the driving data sub-pad and the first input lead is connected through the overlap with the first input via hole.
  • the connection lead is connected, and the other is connected to the second input lead through the connection lead overlapping the third input via hole.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions Between the device areas;
  • the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a gate signal sub-pad, a relay signal sub-pad and four output sub-pads. pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads through the connecting leads in a one-to-one correspondence;
  • each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extending direction;
  • Chip pad groups are cascaded in sequence according to the numbering sequence of the control area; between the strobe signal sub-pads and the address leads of the chip pad group in the control area numbered 1, through The connection leads overlapping with the address vias are connected; the relay signal sub-pads of the chip pad group in the control area numbered (n-1) are connected to the relay signal sub-pads numbered n.
  • the gate signal sub-pads of the chip pad group in the control area are connected by the connecting wires;
  • n is a positive integer greater than 1 and not greater than the number of the control areas in one of the signal channels ;
  • the reference voltage sub-pad and the reference voltage lead pass through the connection lead is connected; one of the chip power supply sub-pad and the drive data sub-pad is connected with the first input lead through the connection lead overlapping the fifth input via hole , and the other is connected to the second input lead through the connection lead that overlaps with the sixth input via hole.
  • the device control circuit in the first device region when the wiring substrate includes the second control regions, in any one of the second control regions, the device control circuit in the first device region
  • the first end of the power supply voltage lead and the first power supply voltage lead are connected through the connection lead overlapping the seventh power supply via hole; the first end of the device control circuit in the third device area It is connected with the first power supply voltage lead through the connection lead overlapping the eighth power supply via hole; the first end of the device control circuit in the second device area is connected to the first end of the device control circuit in the second device area
  • the two power supply voltage leads are connected through the connecting lead overlapping the ninth power supply via hole; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead connected through the connecting leads overlapping the tenth power supply via hole; the second ends of the device control circuits in the four device regions are soldered to the four output sub-ports in a one-to-one correspondence.
  • the discs are connected by connecting leads;
  • the reference voltage sub-pad and the reference voltage lead are connected through the connection lead overlapping the tenth reference via hole; the chip power sub-pad and the driving data sub-pad One is connected to the first input lead through the connecting lead that overlaps the eighth input via, and the other is connected to the second input lead through a connection that overlaps the tenth input via.
  • the connecting leads are connected.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions Between the device areas;
  • the chip pad group includes two reference voltage sub-pads, chip power sub-pads, drive data sub-pads, strobe signal sub-pads, relay signal sub-pads and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads through the connecting leads in a one-to-one correspondence;
  • each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extending direction;
  • Chip pad groups are cascaded in sequence according to the numbering sequence of the control area; between the strobe signal sub-pads and the address leads of the chip pad group in the control area numbered 1, through The connection leads overlapping with the address vias are connected; the relay signal sub-pads of the chip pad group in the control area numbered (n-1) are connected to the relay signal sub-pads numbered n.
  • the gate signal sub-pads of the chip pad group in the control area are connected by the connecting wires;
  • n is a positive integer greater than 1 and not greater than the number of the control areas in one of the signal channels ;
  • the reference voltage sub-pad is located between the gate signal sub-pad and the first reference via;
  • the reference voltage sub-pad and the reference voltage lead are connected through the connection lead overlapping the first reference via hole;
  • one of the chip power sub-pad and the driving data sub-pad is connected to
  • the first input lead is connected through the connection lead that overlaps with the first input via, and the other is connected to the second input lead through all the connection lead that overlaps with the third input via.
  • the connecting leads are connected as described above.
  • the array substrate is provided with one of the chip pad groups, and the chip pad groups are located in four of the control regions Between the device areas;
  • the chip pad group includes two reference voltage sub-pads, chip power sub-pads, drive data sub-pads, strobe signal sub-pads, relay signal sub-pads and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads through the connecting leads in a one-to-one correspondence;
  • each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extending direction;
  • Chip pad groups are cascaded in sequence according to the numbering sequence of the control area; between the strobe signal sub-pads and the address leads of the chip pad group in the control area numbered 1, through The connection leads overlapping with the address vias are connected; the relay signal sub-pads of the chip pad group in the control area numbered (n-1) are connected to the relay signal sub-pads numbered n.
  • the gate signal sub-pads of the chip pad group in the control area are connected by the connection leads;
  • the reference voltage sub-pad is located on the gate signal sub-pad and the first reference via hole; the chip pad group is located on one side of the fifth reference via hole in the second direction; one of the reference voltage sub-pads and the reference voltage lead pass through the connection lead that overlaps with the first reference via is connected; the other reference voltage sub-pad and the reference voltage lead are connected through the connection lead that overlaps the fifth reference via connection; one of the chip power supply sub-pad and the driving data sub-pad is connected to the first input lead through the connection lead that overlaps the first input via hole, and the other is connected to the first input lead.
  • the second input leads are connected through the connection leads that overlap with the third input vias.
  • the device control circuit in the first device region when the wiring substrate includes the second control regions, in any one of the second control regions, the device control circuit in the first device region
  • the first end of the power supply voltage lead and the first power supply voltage lead are connected through the connection lead overlapping the seventh power supply via hole; the first end of the device control circuit in the third device area It is connected with the first power supply voltage lead through the connection lead overlapping the eighth power supply via hole; the first end of the device control circuit in the second device area is connected to the first end of the device control circuit in the second device area
  • the two power supply voltage leads are connected through the connecting lead overlapping the ninth power supply via hole; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead connected through the connecting leads overlapping the tenth power supply via hole; the second ends of the device control circuits in the four device regions are soldered to the four output sub-ports in a one-to-one correspondence.
  • the discs are connected by connecting leads;
  • connection leads of the stack are connected.
  • a light-emitting module including the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of the positions of various pins of the first chip in the present disclosure.
  • FIG. 2 is a schematic diagram of the position of each sub-pad of the first pad group in the present disclosure.
  • FIG. 3 is a schematic diagram of the positions of various pins of the second chip in the present disclosure.
  • FIG. 4 is a schematic diagram of the position of each sub-pad of the second pad group in the present disclosure.
  • FIG. 5 is a schematic diagram of the positions of various pins of the third chip in the present disclosure.
  • FIG. 6 is a schematic diagram of the position of each sub-pad of the third pad group in the present disclosure.
  • FIG. 7 is a schematic diagram of the positions of various pins of the fourth chip in the present disclosure.
  • FIG. 8 is a schematic diagram of the position of each sub-pad of the fourth pad group in the present disclosure.
  • FIG. 9 is a schematic partial structure diagram of a wiring substrate in an embodiment of the present disclosure, wherein FIG. 9 only illustrates the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 10 is a partially enlarged schematic view of the wiring substrate shown in FIG. 9 in a first control area, wherein FIG. 10 only shows the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 11 is a schematic structural diagram of a first array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 11 only illustrates the relative positions of the driving leads, at least part of the via holes provided in the insulating material layer, and the connecting leads (indicated by thick lines), the first pad group for bonding the first chip, and the functional devices in each device area.
  • FIG. 12 is a schematic structural diagram of a second array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 12 only illustrates the relative positions of the driving leads, at least part of the via holes provided in the insulating material layer, and the connecting leads (indicated by thick lines), the second pad group for bonding the second chip, the functional devices in each device area.
  • FIG. 13 is a schematic structural diagram of a third array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 13 only illustrates the relative positions of the drive leads, at least some of the via holes provided in the insulating material layer, and the connection leads (indicated by thick lines), the third pad group for bonding the third chip, the functional devices in each device area.
  • FIG. 14 is a schematic structural diagram of a fourth array substrate in a first control area according to an embodiment of the disclosure; wherein, FIG. 14 only illustrates the relative positions of the driving leads, at least some of the via holes provided in the insulating material layer, and the connecting leads (represented by thick lines), the fourth pad group for bonding the fourth chip, and the functional devices in each device area.
  • FIG. 15 is a schematic partial structure diagram of a wiring substrate in an embodiment of the disclosure, wherein FIG. 15 only illustrates the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 16 is a partially enlarged schematic view of the wiring substrate shown in FIG. 15 in a first control area, wherein FIG. 16 only shows the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 17 is a schematic structural diagram of a fifth array substrate in a first control area according to an embodiment of the disclosure; wherein, FIG. 17 only illustrates the relative positions of the driving leads, at least some of the via holes provided in the insulating material layer, and the connecting leads (indicated by thick lines), the first pad group for bonding the first chip, and the functional devices in each device area.
  • FIG. 18 is a schematic structural diagram of a sixth array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 18 only illustrates the relative positions of the driving leads, at least part of the via holes provided in the insulating material layer, and the connecting leads (indicated by thick lines), the second pad group for bonding the second chip, the functional devices in each device area.
  • FIG. 19 is a schematic structural diagram of a seventh array substrate in a first control area according to an embodiment of the disclosure; wherein, FIG. 19 only illustrates the relative positions of the driving leads, at least part of the via holes provided in the insulating material layer, and the connecting leads (indicated by thick lines), the third pad group for bonding the third chip, the functional devices in each device area.
  • FIG. 20 is a schematic structural diagram of an eighth array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 20 only illustrates the relative positions of the driving leads, at least part of the via holes provided in the insulating material layer, and the connecting leads (represented by thick lines), the fourth pad group for bonding the fourth chip, and the functional devices in each device area.
  • FIG. 21 is a schematic partial structure diagram of a wiring substrate in an embodiment of the disclosure, wherein FIG. 21 only illustrates the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 22 is a partially enlarged schematic view of the wiring substrate shown in FIG. 21 in a first control area, wherein FIG. 22 only shows the relative positions of at least some of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 23 is a schematic structural diagram of a ninth array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 23 only illustrates the relative positions of the driving leads, at least part of the via holes provided in the insulating material layer, and the connecting leads (indicated by thick lines), the first pad group for bonding the first chip, and the functional devices in each device area.
  • FIG. 24 is a schematic structural diagram of the tenth array substrate in a first control area according to an embodiment of the disclosure; wherein, FIG. 24 only illustrates the relative positions of the drive leads, at least part of the via holes provided in the insulating material layer, and the connection leads (indicated by thick lines), the second pad group for bonding the second chip, the functional devices in each device area.
  • FIG. 25 is a schematic structural diagram of the eleventh array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 25 only illustrates the relative positions and connections of the drive leads and at least some of the via holes provided in the insulating material layer. Leads (indicated by thick lines), a third pad group for bonding the third chip, functional devices within each device area.
  • FIG. 26 is a schematic structural diagram of the twelfth array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 26 only illustrates the relative positions and connections of the drive leads and at least part of the via holes provided in the insulating material layer. Leads (indicated by thick lines), the fourth pad group for bonding the fourth chip, the functional devices in each device area.
  • FIG. 27 is a schematic partial structure diagram of a wiring substrate in an embodiment of the disclosure, wherein FIG. 27 only illustrates the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 28 is a partially enlarged schematic view of the wiring substrate shown in FIG. 27 in a first control area, wherein FIG. 28 only shows the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 29 is a schematic structural diagram of the thirteenth array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 29 only illustrates the relative positions and connections of the drive leads and at least some of the via holes provided in the insulating material layer. Leads (indicated by thick lines), the first pad group for bonding the first chip, the functional devices in each device area.
  • FIG. 30 is a schematic structural diagram of a fourteenth array substrate in a first control region in an embodiment of the disclosure; wherein, FIG. 30 only illustrates the relative positions and connections of the drive leads and at least some of the via holes provided in the insulating material layer. Leads (indicated by thick lines), a second pad group for bonding the second chip, functional devices within each device area.
  • FIG. 31 is a schematic structural diagram of a fifteenth array substrate in a first control region in an embodiment of the disclosure; wherein, FIG. 31 only illustrates the relative positions and connections of the drive leads and at least part of the via holes provided in the insulating material layer. Leads (indicated by thick lines), a third pad group for bonding the third chip, functional devices within each device area.
  • FIG. 32 is a schematic structural diagram of a sixteenth array substrate in a first control area in an embodiment of the disclosure; wherein, FIG. 32 only illustrates the relative positions and connections of the drive leads and at least part of the via holes provided in the insulating material layer. Leads (indicated by thick lines), the fourth pad group for bonding the fourth chip, the functional devices in each device area.
  • FIG. 33 is a schematic diagram of a partial structure of a wiring substrate in an embodiment of the disclosure, wherein FIG. 33 only illustrates the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 34 is a partially enlarged schematic view of the wiring substrate shown in FIG. 33 in a second control area, wherein FIG. 34 only shows the relative positions of at least part of the via holes provided in the first metal wiring layer and the insulating material layer.
  • FIG. 35 is a schematic structural diagram of the seventeenth array substrate in a second control area in an embodiment of the disclosure; wherein, FIG. 35 only illustrates the relative positions and connections of the drive leads and at least part of the via holes provided in the insulating material layer. Leads (indicated by thick lines), the first pad group for bonding the first chip, the functional devices in each device area.
  • FIG. 36 is a schematic structural diagram of the eighteenth array substrate in a second control area in an embodiment of the disclosure; wherein, FIG. 36 only illustrates the relative positions and connections of the drive leads and at least some of the via holes provided in the insulating material layer. Leads (indicated by thick lines), a second pad group for bonding the second chip, functional devices within each device area.
  • FIG. 37 is a schematic diagram of the structure of the nineteenth array substrate in a second control area in an embodiment of the disclosure; wherein, FIG. 37 only illustrates the relative positions and connections of the drive leads and at least some of the via holes provided in the insulating material layer. Leads (indicated by thick lines), a third pad group for bonding the third chip, functional devices within each device area.
  • FIG. 38 is a schematic structural diagram of the twentieth array substrate in a second control area in an embodiment of the disclosure; wherein, FIG. 38 only illustrates the relative positions and connections of the drive leads and at least some of the via holes provided in the insulating material layer. Leads (indicated by thick lines), the fourth pad group for bonding the fourth chip, the functional devices in each device area.
  • FIG. 39 is a schematic partial structure diagram of an input lead and a reference voltage lead in a wiring substrate according to an embodiment of the disclosure.
  • 40 is a schematic diagram of relative positions of address vias and address leads in a wiring substrate according to an embodiment of the disclosure.
  • FIG. 41 is a schematic structural diagram of the electrical connection between a microchip and an address lead in an array substrate according to an embodiment of the disclosure.
  • FIG. 42 is a schematic structural diagram of the electrical connection between a microchip and an address lead in an array substrate according to an embodiment of the disclosure.
  • 43 is a schematic diagram of relative positions of address vias and address leads in a wiring substrate according to an embodiment of the disclosure.
  • FIG. 44 is a schematic structural diagram of the electrical connection between a microchip and an address lead in an array substrate according to an embodiment of the disclosure.
  • FIG. 45 is a schematic structural diagram of the electrical connection between a microchip and an address lead in an array substrate according to an embodiment of the disclosure.
  • FIG. 46 is a schematic diagram of a partial structure of an array substrate according to an embodiment of the disclosure, at one end away from the binding area.
  • FIG. 47 is a schematic partial structure diagram of an array substrate according to an embodiment of the disclosure, wherein FIG. 47 does not show functional devices bound and connected to the device pad group.
  • FIG. 48 is a schematic cross-sectional view of the wiring substrate at the MN position of FIG. 47 in an embodiment of the disclosure.
  • FIG. 49 is a schematic cross-sectional view of the array substrate at the MN position of FIG. 47 in an embodiment of the disclosure, wherein FIG. 49 does not show functional devices bound and connected to the device pad group.
  • FIG. 50 is a schematic structural diagram of one end of the first metal wiring layer close to the bonding area in an embodiment of the disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • an array substrate used as an active-driven Mini LED substrate may include a substrate substrate, a first metal wiring layer, an insulating material layer, a second metal wiring layer, an insulating protection layer, and a bonding layer arranged in sequence.
  • Microchips and light-emitting elements positioned on the second metal wiring layer.
  • the first metal wiring layer may be provided with driving leads;
  • the second metal wiring layer is provided with a device pad group for binding light-emitting elements and a chip pad group for binding microchips, and is also provided with a device pad group for bonding the device Connecting leads for connecting the pad group, the chip pad group and the drive lead.
  • the light-emitting element can emit light in a controlled manner.
  • the first chip 010 has four different pins, namely a first input pin 013, a second input pin 014, a reference voltage pin 011 and an output pin 012.
  • four pins are distributed in a rectangular area, and are respectively located at the four top corners of the rectangular area.
  • the reference voltage pin 011 is used to load the reference voltage GND to the first chip 010
  • the first input pin 013 is used to load the first input signal Pwr to the first chip 010
  • the second input pin 014 is used to load the first chip 010
  • the second input signal Di is loaded.
  • the first chip 010 may be configured to, according to the first input signal Pwr loaded on the first input pin 013 and the second input signal Di loaded on the second input pin 014, pass the output lead in the first period of time.
  • the pin 012 outputs a relay signal, and provides a light-emitting path for the light-emitting element through the output pin 012 in the second time period.
  • the relay signal is an address signal or a strobe signal.
  • the first chip 010 can receive the first input signal Pwr loaded on the first input pin 013 .
  • the first input signal Pwr is a power line carrier communication signal, which can provide the first chip 010 with the chip operating voltage VCC and drive data at the same time.
  • one or more light-emitting elements connected to each other can form a light-emitting area, and one light-emitting area can be connected to an output pin 012 of the first chip 010 .
  • one first chip 010 can drive one light-emitting region, and a plurality of first chips 010 can be cascaded in sequence to form a signal channel.
  • the n-th first chip 010 responds to the relay signal of the (n-1)-th first chip 010, and sends the relay signal to the (n+1)-th first chip 010, thereby realizing Control of the first chip 010 at all levels.
  • a first pad group P10 as a chip pad group needs to be set on the array substrate, and the first pad group P10 has a one-to-one correspondence with each pin of the first chip 010 of multiple sub-pads.
  • the first pad group P10 may include a reference voltage sub-pad P11 for binding connection with the reference voltage pin 011 of the first chip 010 , and an output sub-pad P11 for binding connection with the output pin 012 of the first chip 010 .
  • the second chip 020 has eight different pins, namely the chip power supply pin 023 , the driving data pin 024 , the address pin 025 , and the reference voltage pin 011 . and four output pins (including a first output pin 0221, a second output pin 0222, a third output pin 0223, and a fourth output pin 0224).
  • eight pins are distributed in a rectangular area
  • four output pins are respectively set at the four corners of the rectangular area
  • chip power pins 023 and drive data pins 024 are respectively set in the middle of the four edges of the rectangular area.
  • address pin 025 reference voltage pin 021.
  • the chip power supply pin 023 and the driving data pin 024 are respectively located on two opposite edges.
  • the chip power pin 023 is used to load the chip working voltage VCC to the second chip 020
  • the driving data pin 024 is used to load the driving data Data to the second chip 020
  • the reference voltage pin 021 is used to load the second chip 020
  • the address pin 025 is used for loading the strobe signal to the second chip 020
  • the four output pins are respectively used for loading the driving signal output by the second chip 020 .
  • the second chip 020 is configured to, under the control of the strobe signal loaded on the address pin 025, receive the driving data Data loaded on the driving data pin 024; then, according to the received driving data Data, chip power
  • the chip working voltage VCC loaded on the pin 023 and the reference voltage GND loaded on the reference voltage pin 021 respectively provide light-emitting paths for the light-emitting elements through the four output pins.
  • any output pin of the second chip 020 can be used to control one light-emitting area; that is, one second chip 020 can control four light-emitting areas to emit light independently.
  • the multiple second chips 020 can be arranged in multiple rows, and the array substrate can control the respective second chips 020 by scanning through the respective second chip rows row by row.
  • a second pad group P20 as a chip pad group needs to be set on the array substrate.
  • the second pad group P20 includes eight sub-pads, which are respectively used for connecting with the chip pads.
  • the four output sub-pads include a first output sub-pad P221 for binding connection with the first output pin 0221, and a second output sub-pad P222 for binding connection with the second output pin 0222 , a third output sub-pad P223 for binding connection with the third output pin 0223, and a fourth output sub-pad P224 for binding connection with the fourth output pin 0224.
  • eight sub-pads are distributed in a rectangular area, four output sub-pads are respectively set at the four corners of the rectangular area, and chip power sub-pads P23 and driver are respectively set in the middle of the four edges of the rectangular area.
  • the chip power supply sub-pad P23 and the driving data sub-pad P24 are respectively located on two opposite edges, and the reference voltage sub-pad P11 and the address sub-pad P25 are respectively located on the opposite two edges; the reference voltage sub-pad P11 also Can extend to the center of the rectangular area.
  • the third chip 030 includes nine pins, that is, a chip power supply pin 033 , a driving data pin 034 , a strobe signal pin 035 , and a relay signal pin. 036.
  • Reference voltage pin 031 and four output pins, the four output pins respectively include a first output pin 0321, a second output pin 0322, a third output pin 0323 and a fourth output pin 0324.
  • the nine pins are distributed in a rectangular area in an array of three rows and three columns. Four output pins are respectively set at the four corners of the rectangular area. The center of the rectangular area is set with the strobe signal pin 035.
  • the edges are respectively provided with relay signal pins 036, chip power pins 033, reference voltage pins 031 and drive data pins 034.
  • the chip power supply pin 033 and the driving data pin 034 are respectively located on two opposite edges
  • the relay signal pin 036 and the reference voltage pin 031 are respectively located on two opposite edges.
  • the chip power pin 033 is used to load the chip working voltage VCC to the third chip 030
  • the driving data pin 034 is used to load the driving data Data to the third chip 030
  • the reference voltage pin 031 is used to load the third chip 030
  • the reference voltage GND is used to load the strobe signal to the third chip 030
  • the relay signal pin 036 is used to load the relay signal output by the third chip 030
  • the four output pins are respectively used to load The driving signal output by the third chip 030 .
  • the relay signal is a kind of strobe signal.
  • the third chip 030 is configured to output through the relay signal pin 036 according to the strobe signal or the relay signal loaded on the strobe signal pin 035 and according to the driving data Data loaded on the driving data pin 034 Relay signals, and respectively provide light-emitting paths for light-emitting elements through four output pins.
  • the third chip 030 is applied to an array substrate, one or more light-emitting elements connected to each other can form a light-emitting area, and one light-emitting area can be connected to an output pin of a third chip 030 .
  • the four output pins of one third chip 030 can respectively drive one light-emitting area, that is, one third chip 030 can drive four light-emitting areas.
  • a plurality of third chips 030 can be cascaded in sequence to form a signal channel; in a signal channel, the first-level third chip 030 sends a relay signal to the second-level third chip 030 in response to the strobe signal, and the nth-level The third chip 030 responds to the relay signal of the (n-1)th stage third chip 030 and sends the relay signal to the (n+1)th stage third chip 030, thereby realizing the control of the third stage of the third chip 030.
  • a third pad group P30 as a chip pad group needs to be set on the array substrate.
  • a corresponding nine sub-pads are respectively the chip power sub-pad P33 for binding and connection with the chip power pin 033, the driving data sub-pad P34 for binding and connecting with the driving data pin 034, and the The strobe signal sub-pad P35 bound and connected to the strobe signal pin 035, the relay signal sub-pad P36 used to be bound and connected to the relay signal pin 036, and used to bind to the reference voltage pin 031
  • the connected reference voltage sub-pad P31 and the four output sub-pads for one-to-one binding connection with the four output pins.
  • the four output sub-pads respectively include a first output sub-pad P321, a second output sub-pad P322, a third output sub-pad P323 and a fourth output sub-pad P324.
  • the nine sub-pads are distributed in a rectangular area in an array of three rows and three columns.
  • Four output sub-pads are respectively set at the four corners of the rectangular area.
  • the four edges are respectively provided with relay signal sub-pads P36, chip power sub-pads P33, reference voltage sub-pads P31 and driving data sub-pads P34.
  • the chip power supply sub-pad P33 and the driving data sub-pad P34 are respectively located on two opposite edges
  • the relay signal sub-pad P36 and the reference voltage sub-pad P31 are respectively located on two opposite edges.
  • the fourth chip 040 includes ten pins, that is, a chip power supply pin 043 , a driving data pin 044 , a strobe signal pin 045 , and a relay signal pin. 046, two reference voltage pins 041 and four output pins.
  • the four output pins respectively include a first output pin 0421 , a second output pin 0422 , a third output pin 0423 and a fourth output pin 0424 .
  • the ten pins are distributed in a rectangular area in two columns and five rows. The first column is set in sequence with the first output pin 0421, the relay signal pin 046, the chip power supply pin 043, the strobe signal pin 045 and the first output pin 046.
  • the chip power pin 043 is used to load the chip working voltage VCC to the fourth chip 040
  • the driving data pin 044 is used to load the driving data Data to the fourth chip 040
  • the reference voltage pin 041 is used to load the fourth chip 040
  • the reference voltage GND is used to load the strobe signal to the fourth chip 040
  • the relay signal pin 046 is used to load the relay signal output by the fourth chip 040
  • the four output pins are used to load the fourth chip 040.
  • the relay signal is a kind of strobe signal. When the strobe signal pin 045 of a fourth chip 040 is loaded with the relay signal, the fourth chip 040 can receive the driving data loaded on the driving data pin 044 Data.
  • the fourth chip 040 is configured to output the intermediate signal through the relay signal pin 046 according to the strobe signal or the relay signal loaded on the strobe signal pin 045 and according to the driving data loaded on the driving data pin 044. follow the signal, and respectively provide light-emitting paths for light-emitting elements through four output pins.
  • the fourth chip 040 When the fourth chip 040 is applied to the array substrate, one or more light-emitting elements connected to each other may form a light-emitting area, and one light-emitting area may be connected to an output pin of a fourth chip 030 . In this way, the four output pins of the fourth chip 040 can respectively drive one light-emitting area, that is, one fourth chip 040 can drive four light-emitting areas.
  • a plurality of fourth chips 040 can be cascaded in sequence to form a signal channel; in a signal channel, the nth-level fourth chip 040 responds to the relay signal of the (n-1)th-level fourth chip 040 to the (n+th)th 1)
  • the fourth chip 040 of the stage sends a relay signal, thereby realizing the control of each fourth chip 040 .
  • a fourth pad group P40 as a chip pad group needs to be set on the array substrate, and the fourth pad group P40 includes ten pins connected to the fourth chip 040
  • the ten sub-pads in one-to-one correspondence are the chip power sub-pad P43 for binding and connection with the chip power pin 043, the driving data sub-pad P44 for binding and connection with the driving data pin 044, and the The strobe signal sub-pad P45 bound and connected to the strobe signal pin 045, the relay signal sub-pad P46 used to be bound and connected to the relay signal pin 046, and the two reference voltage pins 041 Two reference voltage sub-pads P41 for one-to-one bonding connection, and four output sub-pads for one-to-one bond connection with four output pins.
  • the four output sub-pads respectively include a first output sub-pad P421 for binding connection with the first output pin 0421, a second output sub-pad P422 for binding connection with the second output pin 0422, The third output sub-pad P423 for bonding connection with the third output pin 0423 and the fourth output sub-pad P424 for bonding connection with the fourth output pin 0424.
  • the ten sub-pads are distributed in a rectangular area in two columns and five rows, wherein the first output sub-pad P421, the relay signal sub-pad P46, the chip power sub-pad P43, and the gate signal sub-pad are arranged in sequence in the first column.
  • the pad P45 and the third output sub-pad P423; the second column is provided with the second output sub-pad P422, the reference voltage sub-pad P41, the driving data sub-pad P44, the reference voltage sub-pad P41 and the fourth output sub-pad in sequence Disk P424.
  • each array substrate has different requirements for the arrangement of the driving leads located on the first metal wiring layer, the connection leads located on the second metal wiring layer and the arrangement of the device pad groups, so that Different array substrates have great differences in structure.
  • the present disclosure provides a wiring substrate.
  • the wiring substrate of the present disclosure includes a base substrate 101, a first metal wiring layer 102, and an insulating material layer 103 that are stacked in sequence, which can be used to further prepare at least two different types of array substrates, and each type The types of microchips employed on the array substrate can vary.
  • the required second metal wiring layer 104 and the insulating protection layer 105 can be further prepared, and functional devices (not shown in FIG. 49 ) and the required The desired microchip (not shown in FIG.
  • the wiring substrate of the present disclosure can be used as an intermediate substrate for different types of array substrates, so that different types of array substrates can use the same process, materials and equipment in the stage of preparing the wiring substrate, such as sharing the same mask. etc., thereby reducing the cost of different types of array substrates, and helping to improve the productivity and yield of different types of array substrates.
  • the insulating material layer 103 may be provided with a plurality of via holes exposing the first metal wiring layer 102 .
  • the second metal wiring layer 104 may be connected to the first metal wiring layer 102 through at least part of the via holes, and the rest of the via holes may be connected to the first metal wiring layer 102 .
  • the via holes may be filled with the insulating protective layer 105 .
  • the via hole used to connect the second metal wiring layer 104 and the first metal wiring layer 102 in one array substrate may still be used in another array substrate For connecting the second metal wiring layer 104 to the first metal wiring layer 102 , it may also be filled with the insulating protective layer 105 without overlapping the second metal wiring layer 104 .
  • the vias filled with the insulating protective layer 105 in one array substrate and not overlapping with the second metal wiring layer 104 are not in the other array substrates.
  • the substrate can be used to connect the second metal wiring layer 104 with the first metal wiring layer 102 , or it can still be filled with the insulating protective layer 105 without overlapping with the second metal wiring layer 104 .
  • the insulating material layer 103 of the wiring substrate of the present disclosure may be applicable to different types of array substrates by providing redundant vias.
  • the base substrate 101 may be a base substrate of an inorganic material, or may be a base substrate of an organic material.
  • the material of the base substrate may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or the like, or may be metals such as stainless steel, aluminum, and nickel. Material.
  • the material of the base substrate may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP) ), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (polycarbonate, PC), polyethylene terephthalate (PET), poly Polyethylene naphthalate (PEN) or a combination thereof.
  • PMMA polymethyl methacrylate
  • PVA polyvinyl alcohol
  • PVP polyvinyl phenol
  • PES polyether sulfone
  • polyimide polyamide
  • polyacetal polycarbonate
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PEN poly Polyethylene naphthalate
  • the base substrate 101 may be a glass substrate.
  • the first metal wiring layer 102 may include a driving lead and a fan-out lead connected with the driving lead.
  • the first metal wiring layer 102 may further include bonding pads connected to the fan-out leads. It is not covered by any other insulating film to ensure electrical connection with external signal source circuits such as printed circuit boards.
  • the first metal wiring layer 102 may include one layer of metal, or may include multiple layers of metal.
  • the first metal wiring layer 102 may include a copper seed layer 1021 and a copper growth layer 1022 sequentially stacked on one side of the base substrate 101 .
  • the copper growth layer 1022 may be disposed on the surface of the copper seed layer 1021 away from the base substrate 101, and at least part of the side surface of the copper seed layer 1021 may be exposed, for example, the copper seed layer 1021 and the copper growth layer 1022 are in the lining
  • the orthographic projections on the base substrate 101 are substantially coincident.
  • the copper growth layer 1022 may completely coat the sides of the copper seed layer 1021 and its surface away from the base substrate 101 .
  • the copper seed layer 1021 may be formed by a magnetron sputtering method, and the copper growth layer 1022 may be formed by an electroplating or electroless plating method.
  • the copper seed layer 1021 may include a first metal adhesion layer and a first copper metal layer sequentially stacked on one side of the base substrate 101 , and the first metal adhesion layer may strengthen the first copper metal layer and the base substrate.
  • the bonding force between 101; the material of the first metal adhesion layer can be an alloy material containing molybdenum, such as a molybdenum-niobium alloy, a molybdenum-niobium-copper alloy, and the like.
  • the first metal wiring layer 102 may further include a first metal protection layer on the side of the copper growth layer 1022 away from the base substrate 101, and the first metal protection layer can prevent the surface of the copper growth layer 1022 from being oxidized;
  • the material of a metal protective layer can be an alloy containing nickel or molybdenum, such as copper-nickel alloy, molybdenum-niobium alloy, molybdenum-titanium-nickel (MTD) alloy, and the like.
  • the first metal wiring layer 102 may further include an etch stop layer on the surface of the first metal wiring layer 102 away from the base substrate 101, so that when the second metal wiring layer 104 of the array substrate is prepared Etching of the first metal wiring layer 102 is reduced or avoided.
  • the material of the etch stop layer can be a conductive metal oxide, such as indium zinc oxide.
  • the first metal wiring layer 102 can be prepared in a number of different ways.
  • an unpatterned copper seed layer 1021 covering the base substrate 101 may be formed first, and then copper is deposited by electroplating copper to form an unpatterned copper growth layer 1022 , and finally pattern the patterned copper seed layer 1021 and the unpatterned copper growth layer 1022 to obtain the first metal wiring layer 102 .
  • a patterned copper seed layer 1021 may be formed first, and then a pattern defining layer covering the base substrate 101 and exposing the copper seed layer 1021 may be formed, and then electroplating copper is used.
  • the method forms a patterned copper growth layer 1022 on the patterned copper seed layer 1021 to obtain a first metal wiring layer 102; and removes the pattern defining layer.
  • an unpatterned copper seed layer 1021 covering the base substrate 101 may be formed first, and then a pattern is formed on the side of the copper seed layer 1021 away from the base substrate 101 .
  • the defining layer, the pattern defining layer only exposes the position where the copper growth layer 1022 needs to be formed; then, the patterned copper growing layer 1022 is formed on the unpatterned copper seed layer 1021 by the method of electroplating copper, and the unpatterned copper growth layer 1022 is formed after removing the pattern defining layer.
  • the patterned copper seed layer 1021 is patterned to obtain the first metal wiring layer 102 .
  • the first metal wiring layer can also be formed by a method of multiple magnetron sputtering.
  • the first metal wiring material layer may be formed by multiple times of magnetron sputtering, and the thickness of the metal layer formed by each magnetron sputtering is not greater than 1 micrometer; and then the first metal wiring material layer is patterned, to form a first metal wiring layer.
  • a plurality of metal wiring sub-layers with the same pattern may be formed in sequence, and the respective metal wiring sub-layers are stacked in sequence to form the first metal wiring layer.
  • a metal wiring material sub-layer can be formed by magnetron sputtering first, and the thickness of the metal wiring material sub-layer is not greater than 1 micron; then the metal wiring material sub-layer is patterned, to form a metal wiring sublayer.
  • the above description of the structure, material and preparation method of the first metal wiring layer is only an exemplary description of the first metal wiring layer; in other embodiments of the present disclosure, the first metal wiring layer may exhibit Other film layer structures are obtained, or other materials are used, or other methods are used to prepare them.
  • the insulating material layer 103 may include a planarized organic material layer 1032 .
  • the material of the planarizing organic material layer 1032 may be an organic material, such as polyimide, epoxy resin, phenolic resin or other organic materials.
  • the planarizing organic material layer 1032 may be an organic material containing a photosensitizer.
  • the planarizing organic material layer 1032 may provide a planarized surface for the second metal wiring layer of the array substrate, and adjust the capacitance value between the first metal wiring layer and the second metal wiring layer.
  • the insulating material layer 103 may further include a first passivation layer 1031 located between the planarized organic material layer 1032 and the first metal wiring layer 102 for protecting the first passivation layer 1031 Metal wiring layer 102 .
  • the material of the first passivation layer 1031 may be an inorganic dielectric material, such as silicon nitride, silicon oxide or silicon oxynitride. In one embodiment of the present disclosure, the material of the first passivation layer 1031 may be silicon nitride.
  • the wiring substrate and the array substrate of the present disclosure may further include a buffer layer 108 located between the base substrate 101 and the first metal wiring layer 102 for eliminating the first metal wiring layer 102 and the insulating material layer 103 stress to the base substrate 101 .
  • the material of the buffer layer 108 may be an inorganic dielectric material, such as silicon nitride, silicon oxide or silicon oxynitride. In one embodiment of the present disclosure, the material of the buffer layer 108 may be silicon nitride.
  • the array substrate provided by the present disclosure may include the wiring substrate provided by the present disclosure, a second metal wiring layer 104 and an insulating protective layer 105 sequentially stacked on the surface of the wiring substrate, and a functional device (Fig. 49) and a microchip (not shown in FIG. 49).
  • the second metal wiring layer 104 is located on the side of the insulating material layer 103 away from the base substrate 101 , and is connected to the first metal wiring layer 102 through vias on the insulating material layer 103 . It can be understood that, in some embodiments, some vias on the insulating material layer 103 are not used for connecting the first metal wiring layer 102 and the second metal wiring layer 104 , and are filled with the insulating protection layer 105 . In other words, in an array substrate, at least part of the via holes on the insulating material layer 103 can be filled with the insulating protective layer 105 .
  • the second metal wiring layer 104 may include a second metal adhesion layer and a second copper metal layer stacked in sequence, and the second metal adhesion layer is used to enhance the bonding between the second copper metal layer and the planarized organic material layer 1032 Force;
  • the material of the second metal adhesion layer can be an alloy material containing molybdenum, such as molybdenum-niobium alloy, molybdenum-niobium-copper alloy, and the like.
  • the second metal wiring layer 104 may further include a second metal protection layer located on the side of the second copper metal layer away from the base substrate 101, so as to prevent the surface of the second copper metal layer from being oxidized, and for improving functional devices and performance.
  • the bonding force between the microchip and the second metal wiring layer 104 The material of the second metal protective layer can be an alloy containing nickel, for example, a copper-nickel alloy or a copper-titanium alloy.
  • the second metal wiring layer 104 may include a plurality of device pad groups for bonding functional devices, a plurality of chip pad groups for bonding microchips, and a plurality of connection leads 500 .
  • the functional device is bound and connected to the device pad group
  • the microchip is bound and connected to the chip pad group
  • the device pad group and the chip pad group are connected to the connecting lead 500 .
  • At least part of the connection lead 500 is connected to the first metal wiring layer 102 through at least part of the via hole provided on the insulating material layer 103 .
  • connection leads 500 may extend along the second direction D, or at least part of the connection leads 500 may extend along the second direction D, so as to reduce the overlapping length between part of the connection lead 500 and part of the drive lead and reduce insulation
  • the local failure of the material layer 103 creates a risk of poor short circuits.
  • at least part of the lead segments of the connecting leads 500 may extend along the second direction D, and the rest The lead segments may extend in the first direction.
  • the connecting leads electrically connected to the first input lead or the second input lead may extend in the second direction without being bent, so that these connecting leads 500
  • the extending direction is perpendicular to the extending direction of the driving lead, so that the overlapping length between these connecting leads and the reference voltage lead can be reduced, and the risk of short circuit failure can be reduced.
  • the connection lead connected to the first input lead or the second input lead may extend along the second direction to overlap the input lead. position, then bend and continue in the first direction to the input via overlap.
  • connection leads 500 extending in the second direction and the reference voltage lead have a relatively small overlapping length, so that the short-circuit defect that raises the array substrate can be avoided.
  • the lead segments of these connecting leads extending in the first direction can overlap with the first input lead or the second input lead, so even if a short circuit occurs, it will not cause a change in the potential on these connecting leads, that is, there will be no short-circuit failure. .
  • the insulating protection layer 105 may include an organic protection layer 1052, and the organic protection layer 1052 may include an organic insulating material, for example, may contain a resin material.
  • the organic protective layer 1052 may also contain inorganic materials, such as inorganic particles dispersed in resin.
  • the organic protective layer 1052 may be an organic-inorganic composite layer formed by cross-linking and curing of an acrylic monomer dispersed with nano titanium oxide particles.
  • the insulating protection layer 105 may further include a second passivation layer 1051 located between the organic protection layer 1052 and the second metal wiring layer 104 .
  • the second passivation layer 1051 is used to protect the second metal wiring layer 104, and its material may be an inorganic dielectric material, such as silicon nitride, silicon oxide or silicon oxynitride. In one embodiment of the present disclosure, the material of the second passivation layer 1051 may be silicon nitride.
  • the insulating protection layer 105 may have via holes exposing each sub-pad of the device pad group and each sub-pad of the chip pad group, so as to bond and connect the functional device and the microchip on the array substrate.
  • the array substrate may be bound with functional devices and a microchip, and the microchip is used to control each functional device.
  • the functional device can be a current-driven element, such as a heating element, a light-emitting element, a sound-emitting element, etc., or an electronic element that realizes a sensing function, such as a photosensitive element, a thermal element, and the like.
  • the functional device may be a light-emitting element, such as a Micro LED or a Mini LED.
  • part of the functional devices may be light-emitting elements, and another part of the functional devices may be sensors, for example, electronic components such as temperature sensors, pressure sensors, and infrared sensors.
  • the wiring substrate provided by the present disclosure has a plurality of control regions 201 distributed in an array, and the plurality of control regions 201 are arranged into a plurality of control region rows 210 and a plurality of control regions Column 220.
  • Any control area column 220 includes a plurality of control areas 201 arranged along the first direction C, and any control area row 210 includes a plurality of control areas 201 arranged along the second direction D; the second direction D is parallel to the plane where the wiring substrate is located and intersects with the first direction C.
  • the included angle between the second direction D and the first direction C may be 85° ⁇ 90°.
  • the second direction D is perpendicular to the first direction C.
  • any one of the control regions 201 includes four device regions A distributed in an array, and the device regions A are used to set the functional devices 107 that are electrically connected to each other.
  • one device area A may be provided with a device control circuit, and the device control circuit includes one functional device or a plurality of electrically connected functional devices.
  • one control circuit may include four light-emitting elements connected in series in sequence.
  • the device control circuit may include connection leads 500 on the second metal wiring layer 104 and a device pad group P50 corresponding to a functional device (not shown in FIG. 47 ).
  • the device pad group P50 is connected to The leads 500 are connected and bonded to the functional device.
  • one device pad group P50 includes a first device sub-pad P51 and a second device sub-pad P52 arranged in pairs, the first device sub-pad P51 and the first device sub-pad The two device sub-pads P52 are respectively used for binding connection with the positive and negative electrodes of the light-emitting element.
  • each device area A on the wiring substrate may be distributed in an array. Wherein, 2*2 adjacent four device regions A may constitute one control region 201 of the present disclosure.
  • four device regions A may be numbered as the first device region A(1, 1), the second device region A(1, 1) 2), the third device area A(2,1), and the fourth device area A(2,2).
  • the first device region A(1,1) is the device region A located in the first row in the first direction C and in the first column in the second direction D in the control region 201;
  • the second device region A(1,1) 2) is the device area A located in the first row in the first direction C and in the second column in the second direction D in the control area 201;
  • the third device area A(2,1) is in the first direction in the control area 201
  • the device area A is located in the second row on C and located in the first column in the second direction D;
  • the fourth device area A(2, 2) is located in the second row in the first direction C in the control area 201, in the second The device region A in the second column in the direction D.
  • the first metal wiring layer 102 is provided with the driving leads 300 extending along the first direction C.
  • the driving lead 300 at least includes a first power supply voltage lead 310, a first input lead 320, a reference voltage lead 330, a second input lead 340, and a second input lead 310, which are sequentially arranged along the second direction D.
  • Supply voltage lead 350 .
  • the wiring substrate also has at least one signal channel extending along the first direction C, and any one of the signal channels includes at least one control area column 220; in any one of the signal channels, the driving lead 300 further includes at least one address lead 360. In some embodiments, one signal channel includes one control area column 220 .
  • the first power supply voltage lead 310 and the second power supply voltage lead 350 may be power supply voltage leads of the wiring substrate and the array substrate; the first input lead 320 and the second input lead 340 may be the input leads of the wiring substrate and the array substrate.
  • the insulating material layer 103 may be provided with power vias exposing a partial area of the power supply voltage lead (the first power supply voltage lead 310 or the second power supply voltage lead 350 ), so that one end of the device control circuit is connected to the power supply voltage lead through the power supply via hole.
  • the insulating material layer 103 may be provided with a reference via hole exposing a partial area of the reference voltage lead 330, and the reference voltage lead 330 supplies power to the reference voltage pin of the microchip through the reference via hole.
  • the insulating material layer 103 may be provided with input vias exposing a partial area of the input lead (the first input lead 320 or the second input lead 340 ), so that part of the pins of the microchip are connected to the input leads through the input vias.
  • the control area 201 may include a first control area 2011 .
  • the insulating material layer 103 is provided with first to sixth power supply vias, first to fourth input vias, a first reference via HR1 and a second reference via HR2.
  • the first power supply via HV1 , the second power supply via HV2 and the third power supply via HV3 are sequentially arranged along the first direction C and expose portions of the first power supply voltage lead 310 area;
  • the first power supply via HV1 is located on the side of the first device region A(1,1) away from the third device region A(2,1) or located in the first device region A(1,1) and the third device region Between A(2,1);
  • the second power supply via HV2 is located between the first device area A(1,1) and the third device area A(2,1);
  • the third power supply via HV3 is located in the third device The area A(2,1) is away from the side of the first device area A(1,1).
  • the fourth power via HV4 , the fifth power via HV5 and the sixth power via HV6 are sequentially arranged along the first direction C and expose a partial region of the second power supply voltage lead 350 .
  • the fourth power supply via HV4 is located on the side of the second device region A(1,2) away from the fourth device region A(2,2) or located in the second device region A(1,2) and the fourth device region A( 2,2);
  • the fifth power supply via HV5 is located between the second device region A(1,2) and the fourth device region A(2,2);
  • the sixth power supply via HV6 is located in the fourth device region A (2,2) A side away from the second device region A (1,2).
  • the specific positions of the first power supply via HV1 and the fourth power supply via HV4 may be determined in advance according to the arrangement of the device control circuit in the device area A.
  • the device control circuit in the device area A may have a first end and a second end, wherein the second end is used for electrical connection with the microchip, and the first end is used for connection with the power supply voltage lead through the connecting lead overlapping the power supply via .
  • the first end of the device control circuit can be close to a top corner of the device region, and the top corner is located in the device region away from the reference voltage lead in the second direction side.
  • the first power supply via HV1 may be located on the side close to the third device area A(2,1), and the fourth power via HV4 may be located in the second device area A(1,2) close to the fourth device area One side of A(2,2).
  • the first power source may be located on the side of the first device region A(1,1) away from the third device region A(2,1), and the fourth power supply via HV4 may be located in the second device region A(1,2) away from the first device region A(1,2).
  • the device area A is provided with N*N functional devices 107 arranged in an array and connected in series.
  • N is an even number not less than 2
  • the first power via HV1 may be located on the side of the first device region A(1,1) close to the third device region A(2,1)
  • the fourth power via HV4 may be It is located on the side of the second device region A(1, 2) close to the fourth device region A(2, 2).
  • N is an odd number not less than 2
  • the first power supply via HV1 may be located on the side of the first device region A(1,1) away from the third device region A(2,1)
  • the fourth power supply via HV4 may be It is located on the side of the second device region A(1, 2) away from the fourth device region A(2, 2).
  • connection leads 500 in the first device area A(1, 1) and the second device area A(1, 2) can be simplified as much as possible. It can be understood that since the second power supply via HV2 and the third power supply via HV3 are located on both sides of the third device area A(2,1), the device control circuit in the third device area A(2,1) It may be connected to one of the second power via HV2 and the third power via HV3 according to the wiring requirements of the connection lead 500 .
  • the device control circuit in the fourth device area A(2,2) can be controlled according to The wiring of the connection lead 500 is required to connect to one of the fifth power supply via HV5 and the sixth power supply via HV6.
  • the wiring substrate of the present disclosure is provided with two first power supply vias HV1 and two fourth power supply vias HV4 in the first control region 2011 .
  • the two first power supply vias HV1 are respectively located on both sides of the first device area A(1,1)
  • the two fourth power supply vias HV4 are respectively located on both sides of the second device area A(1,2).
  • the array substrate can select one of the first power supply vias HV1 to realize the connection between the device control circuit in the first device area A(1,1) and the first power supply voltage lead 310
  • one of the fourth power supply vias HV4 is selected to realize the electrical connection between the device control circuit in the second device area A(1, 2) and the fifth power supply voltage lead 350 .
  • the first input via HI1 and the second input via HI2 expose a partial area of the first input lead 320; the first input via HI1 is located in the first device area A(1,1) away from the third device area A(2,1 ) and the edge of the third device area A(2,1) close to the first device area A(1,1); the second input via HI2 is located in the third device area A(2,1) away from the first One side of device area A(1,1).
  • the third input via HI3 and the fourth input via HI4 expose partial regions of the second input lead 340 .
  • the third input via HI3 is located at the edge of the second device area A(1, 2) away from the fourth device area A(2, 2) and the fourth device area A(2, 2) is close to the second device area A(1, 2) 2); the fourth input via HI4 is located on the side of the fourth device area A(2, 2) away from the second device area A(1, 2).
  • Both the first reference via hole HR1 and the second reference via hole HR2 expose a partial area of the reference voltage lead 330; along the first direction C, the first reference via hole HR1 is located in the first device region A(1,1) and the third device Between the regions A(2,1), the second reference via HR2 is located on the side of the third device region A(2,1) away from the first device region A(1,1).
  • the insulating material layer 103 is further provided with at least one address via hole exposing a partial region of the address lead 360 .
  • the wiring substrate may further have a fan-out area and a binding area B, wherein the first metal wiring layer 102 is provided with fan-out leads 400 connected to each drive lead 300 in a one-to-one correspondence in the fan-out area , the bonding area B is provided with bonding pads connected with each fan-out lead 400 in a one-to-one correspondence.
  • the fan-out leads 400 and the bonding pads are located on the side of the first direction C of the corresponding driving leads 300 ; that is, along the first direction C, the bonding area B is located at the end of the wiring board.
  • the driving leads are located on the first direction C side of the corresponding fan-out leads and the bonding pads; that is, along the first direction C, the bonding area B is located at the starting end of the wiring substrate .
  • the bonding area B may be disposed close to an edge of the wiring substrate, for example, an edge of the wiring substrate in the first direction C or an edge in the opposite direction of the first direction C.
  • the wiring substrate and the array substrate of the present disclosure may be provided with at least one row of bonding pads in the bonding area B. Further, in the same row of bonding pads, each bonding pad may be arranged along the second direction D. In one embodiment of the present disclosure, each bonding pad is arranged in a row along the second direction D, and is provided in a one-to-one correspondence with each driving lead 300 .
  • two bonding pads correspondingly connected to two adjacent power supply voltage leads in two adjacent signal channels are connected to each other as a whole.
  • the two fan-out leads 400 connected to two adjacent power supply voltage leads can also be connected to each other to form a whole. In this way, it is equivalent that two adjacent power supply voltage leads are connected to the same bonding pad through the same fan-out lead 400 .
  • the binding area is provided with a plurality of binding electrodes arranged at equal intervals along the second direction D, and each binding electrode has the same width.
  • One or more adjacent bond electrodes may be connected to the same fan-out lead as a whole as a bond pad to which the bond lead is connected. When a bonding pad includes a larger number of bonding electrodes, the width of the bonding pad is larger.
  • the wiring substrate provided by the present disclosure can be applied to at least two different microchips to prepare different array substrates with different microchips.
  • These array substrates include the wiring substrate provided by the present disclosure, the second metal wiring layer 104 and the insulating protective layer 105 on the side of the insulating material layer 103 stacked on the wiring substrate away from the base substrate 101 , and are also bound with microchips and functions device.
  • one of the second power supply via HV2 and the third power supply via HV3 is used to overlap the connection lead 500, so that The device control circuit in the third device region A( 2 , 1 ) is connected to the first power supply voltage lead 310 ;
  • One of the fifth power supply via HV5 and the sixth power supply via HV6 is used to overlap the connection lead 500 so that the device control circuit in the fourth device region A(2, 2) is connected to the second power supply voltage lead 350 ; the other may not overlap with any second metal wiring layer 104 and be filled with the insulating protective layer 105 .
  • the wiring substrate provided by the present disclosure can be used to prepare an array substrate having a first chip, for example, can be used to prepare a first array substrate.
  • the base substrate 101 , the first metal wiring layer 102 and the insulating material layer 103 of the first array substrate form the wiring substrate in this embodiment.
  • FIG. 11 shows a schematic structural diagram of a first array substrate in a first control area 2011 ; wherein, FIG. 11 only shows the positions and connections of the drive leads 300 and at least part of the via holes provided in the insulating material layer 103 .
  • Wires 500 (indicated by thick lines), the first pad group P10 for bonding the first chip, the functional devices 107 in each device area A, and the like.
  • the first array substrate may be provided with four first pad groups P10 corresponding to the four device areas A one-to-one; any one of the first pad groups P10 is located corresponding to the first direction C side of the device region A.
  • the first pad group P10 corresponding to the second device region A(1,2) is located on the side of the second direction D of the first pad group P10 corresponding to the first device region A(1,1); the fourth device region A
  • the first pad group P10 corresponding to (2, 2) is located on the second direction D side of the first pad group P10 corresponding to the third device region A (2, 1).
  • the reference voltage sub-pads P11 of the first pad group P10 corresponding to the first device region A(1,1) and the second device region A(1,2) are connected through the connection lead 500 overlapping the first reference via hole HR1.
  • the reference voltage sub-pads P11 of the first pad group P10 corresponding to the third device area A(2, 1) and the reference voltage sub-pads of the first pad group P10 corresponding to the fourth device area A(2, 2) P11 and the reference voltage lead 330 are connected through the connection lead 500 overlapping the second reference via hole HR2. This can make the reference voltage sub-pads P11 of each of the first pad groups P10 electrically connected to the reference voltage lead 330 .
  • the connection lead 500 overlapping the first reference via hole HR1 and the connection lead 500 overlapping the second reference via hole HR2 are in the first metal None of the orthographic projections on the wiring layer 102 exceed the range of the reference voltage lead 330 . In this way, even if a layout failure of the insulating material layer 103 occurs and the connection leads 500 and the reference voltage leads 330 are short-circuited, the voltage on these leads will not be changed to cause defects.
  • each device area A may be numbered in sequence, wherein the first pad group P10 corresponding to the device area A numbered 1 may be located at one end of the signal channel in its extension direction, for example, it may be It is located at the end close to the binding area B or at the end away from the binding area B.
  • the first pad groups P10 corresponding to each device area A can be numbered row by row and column by row according to Z shape, or numbered row by column according to S shape, or numbered row by column according to N shape. , or in U-shape or inverted U-shape column by column and row by row.
  • the row direction is the direction along the second direction D or the opposite direction thereof
  • the column direction is the direction along the first direction C or the opposite direction thereof.
  • the first pad group P10 corresponding to each device area A can be cascaded in sequence according to the numbering sequence, wherein the second input sub-pad P14 of the first pad group P10 corresponding to the device area A numbered 1 It is connected with one of the address leads 360 through the connection lead 50 overlapping with the address via hole.
  • the output sub-pad P12 of the first pad group P10 corresponding to the device area A numbered (n-1) passes through the second input sub-pad P14 of the first pad group P10 corresponding to the device area A numbered n Connection leads 500 are connected.
  • n is an integer greater than 1 and not greater than the number of device regions in one signal channel.
  • the first pad group P10 corresponding to the first device area A(1,1) and the first pad group P10 corresponding to the second device area A(1,2) are cascaded in sequence.
  • the output sub-pad P12 of the first pad group P10 corresponding to the first device area A(1,1) and the second input sub-pad P10 of the first pad group P10 corresponding to the second device area A(1,2) The pads P14 are connected, and the output sub-pads P12 of the first pad group P10 corresponding to the second device region A(1, 2) are connected to the output sub-pads P12 of the first pad group P10 corresponding to the third device region A(2, 1).
  • the two input sub-pads P14 are connected, and the output sub-pads P12 of the first pad group P10 corresponding to the third device region A(2,1) are connected to the first pad group corresponding to the fourth device region A(2,2).
  • the second input subpad P14 of P10 is connected.
  • the output sub-pad P12 of the first pad group P10 corresponding to the fourth device region A(2, 2) of the control region 201 on the opposite side of the first direction C which is connected to the second input sub-pad P14 of the first pad group P10 corresponding to the first device region A(1, 1) of the control region 201 on the side of the first direction C.
  • the first array substrate is provided with a device control circuit in the device area A, wherein the first end of the device control circuit and the power supply voltage lead are connected through the connection lead 500 overlapping the power supply via; the device control circuit
  • the second end of the device area A is connected with the output sub-pad P12 of the first pad group P10 corresponding to the device area A through the connecting lead 500 .
  • the first end of the device control circuit may be the first device sub-pad P51 in one device pad group P50 on the supply voltage lead, and the second end of the device control circuit may be in the first direction C A second device sub-pad P52 in one device pad group P50 that is close to the corresponding first chip 010 and close to the axis of the reference voltage lead 330 in the second direction D.
  • the length of the connection lead 500 between the output pin 012 of the first chip 010 and the second end of the device control circuit can be reduced as much as possible, and the overlapping length between the connection lead 500 and the reference voltage lead 330 can be reduced, and further The risk of bad short circuits between these connection leads 500 and the reference voltage lead 330 is reduced.
  • four light-emitting elements in series and distributed in a 2*2 array are arranged in one device area A; wherein, the first light-emitting element and the power supply voltage lead are connected through The connecting lead 500 overlapping with the power supply via is connected, and the fourth light-emitting element is connected to the output sub-pad P12 of the first pad group P10 through the connecting lead 500 .
  • the three connecting leads 500 connecting the four light-emitting elements in series are distributed in a zigzag shape with the openings facing the first direction C as a whole.
  • the first power via HV1 may be disposed on the side of the first direction C of the first device area A(1,1), and the fourth power via HV4 may be disposed in The first direction C side of the second device region A(1, 2).
  • the first end of the device control circuit in the first device area A(1, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the first power supply via HV1.
  • the first end of the device control circuit in the second device area A(1, 2) and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the fourth power supply via HV4.
  • the first end of the device control circuit in the third device area A(2, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the third power supply via HV3.
  • the first end of the device control circuit in the fourth device area A(2, 2) is connected to the second power supply voltage lead 350 through the connection lead 500 overlapping the sixth power supply via HV6.
  • connection leads 500 of HI1 are connected; between the first input sub-pad P13 of the first pad group P10 corresponding to the third device area A(2,1) and the first input lead 320, through the connection with the second input sub-pad P13
  • the connection lead 500 overlapped by the hole HI2 is connected; between the first input sub-pad P13 of the first pad group P10 corresponding to the second device area A(1, 2) and the second input lead 340, through the connection with the third input sub-pad P13
  • the connection lead 500 overlapped by the via hole HI3 is connected; the connection between the first input sub-pad P13 and the second input lead 340 of the first pad group P10 corresponding to the fourth device area A(2, 2) is connected to the fourth device area A(2,2).
  • the connecting leads 500 overlapping the input vias HI4 are connected.
  • the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driving device control circuit, for example, to load the power supply voltage VLED of each light emitting element in the driving device control circuit to emit light.
  • the reference voltage lead 330 may be used to load the reference voltage GND.
  • One of the first input lead 320 and the second input lead 340 may be used to load the first input signal Pwr.
  • at least one address pin 360 may be used to load the second input signal Di. In this way, under the control of each driving lead 300, each of the first chips 010 and the functional device 107 can work normally.
  • the input lead is provided with a direction toward the reference voltage lead 330 .
  • a protruding portion 301 protruding on one side, and the reference voltage lead 330 is provided with an accommodating notch 302 corresponding to the protruding portion 301 of the reference voltage lead 330 and capable of accommodating the protruding portion 301 .
  • the first pad group P10 may be disposed close to the protruding portion 301 , so that the first input sub-pad P13 of the first pad group P10 is on the first metal wiring layer 102
  • the projection is located on the protrusion 301 of the input lead, and the orthographic projection of the reference voltage sub-pad P11 of the first pad group P10 on the first metal wiring layer 102 is located on the reference voltage lead 330 .
  • At least part of the protruding part 301 of the input lead may serve as the first supporting metal part 303, and the first supporting metal part 303 may completely overlap the input sub-pad of the first pad group P10;
  • the reference voltage At least a part of the lead 330 close to the accommodating notch 302 can serve as the second supporting metal part 304 , and the second supporting metal part 304 can completely overlap with the reference voltage sub-pad P11 of the first pad group P10 .
  • the connection lead 500 connected to the reference voltage sub-pad P11 and overlapping with the reference via hole may completely overlap the reference voltage lead 330 . In this way, the risk of short circuit failure caused by the insulation failure of the insulating material layer 103 is further reduced.
  • the first metal wiring layer 102 may further be provided with a third support metal part 305 and a fourth support metal part 306 , and both the third support metal part 305 and the fourth support metal part 306 are It is located between the input lead and the reference voltage lead 330 and is insulated from the input lead and the reference voltage lead 330 .
  • the orthographic projection of the third supporting metal portion 305 on the base substrate 101 coincides with the orthographic projection of the output sub-pad P12 on the base substrate 101 ; the orthographic projection of the second supporting metal portion 304 on the base substrate 101 , which coincides with the orthographic projection of the second input sub-pad P14 on the base substrate 101 . In this way, the distances between each sub-pad of the first pad group P10 and the base substrate 101 can be made substantially the same, which is beneficial to the bonding of the first chip 010 .
  • the wiring substrate provided by the present disclosure can also be used to prepare an array substrate having the second chip 020, for example, can be used to prepare a second array substrate.
  • the base substrate 101 , the first metal wiring layer 102 and the insulating material layer 103 of the second array substrate form the wiring substrate in this embodiment.
  • FIG. 12 shows a schematic structural diagram of a second array substrate in a first control area 2011; wherein, FIG. 12 only shows the positions of the driving leads 300, the via holes provided in the insulating material layer 103, and the connection leads 500 (indicated by thick lines), the second pad group P20 for bonding the second chip 020, the functional devices 107 in each device area A, and the like.
  • the second array substrate may be provided with a second pad group P20 for binding the second chip 020 in a first control area 2011 , and the second pad group P20 may be located in the first control area 2011 between the four device regions A within.
  • the second pad group P20 in a first control region 2011, along the first direction C, the second pad group P20 is located between the first device region A(1,1) and the third device region A(2,1); In the second direction D, the second pad group P20 is located between the first device region A(1,1) and the second device region A(1,2).
  • the reference voltage sub-pad P21 of the second pad group P20 is located on the first direction C side of the address sub-pad P25 of the second pad group P20 to ensure the reference voltage sub-pad of the second pad group P20
  • the connection lead 500 connected to the pad P21 can extend to overlap the second reference via hole HR2 , and the connection lead 500 completely overlaps the reference voltage lead 330 . In this way, when the connection lead 500 and the reference voltage lead 330 are short-circuited, the second array substrate can avoid defects.
  • one of the chip power supply sub-pad P23 and the driving data sub-pad P24 is connected with the first input lead 320 through the connection lead 500 overlapping the first input via HI1; the other is connected with the second input lead 340 is connected through the connecting lead 500 overlapping the third input via HI3.
  • the four input sub-pads are respectively connected to the second ends of the device control circuits in the four device regions through connecting leads 500 .
  • the chip power sub-pads P23 of the second pad group P20 are located on the opposite side of the second direction D of the driving data sub-pads P24 .
  • the chip power supply sub-pad P23 of the second pad group P20 and the first input lead 320 can be connected through the connecting lead 500 for overlapping the first input via HI1; the driving of the second pad group P20
  • the connection lead 500 for overlapping the third input via HI3 may be connected.
  • the address sub-pad P25 of the second pad group P20 and the address wire 360 may be connected through the connection wire 500 overlapping with the address via hole.
  • connection lead 500 The first end of the device control circuit in the second device area A(1, 2) and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the fourth power supply via HV4; the second device area A
  • connection lead 500 overlapping the second power supply via HV2 or the third power supply via HV3 passes through Connection:
  • the connection between the second end of the device control circuit in the third device area A(2, 1) and the third output sub-pad P223 of the second pad group P20 is connected through the connection lead 500 .
  • connection lead 500 overlapping the fifth power supply via HV5 or the sixth power supply via HV6 Connection:
  • the connection between the second end of the device control circuit in the fourth device area A(2, 2) and the fourth output sub-pad P224 of the second pad group P20 is connected through the connection lead 500 .
  • the first end of the device control circuit may be a sub-pad in a device pad group P50 located on the power supply voltage lead, and the second end of the device control circuit may be close to the second chip 020 in the first direction C And one sub-pad in one device pad group P50 in the second direction D is close to the axis of the reference voltage lead 330 .
  • connection lead 500 can minimize the length of the connection lead 500 between the output pin 012 of the second chip 020 and the second end of the device control circuit, reduce the overlapping length between these connection leads 500 and the reference voltage lead 330, and further reduce these There is a risk of poor short circuit between the connection lead 500 and the reference voltage lead 330 .
  • the device control circuit in the first device area A(1,1) has connection leads connecting various functional devices, and the device control circuit in the third device area A(2,1) There are connection leads connecting each functional device, and the connection leads in the first device area A(1,1) are symmetrical with the connection leads in the third device area A(2,1) about an axis of symmetry, and the axis of symmetry is parallel in the second direction.
  • the device control circuit in the second device area A(1, 2) has connecting leads connecting various functional devices
  • the device control circuit in the fourth device area A(2, 2) has connecting leads connecting each functional device
  • the second The connection leads of the device area A(1, 2) are symmetrical with the connection leads in the fourth device area A(2, 2) about an axis of symmetry, and the axis of symmetry is parallel to the second direction.
  • four light-emitting elements in series and distributed in a 2*2 array are arranged in one device area A; wherein, between the first light-emitting element and the power supply voltage lead, The fourth light emitting element is connected to the output sub-pad P12 of the second pad group P20 through the connection lead 500 .
  • the three connecting leads 500 of the four light-emitting elements in series are distributed in a zigzag shape with the opening facing the first direction C as a whole. .
  • the three connecting leads 500 of the four light-emitting elements in series are in the opposite direction of the opening toward the first direction C as a whole. font distribution.
  • the first power via HV1 may be disposed on the side of the first direction C of the first device area A(1,1)
  • the fourth power via HV4 may be disposed in The first direction C side of the second device region A(1, 2).
  • the first end of the device control circuit in the first device area A(1, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the first power supply via HV1.
  • the first end of the device control circuit in the third device area A(2, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the second power supply via HV2.
  • the first end of the device control circuit in the second device area A(1, 2) and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the fourth power supply via HV4.
  • the first end of the device control circuit in the fourth device area A(2, 2) is connected to the second power supply voltage lead 350 through the connection lead 500 overlapping the fifth power supply via HV5.
  • the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driving device control circuit, for example, to load the power supply voltage VLED of each light emitting element in the driving device control circuit to emit light.
  • the reference voltage lead 330 may be used to load the reference voltage GND.
  • the first input lead 320 can be used to load the chip working voltage VCC, and the second input lead 340 can be used to load the driving data Data. At least a portion of address leads 360 may be used to load strobe signals. In this way, each second chip 020 and the functional device 107 can work normally under the control of each driving lead 300 .
  • the first reference via HR1 , the second input via HI2 , and the fourth input via HI4 may not overlap with any second metal wiring layer 104 , and is filled with the insulating protective layer 105 .
  • the wiring substrate provided by the present disclosure can be used to prepare an array substrate having the third chip 030, for example, can be used to prepare a third array substrate.
  • the base substrate 101 , the first metal wiring layer 102 and the insulating material layer 103 of the third array substrate form the wiring substrate in this embodiment.
  • FIG. 13 shows a schematic structural diagram of a third array substrate in a first control area 2011 ; wherein, FIG. 13 only shows the driving leads 300 and the via holes provided in the insulating material layer 103 .
  • connection lead 500 (indicated by a thick line), third pad group P30 for bonding the third chip 030, functional device 107 in each device area A, and the like.
  • the third array substrate may be provided with a third pad group P30 for binding the third chip 030 in a first control area 2011 , and the third pad group P30 may be located in the first control area 2011 between the four device regions A within.
  • the third pad group P30 in a first control region 2011, along the first direction C, is located between the first device region A(1,1) and the third device region A(2,1); In the second direction D, the third pad group P30 is located between the first device region A(1,1) and the second device region A(1,2).
  • the reference voltage sub-pad P31 of the third pad group P30 is located on the first direction C side of the relay signal sub-pad P36 of the third pad group P30, which is more conducive to the
  • the connection lead 500 connected to the reference voltage sub-pad P31 extends to overlap with the second reference via hole HR2 , and the connection lead 500 completely overlaps with the reference voltage lead 330 . In this way, when the connection lead 500 and the reference voltage lead 330 are short-circuited, the third array substrate can avoid defects.
  • the reference voltage sub-pad P31 and the reference voltage lead 330 can be connected through the connection lead 500 overlapping the second reference via HR2; the chip power sub-pad P33
  • One of the driving data sub-pads P34 is connected to the first input lead 320 through the connection lead 500 overlapping the first input via HI1, and the other is connected to the second input lead 340 through the third input lead 340.
  • the connection leads 500 where the holes HI3 overlap are connected.
  • the chip power sub-pads P33 of the third pad group P30 are located on the opposite side of the second direction D of the driving data sub-pads P34. In this way, the chip power sub-pad P33 of the third pad group P30 and the first input lead 320 are connected through the connection lead 500 overlapping the first input via HI1.
  • the driving data sub-pad P34 of the third pad group P30 and the second input lead 340 are connected through the connection lead 500 overlapping the third input via HI3.
  • connection lead 500 overlapped by a power supply via HV1 is connected; the second end of the device control circuit in the first device area A(1,1) is connected to the first output sub-pad of the third pad group P30 through the connection lead 500 P321 connection.
  • the first end of the device control circuit in the second device area A(1, 2) and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the fourth power supply via HV4; the second device area A
  • the second end of the device control circuit in (1, 2) is connected to the second output sub-pad P322 of the third pad group P30 through the connection lead 500 .
  • the connection lead 500 is connected; the second end of the device control circuit in the third device area A(2,1) is connected to the third output sub-pad P323 of the third pad group P30 through the connection lead 500 .
  • the connection lead 500 is connected; the second end of the device control circuit in the fourth device area A(2, 2) is connected to the fourth output sub-pad P324 of the third pad group P30 through the connection lead 500 .
  • the first end of the device control circuit may be a sub-pad in a device pad group P50 located on the power supply voltage lead, and the second end of the device control circuit may be close to the third chip 030 in the first direction C And one sub-pad in one device pad group P50 in the second direction D is close to the axis of the reference voltage lead 330 .
  • connection lead 500 can minimize the length of the connection lead 500 between the output pin of the third chip 030 and the second end of the device control circuit, reduce the overlapping length between these connection leads 500 and the reference voltage lead 330, and further reduce these connections There is a risk of poor short circuit between lead 500 and reference voltage lead 330 .
  • the device control circuit in the first device area A(1,1) has connection leads connecting various functional devices, and the device control circuit in the third device area A(2,1) There are connection leads connecting each functional device, and the connection leads in the first device area A(1,1) are symmetrical with the connection leads in the third device area A(2,1) about an axis of symmetry, and the axis of symmetry is parallel in the second direction.
  • the device control circuit in the second device area A(1, 2) has connecting leads connecting various functional devices
  • the device control circuit in the fourth device area A(2, 2) has connecting leads connecting each functional device
  • the second The connection leads of the device area A(1, 2) are symmetrical with the connection leads in the fourth device area A(2, 2) about an axis of symmetry, and the axis of symmetry is parallel to the second direction.
  • the connecting leads 500 overlapping with the power supply vias are connected; the fourth light-emitting element is connected to the output sub-pads of the third pad group P30 through the connecting leads 500 .
  • the three connecting leads 500 of the four light-emitting elements in series are distributed in a zigzag shape with the opening facing the first direction C as a whole. .
  • the three connecting leads 500 of the four light-emitting elements in series are in the opposite direction of the opening toward the first direction C as a whole. font distribution.
  • the first power via HV1 may be disposed on the side of the first direction C of the first device area A(1,1)
  • the fourth power via HV4 may be disposed in The first direction C side of the second device region A(1, 2).
  • the first end of the device control circuit in the first device area A(1, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the first power supply via HV1.
  • the first end of the device control circuit in the third device area A(2, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the first power supply via HV2.
  • the first end of the device control circuit in the second device area A(1, 2) and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the fourth power supply via HV4.
  • the first end of the device control circuit in the fourth device area A(2, 2) is connected to the second power supply voltage lead 350 through the connection lead 500 overlapping the fifth power supply via HV5.
  • each control area 201 may be numbered sequentially, wherein, the control area 201 numbered 1 may be located at one end of the signal channel in its extending direction, for example, may be located close to the binding area B or the end far from the binding area B.
  • each control area 201 may be numbered sequentially along the first direction C or the opposite direction of the first direction C.
  • each control area 201 may be numbered row by row and column by column in Z shape, or numbered row by column in S shape, or numbered row by column in N shape.
  • the numbers are sequentially numbered column by column and row by row, or numbered column by column and row by row in a U-shape or inverted U-shape.
  • the third pad groups P30 in each control area 201 can be cascaded in sequence according to the numbering sequence of the control areas 201 , wherein the strobe communication of the third pad group P30 in the control area 201 numbered 1
  • the number sub-pad P35 and the address lead 360 are connected through the connection lead 500 overlapping with the address via hole.
  • the relay signal sub-pad P36 of the third pad group P30 in the control area 201 numbered (n-1) and the gate signal sub-pad of the third pad group P30 in the control area 201 numbered n P35 is connected by connecting lead 500 .
  • n is a positive integer greater than 1 and not greater than the number of control regions in one signal channel.
  • the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driving device control circuit, for example, to load the power supply voltage VLED of each light-emitting element in the driving device control circuit to emit light .
  • the reference voltage lead 330 may be used to load the reference voltage GND.
  • the first input lead 320 can be used to load the chip working voltage VCC, and the second input lead 340 can be used to load the driving data Data.
  • the address lead 360 connected to the third pad group P30 of the first-level control region 201 can be loaded with a strobe signal. In this way, under the control of each driving lead 300, each third chip 030 and the functional device 107 can work normally.
  • the first reference via HR1, the second input via HI2, and the fourth input via HI4 may not overlap with any second metal wiring layer 104 , and is filled with the insulating protective layer 105 .
  • the wiring substrate provided by the present disclosure can also be used to prepare an array substrate having a fourth chip 040, for example, can be used to prepare a fourth array substrate.
  • the base substrate 101 , the first metal wiring layer 102 and the insulating material layer 103 of the fourth array substrate form the wiring substrate in this embodiment.
  • FIG. 14 shows a schematic structural diagram of a fourth array substrate in a first control region 2011 ; wherein, FIG. 14 only shows the driving leads 300 and the via holes provided in the insulating material layer 103 .
  • connection lead 500 (indicated by a thick line), fourth pad group P40 for bonding the fourth chip 040, functional device 107 in each device area A, and the like.
  • the fourth array substrate may be provided with a fourth pad group P40 for binding the fourth chip 040 in a first control area 2011 , and the fourth pad group P40 may be located in the first control area 2011 between the four device regions A within.
  • the fourth pad group P40 in a first control region 2011, along the first direction C, is located between the first device region A(1,1) and the third device region A(2,1); In the second direction D, the fourth pad group P40 is located between the first device region A(1,1) and the second device region A(1,2).
  • the chip power sub-pads P43 and the driving data sub-pads P44 of the fourth pad group P40 are arranged along the second direction D or its opposite direction, so that the fourth pad group P40 has two columns of sub-pads, and each The column sub-pads have five sub-pads arranged along the first direction C.
  • This can simplify the design of the connection lead 500 of the fourth array substrate, reduce the length of the connection lead 500 and reduce the probability of short circuit between the connection lead 500 and the driving lead 300 of the first metal wiring layer 102 . Referring to FIG.
  • the reference voltage sub-pad P41 of the fourth pad group P40 is located close to the first Refer to one side of via HR1. In this way, it can be ensured that the connection lead 500 connected to the reference voltage sub-pad P41 of the fourth pad group P40 can extend to overlap with the first reference via hole HR1 or the second reference via hole HR2.
  • the first reference via HR1 is closer to the first power supply voltage lead 310 than the second power supply voltage lead 350 .
  • the fourth pad group P40 includes two columns of sub-pads, and the five sub-pads close to the first power supply voltage lead 310 are the fourth output sub-pad P424, the reference voltage sub-pad P41, and the driving data along the first direction C in sequence.
  • the sub-pad P44, the reference voltage sub-pad P41 and the second output sub-pad P422, the five sub-pads close to the second power supply voltage lead 350 are the third output sub-pad P423 and the gate signal along the first direction C in sequence.
  • the connecting lead 500 may completely overlap with the reference voltage lead 330 .
  • the reference voltage sub-pad P41 of the fourth pad group P40 that is far from the first reference via hole HR1 and the reference voltage lead 330 pass through the second reference via hole.
  • the HR2 overlapping connection leads 500 are connected.
  • the fourth chip 040 can obtain the reference voltage through a reference voltage sub-pad P41 , which can meet the working requirements of the fourth chip 040 .
  • the reference voltage sub-pad P41 close to the first reference via hole HR1 may be electrically connected to the reference voltage lead 330 .
  • the chip power sub-pad P43 and the driving data sub-pad P44 of the fourth pad group P40 close to the first input lead 320
  • the connection lead 500 overlapping the first input via HI1 is connected; between the sub-pad far from the first input lead 320 and the second input lead 340, through the The connection leads 500 of the three input vias HI3 overlap are connected. In this way, the lengths of the connection leads 500 can be minimized to reduce the risk of short circuit between the connection leads 500 and the reference voltage lead 330 .
  • the first ends of the device control circuits of the four device regions A and the power supply voltage lead are connected through the connection lead 500 overlapping the power supply via hole.
  • the second ends of the device control circuits of the four device regions A are connected to the four output sub-pads of the fourth pad group P40 through the connecting leads 500 in a one-to-one correspondence.
  • the second terminal of the device control circuit is connected to the nearest output sub-pad.
  • the first end of the device control circuit in the first device region A(1,1) is connected to the first
  • the power supply voltage leads 310 are connected through the connecting lead 500 overlapping with the first power supply via HV1;
  • the fourth output sub-pad P424 of the disk group P40 is connected.
  • connection lead 500 is connected; the second end of the device control circuit in the third device area A(2,1) is connected to the second output sub-pad P422 of the fourth pad group P40 through the connection lead 500 .
  • the first end of the device control circuit in the second device area A(1, 2) and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the fourth power supply via HV4; the second device area A
  • the second end of the device control circuit in (1, 2) is connected to the third output sub-pad P423 of the fourth pad group P40 through the connection lead 500 .
  • connection lead 500 is connected; the second end of the device control circuit in the fourth device area A(2, 2) is connected to the first output sub-pad P421 of the fourth pad group P40 through the connection lead 500 .
  • the first end of the device control circuit may be a sub-pad in a device pad group P50 located on the power supply voltage lead, and the second end of the device control circuit may be close to the fourth pad in the first direction C A sub-pad in a device pad group P50 of group P40 and close to the axis of the reference voltage lead 330 in the second direction D.
  • connection lead 500 can minimize the length of the connection lead 500 between the output pin of the fourth chip 040 and the second end of the device control circuit, reduce the overlapping length between these connection leads 500 and the reference voltage lead 330, and further reduce these There is a risk of poor short circuit between the connection lead 500 and the reference voltage lead 330 .
  • the device control circuit in the first device area A(1,1) has connection leads connecting various functional devices, and the device control circuit in the third device area A(2,1) There are connection leads connecting each functional device, and the connection leads in the first device area A(1,1) are symmetrical with the connection leads in the third device area A(2,1) about an axis of symmetry, and the axis of symmetry is parallel in the second direction.
  • the device control circuit in the second device area A(1, 2) has connecting leads connecting various functional devices
  • the device control circuit in the fourth device area A(2, 2) has connecting leads connecting each functional device
  • the second The connection leads of the device area A(1, 2) are symmetrical with the connection leads in the fourth device area A(2, 2) about an axis of symmetry, and the axis of symmetry is parallel to the second direction.
  • four light-emitting elements in series and distributed in a 2*2 array are arranged in one device area A; wherein, between the first light-emitting element and the power supply voltage lead, The fourth light emitting element is connected to the output sub-pad of the fourth pad group P40 through the connection lead 500 .
  • the three connecting leads 500 of the four light-emitting elements in series are distributed in a zigzag shape with the opening facing the first direction C as a whole. .
  • the three connecting leads 500 of the four light-emitting elements in series are in the opposite direction of the opening facing the first direction C as a whole. font distribution.
  • the first power via HV1 may be disposed on the side of the first direction C of the first device area A(1,1)
  • the fourth power via HV4 may be disposed in One side of the first direction C of the second device region A(1, 2).
  • the first end of the device control circuit in the first device area A(1, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the first power supply via HV1.
  • the first end of the device control circuit in the third device area A(2, 1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the second power supply via HV2.
  • the first end of the device control circuit in the second device area A(1, 2) is connected to the second power supply voltage lead 350 through the connection lead 500 overlapping the fourth power supply via HV4.
  • the first end of the device control circuit in the fourth device region A(2, 2) is connected to the second power supply voltage lead 350 through the connection lead 500 overlapping the fifth power supply via HV5.
  • each control area 201 may be numbered sequentially, wherein, the control area 201 numbered 1 may be located at one end of the signal channel in its extending direction, for example, may be located close to the binding area One end of B or the end located away from the binding region B.
  • each control area 201 may be numbered sequentially along the first direction C or the opposite direction of the first direction C.
  • each control area 201 may be numbered row by row and column by column in Z shape, or numbered row by column in S shape, or numbered row by column in N shape.
  • the fourth pad groups P40 in each control area 201 can be cascaded in sequence according to the numbering sequence of the control areas 201 , wherein the strobe signal of the fourth pad group P40 in the first-level control area 201
  • the sub-pad P45 and the address lead 360 are connected through the connection lead 500 overlapping with the address via hole; the relay signal sub-pad P46 of the fourth pad group P40 in the (n-1)th level control area 201 It is connected to the gate signal sub-pad P45 of the fourth pad group P40 in the n-th stage control region 201 through the connecting wire 500 .
  • the fourth array substrate can realize the mutual cascade connection of each fourth chip 040 in one signal channel, thereby realizing the control of each device control circuit in the signal channel.
  • the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driving device control circuit, for example, to load the power supply voltage VLED of each light-emitting element in the driving device control circuit to emit light .
  • the reference voltage lead 330 may be used to load the reference voltage GND.
  • one connected to the chip power supply sub-pad P43 can be used to load the chip working voltage VCC, and the other can be used to load the driving data Data.
  • the address lead 360 electrically connected to the fourth pad group P40 of the first-level control region 201 can be loaded with a strobe signal. In this way, each fourth chip 040 and the functional device 107 can work normally under the control of each driving lead 300 .
  • the second input via hole HI2 and the fourth input via hole HI4 may not overlap with any second metal wiring layer 104 and are protected by the insulating protection layer 105 filling.
  • the first power supply via HV1 and the fourth power supply via HV4 are related to the first power supply via HV1 and the fourth power supply via HV4
  • the symmetry axis is symmetrical
  • the second power supply via HV2 and the fifth power supply via HV5 are symmetrical about the second symmetry axis
  • the third power supply via HV3 and the sixth power supply via HV6 are symmetrical about the third symmetry axis.
  • the first axis of symmetry, the second axis of symmetry and the third axis of symmetry extend along the first direction C and coincide with each other. In this way, the design and preparation of the wiring substrate can be facilitated, the cost of the wiring substrate can be reduced, and the cost of each array substrate based on the wiring substrate can be further reduced.
  • the first input via HI1 and the third input via HI3 are symmetrical about the fourth axis of symmetry
  • the second input via HI2 is symmetrical with the fourth input via HI4 about the fifth axis of symmetry.
  • the fourth axis of symmetry and the fifth axis of symmetry extend along the first direction C and coincide with each other. In this way, the design and preparation of the wiring substrate can be facilitated, the cost of the wiring substrate can be reduced, and the cost of each array substrate based on the wiring substrate can be further reduced.
  • the first power supply via HV1 and the fourth power supply via HV4 are located in the first device region between A(1,1) and the first reference via hole HR1, the second power supply via hole HV2 and the fifth power supply via hole HV5 are located between the third device region A(2,1) and the first reference via hole HR1;
  • the third power supply via HV3 and the sixth power supply via HV6 are located between the third device region A(2,1) and the second reference via HR2.
  • a wiring space for the wiring of the array substrate between the first power supply via HV1 and the first reference via HR1, and the second power supply via HV2 is connected to the wiring space of the array substrate.
  • There is a wiring space for array substrate wiring between the first reference vias HR1 a wiring space for array substrate wiring exists between the fourth power supply via HV4 and the first reference via HR1, and the fifth power supply via HV5 and A wiring space for the wiring of the array substrate exists between the first reference vias HR1.
  • the array substrate may arrange the connection wires 500 extending along the second direction D in these wiring spaces, so that the overlapping lengths between these connection wires 500 and different driving wires 300 are minimized.
  • the insulating material layer 103 may further be provided with a partial region exposing the reference voltage lead 330
  • the third reference via HR3 and the first reference via HR1 are respectively located on both sides of the axis of the reference voltage lead 330
  • the fourth reference via HR4 and the second reference via HR2 are respectively located on both sides of the axis of the reference voltage lead 330 .
  • the wiring substrate is in the first control region 2011, and each device region A may have a corresponding reference via hole.
  • the first device region A(1,1) may be set corresponding to the first reference via hole HR1
  • the second device region A(1,2) may be set corresponding to the third reference via hole HR3
  • the third device region A( 2, 1) may be set corresponding to the second reference via hole HR2
  • the fourth device region A(2, 2) may be set corresponding to the fourth reference via hole HR4.
  • the third reference via HR3 and the first reference via HR1 are symmetrical with respect to the sixth axis of symmetry
  • the fourth reference via HR4 and the second reference via HR2 are symmetrical about the seventh axis of symmetry
  • the sixth axis of symmetry and the seventh axis of symmetry are The axes of symmetry extend along the first direction C and coincide with each other. In this way, the design and preparation of the wiring substrate can be facilitated, the cost of the wiring substrate can be reduced, and the cost of each array substrate based on the wiring substrate can be further reduced.
  • the wiring substrate in this embodiment can be used to prepare a fifth array substrate provided with the first chip 010 .
  • the structure of the fifth array substrate on the second metal wiring layer 104 may be basically the same as that of the first array substrate, or may be adjusted locally on this basis.
  • the connection between the reference voltage sub-pad P11 of the first pad group P10 corresponding to the device area A in the fifth array substrate and the reference voltage lead 330 is more flexible.
  • the reference via hole corresponding to the device area A is connected to the reference voltage lead 330 .
  • the reference voltage sub-pad P11 of the first pad group P10 corresponding to the first device area A(1,1) and the reference voltage lead 330 pass through the A connection lead 500 overlapped by a reference via hole HR1 is connected.
  • the reference voltage sub-pad P11 of the first pad group P10 corresponding to the second device region A(1, 2) and the reference voltage lead 330 are connected through the connection lead 500 overlapping the third reference via hole HR3.
  • the reference voltage sub-pad P11 of the first pad group P10 corresponding to the third device region A(2, 1) and the reference voltage lead 330 are connected through the connection lead 500 overlapping the second reference via hole HR2.
  • the reference voltage sub-pad P11 of the first pad group P10 corresponding to the fourth device region A(2, 2) and the reference voltage lead 330 are connected through the connection lead 500 overlapping the fourth reference via hole HR4.
  • the lengths of the connection leads 500 between the reference voltage sub-pads P11 of each first pad group P10 and the reference voltage leads 330 are basically the same, which can improve the uniformity of the working environment of each first chip 010, and further improve the fifth array
  • the working stability of the substrate is favorable, and the debugging of the fifth array substrate is facilitated.
  • the wiring substrate in this embodiment can be used to prepare a sixth array substrate provided with the second chip 020 .
  • the structure of the second metal wiring layer 104 of the sixth array substrate may be basically the same as that of the second array substrate, or may be partially adjusted on this basis.
  • the connection between the reference voltage sub-pads P21 of the second pad group P20 and the reference voltage leads 330 in the first control region 2011 of the fifth array substrate is more flexible.
  • connection lead 500 connected to the reference voltage sub-pad P21 of the second pad group P20 and the reference voltage lead 330 can intersect with the second reference via hole HR2 may overlap with the fourth reference via HR4, or may overlap with the second reference via HR2 and the fourth reference via HR4 at the same time.
  • the connection lead 500 connecting the reference voltage sub-pad P21 and the reference voltage lead 330 may completely overlap with the reference voltage lead 330 .
  • the first reference via hole HR1, the third reference via hole HR3, the second input via hole HI2, and the fourth input via hole HI4 may not be associated with any
  • the two metal wiring layers 104 are overlapped and filled with the insulating protective layer 105 .
  • One of the second reference via hole HR2 and the fourth reference via hole HR4 is used to overlap the connection lead 500, so that the reference voltage sub-pad P11 is connected to the reference voltage lead 330 through the connection lead 500; the other may not be connected to any
  • the second metal wiring layers 104 overlap and are filled with the insulating protective layer 105 .
  • the wiring substrate in this embodiment can be used to prepare a seventh array substrate provided with the third chip 030 .
  • the structure of the seventh array substrate on the second metal wiring layer 104 may be basically the same as that of the third array substrate, and may also be partially adjusted on this basis.
  • the connection between the reference voltage sub-pads P31 of the third pad group P30 and the reference voltage leads 330 of the seventh array substrate in the first control region 2011 is more flexible.
  • the connection lead 500 connected to the reference voltage sub-pad P31 of the third pad group P30 and the reference voltage lead 330 may intersect the second reference via hole HR2 overlap, or may overlap with the fourth reference via HR4.
  • the connection lead 500 connecting the reference voltage sub-pad P31 and the reference voltage lead 330 may completely overlap with the reference voltage lead 330 .
  • the first reference via hole HR1, the third reference via hole HR3, the second input via hole HI2, and the fourth input via hole HI4 may not be associated with any
  • the two metal wiring layers 104 are overlapped and filled with the insulating protective layer 105 .
  • One of the second reference via hole HR2 and the fourth reference via hole HR4 is used to overlap the connection lead 500, so that the reference voltage sub-pad P31 is connected to the reference voltage lead 330 through the connection lead 500; the other may not be connected to any
  • the second metal wiring layers 104 overlap and are filled with the insulating protective layer 105 .
  • the wiring substrate in this embodiment can be used to prepare the eighth array substrate provided with the fourth chip 040 .
  • the structure of the second metal wiring layer 104 of the eighth array substrate may be basically the same as that of the fourth array substrate, and may also be partially adjusted on this basis.
  • the arrangement of the fourth pad group P40 in the first control region 2011 of the eighth array substrate is more flexible.
  • the fourth pad group P40 still includes two columns of sub-pads and the number of each column of sub-pads is 5 sub-pads. Wherein, regardless of whether the reference voltage sub-pads P41 are located on the side close to the first reference via hole HR1 or the side close to the third reference via hole HR3, the two reference voltage sub-pads P41 can be connected to the reference via holes.
  • only one reference voltage sub-pad P41 may be electrically connected to the reference voltage lead 330 through the connection lead 500, and the other reference voltage sub-pad P41 may be Not electrically connected to reference voltage lead 330 .
  • the fourth chip 040 can obtain the reference voltage GND through a reference voltage sub-pad P41 , which can meet the working requirements of the fourth chip 040 .
  • the reference voltage sub-pad P41 close to the first reference via hole HR1 or the third reference via hole HR3 can be electrically connected to the reference voltage lead 330 through the connection lead 500 connect.
  • the second input via hole HI2 and the fourth input via hole HI4 may not overlap with any second metal wiring layer 104 and are protected by the insulating protection layer 105 filling.
  • At least one of the first reference via hole HR1 to the fourth reference via hole HR4 is used to overlap the connection lead 500 , and the rest of the reference via holes may not overlap any second metal wiring layer 104 and are protected by insulation Layer 105 fills.
  • the third reference via HR3 and the fourth reference via HR4 are located in the first reference via HR1 and the second reference via HR1
  • the via hole HR2 is away from one side of the first power supply voltage lead 310 .
  • the first power via HV1, the first input via HI1, the first reference via HR1, the fourth power via HV4, the third input via HI3 and the third reference via HR3 A first via group is formed; one of the second power via HV2 and the third power via HV3, the second input via HI2, the second reference via HR2, the fifth power via HV5 and the sixth power via One of the HV6s, the fourth input via HI4 and the fourth reference via HR4 form a second via group.
  • the relative positions of the via holes in the first via hole group are the same as the relative positions of the via holes in the second via hole group. This can simplify the design and preparation of the wiring substrate and reduce the cost of various array substrates. Not only that, it can also simplify the design and preparation of the array substrate, and facilitate the debugging of the array substrate.
  • the insulating material layer 103 in a first control region 2011 , is further provided with a partial region exposing the reference voltage lead 330
  • the fifth reference via HR5 is located between the four device regions A. In this way, when the wiring substrate is used to prepare different array substrates, the connection leads 500 of some array substrates can be further simplified.
  • the wiring substrate in this embodiment can be used to prepare a ninth array substrate provided with the first chip 010.
  • the structure of the ninth array substrate on the second metal wiring layer 104 may be the same as that of the first array substrate or the fifth array substrate, and may also be partially adjusted on this basis.
  • the fifth reference via hole HR5 may not overlap with any second metal wiring layer 104 and is filled with the insulating protection layer 105 .
  • the wiring substrate in this embodiment can be used to prepare a tenth array substrate provided with the second chip 020 .
  • the structure of the tenth array substrate on the second metal wiring layer 104 may be the same as that of the second array substrate or the sixth array substrate, and may also be partially adjusted on this basis.
  • the reference voltage sub-pad P21 of the tenth array substrate and the reference voltage lead 330 pass through the connection with the second array substrate or the sixth array substrate.
  • the five reference vias HR5 are connected with overlapping connection leads 500 .
  • the reference voltage sub-pad P21 of the tenth array substrate may also be located opposite to the first direction C of the address sub-pad P25 direction side; at this time, the reference voltage sub-pad P21 and the reference voltage lead 330 can be connected through the connection lead 500 overlapping the fifth reference via hole HR5.
  • connection lead that overlaps with the fifth reference via hole HR5 is passed. 500 connections.
  • the first to fourth reference via holes HR1 to HR4 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • the wiring substrate in this embodiment can be used to prepare the eleventh array substrate provided with the third chip 030 .
  • the structure of the eleventh array substrate on the second metal wiring layer 104 may be the same as that of the third array substrate or the seventh array substrate, and may also be partially adjusted on this basis.
  • the reference voltage sub-pad P31 and the reference voltage lead 330 of the eleventh array substrate pass through the fifth reference
  • the connection lead 500 of the overlapped hole HR5 is connected.
  • connection leads 500 are connected; the first to fourth reference vias HR1 to HR4 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • the wiring substrate in this embodiment can be used to prepare a twelfth array substrate provided with the fourth chip 040 .
  • the structure of the twelfth array substrate on the second metal wiring layer 104 may be the same as that of the fourth array substrate or the eighth array substrate, and may also be partially adjusted on this basis.
  • the twelfth array substrate is far away from the first reference via hole HR1 or far away from the third reference via hole HR3
  • the reference voltage sub-pad P41 and the reference voltage lead 330 are connected through the connection lead 500 overlapping the fifth reference via hole HR5.
  • two sub-pad columns of the fourth pad group P40 are provided with reference voltage sub-pads
  • the sub-pad column of P41 is located on the side close to the fifth reference via HR5.
  • the reference voltage sub-pad P41 is located between the gate signal sub-pad P45 and the first reference via hole HR1; the fourth pad group P40 is located in the second direction of the fifth reference via hole HR5 D side. In this way, it is convenient for the reference voltage sub-pad P41 to be electrically connected to the reference voltage lead 330 through the fifth reference via hole HR5.
  • a reference voltage sub-pad P41 of the twelfth array substrate and the reference voltage lead 330 pass through the first reference via HR1 and the first reference via HR1.
  • One of the three reference vias HR3 is connected to an overlapping connection lead 500 .
  • Another reference voltage sub-pad P41 and the reference voltage lead 330 are connected through the connection lead 500 overlapping the fifth reference via hole HR5.
  • the remaining reference vias may not be stacked with any of the second metal wiring layers 104 and filled with the insulating protective layer 105.
  • the insulating material layer 103 is further provided with a second portion exposing a partial region of the first input lead 320 .
  • the sixth input via HI6 in the partial area of the input lead 340 ; the sixth input via HI6 and the fifth input via HI5 are symmetrical with respect to the axis of the reference voltage lead 330 .
  • the wiring substrate provided by the present disclosure can also be applied to different microchips, thereby preparing different array substrates.
  • the wiring substrate in this embodiment can be used to prepare a thirteenth array substrate provided with the first chip 010 .
  • the structure of the thirteenth array substrate on the second metal wiring layer 104 may be basically the same as that of the first array substrate, the fifth array substrate or the ninth array substrate, or may be partially adjusted on this basis.
  • the fifth input via hole HI5 and the sixth input via hole HI6 may not intersect with any second metal wiring layer 104 . stacked and filled with the insulating protective layer 105 .
  • the first input sub-section of the first pad group P10 corresponding to the first device region A(1,1) are connected through the connection lead 500 overlapping the fifth input via HI5.
  • the first input via HI1 may not overlap with any of the second metal wiring layers 104 and be filled with the insulating protection layer 105 .
  • the first input sub-section of the first pad group P10 corresponding to the second device area A(1, 2) The connection between the pad P13 and the second power supply voltage lead 350 is connected through the connection lead 500 overlapping the sixth input via HI6.
  • the third input via HI3 may not overlap with any of the second metal wiring layers 104 and be filled with the insulating protection layer 105 .
  • the wiring substrate in this embodiment can be used to prepare a fourteenth array substrate provided with the second chip 020 .
  • the structure of the fourteenth array substrate on the second metal wiring layer 104 may be basically the same as that of the first array substrate, the fifth array substrate or the tenth array substrate, or may be partially adjusted on this basis.
  • any one of the second reference via hole HR2 and the fifth reference via hole HR5 is connected to the overlapping connection lead 500 .
  • One of the chip power supply sub-pad P23 and the driving data sub-pad P24 is connected to the first input lead 320 through the connection lead 500 overlapping the fifth input via HI5; the other is connected to the second input lead 340. During this time, it is connected through the connecting lead 500 overlapping with the sixth input via HI6.
  • connection lead 500 overlapping with the fifth input via hole HI5 and the connection lead 500 overlapping with the sixth input via hole HI6 may extend linearly along the second direction D to reduce the distance between the connection lead 330 and the reference voltage lead 330 . the overlap length.
  • connection lead 500 overlapping the fifth input via HI5 ; optionally, the connection lead 500 extends linearly along the second direction, so as to reduce the overlapping length with the reference voltage lead 330 .
  • the driving data sub-pad P24 and the second input lead 340 are connected by a connecting lead 500 overlapping with the sixth input via HI6; optionally, the connecting lead 500 extends linearly along the second direction.
  • the first input via hole HI1 and the third input via hole HI3 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • the wiring substrate in this embodiment can be used to prepare the fifteenth array substrate provided with the third chip 030 .
  • the structure of the fifteenth array substrate on the second metal wiring layer 104 may be the same as that of the third array substrate, the seventh array substrate or the tenth array substrate, and may also be partially adjusted on this basis.
  • the chip power sub-pad P33 of the fifteenth array substrate and the first input lead 320 is connected through a connection lead 500 overlapping with the fifth input via HI5; optionally, the connection lead 500 extends linearly along the second direction D.
  • the driving data sub-pad P34 and the second input lead 340 are connected by a connecting lead 500 overlapping with the sixth input via HI6; optionally, the connecting lead 500 extends linearly along the second direction D.
  • the first input via hole HI1 and the third input via hole HI3 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • the wiring substrate in this embodiment can be used to prepare a sixteenth array substrate provided with the fourth chip 040 .
  • the structure of the sixteenth array substrate on the second metal wiring layer 104 may be the same as that of the fourth array substrate, the eighth array substrate or the twelfth array substrate, or may be partially adjusted on this basis.
  • the chip power sub-pad P43 of the sixteenth array substrate and the first input lead 320 is connected through a connection lead 500 overlapping with the fifth input via HI5; optionally, the connection lead 500 extends straight along the second direction D.
  • the driving data sub-pad P44 of the sixteenth array substrate and the second input lead 340 are connected through the connecting lead 500 overlapping the sixth input via HI6; optionally, the connecting lead 500 is along the second direction D Straight line extension.
  • the first input via hole HI1 and the third input via hole HI3 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • the control region 201 may further include a second control region 2012 .
  • the second control area 2012 is located on one side of the first direction C of each of the first control areas 2011 .
  • the last control area 201 along the first direction C may be the second control area 2012
  • the remaining control areas 201 may be the first control area 2011 .
  • the number of the second control area 2012 is one.
  • the wiring substrate includes a fan-out area
  • the first metal wiring layer 102 is provided with a fan-out lead 400 connected to each driving lead 300 in the fan-out area;
  • the corresponding fan-out leads 400 are connected in the second control region 2012 .
  • the connection positions of the fan-out leads 400 and the drive leads 300 are located within the range of each of the second control regions 2012 ; the fan-out regions and the second control regions 2012 at least partially overlap.
  • both the first device region A(1, 1) and the second device region A(1, 2) partially overlap with the driving lead 300 and neither are with the fan The outgoing leads 400 overlap; the third device region A(2,1) and the fourth device region A(2,2) may partially overlap the fanout leads 400 .
  • the insulating material layer 103 is provided with seventh to tenth power supply vias, seventh to tenth input vias, sixth to the tenth reference via.
  • the seventh power supply via HV7 and the eighth power supply via HV8 both expose at least a partial area of the first power supply voltage lead 310 .
  • the eighth power supply via HV8 is located on one side of the seventh power supply via HV7 in the first direction, and is located between the first device region A(1,1) and the third device region A(2,1).
  • the seventh power supply via HV7 may be located between the first device region A(1,1) and the third device region A(2,1), or may be located in the first device region A(1,1) away from the third device region A(1,1) One side of device area A(2,1).
  • the relative positional relationship between the seventh power supply via HV7 and the first device region A(1,1) in the second control region 2012 is the same as that of the first power supply via HV7 in the first control region 2011 .
  • the relative positional relationship between the hole HV1 and the first device region A(1,1) is the same.
  • the ninth power supply via HV9 and the tenth power supply via HV10 both expose at least a partial area of the second power supply voltage lead 350 .
  • the tenth power supply via HV10 is located on one side of the ninth power supply via HV9 in the first direction, and is located between the second device area A(1, 2) and the fourth device area A(2, 2).
  • the seventh power via HV7 may be located between the second device region A(1,2) and the fourth device region A(2,2), or may be located in the second device region A(1,2) away from the fourth device region A(1,2) One side of device area A(2,2).
  • the relative positional relationship between the ninth power supply via HV9 and the second device region A(1, 2) in the second control region 2012 is the same as that of the fourth power supply via HV9 in the first control region 2011 .
  • the relative positional relationship between the hole HV4 and the second device region A(1, 2) is the same.
  • the seventh input via hole HI7 and the eighth input via hole HI8 both expose a partial area of the first input lead 320; the seventh input via hole HI7 is located in the first device area A(1, 1) away from the third device area A(2, 1); the eighth input via HI8 is located between the first device area A(1,1) and the third device area A(2,1).
  • the ninth input via hole HI9 and the tenth input via hole HI10 both expose a partial area of the second input lead 340; the ninth input via hole HI9 is located in the second device area A(1, 2) away from the fourth device area A(2, 2) one side; the tenth input via HI10 is located between the second device area A(1, 2) and the fourth device area A(2, 2).
  • the sixth to tenth reference via holes all expose a partial area of the reference voltage lead 330; wherein the sixth reference via hole HR6 and the seventh reference via hole HR7 are arranged along the second direction D and are located in the first device region A(1,1) and the third device region A(2,1); the eighth reference via HR8 is located between the first device region A(1,1) and the third device region A(2,1), and the ninth reference via HR9 is located between the second device region A( 1 , 2 ) and the fourth device region A( 2 , 2 ), and the tenth reference via HR10 is located between the four device regions A of the second control region 2012 .
  • a driving lead 300 and its connected fan-out lead 400 can be a bent metal lead as a whole;
  • the parts in the extending direction are all the driving leads 300 .
  • the size of the driving lead 300 in the second direction D may already exhibit a gradually decreasing trend.
  • the seventh to tenth power supply vias, the seventh to tenth input vias, and the sixth to tenth reference vias may all expose part of the driving leads 300 , so that the connection leads 500 of the array substrate may be exposed. Can be connected to drive lead 300 instead of fan-out lead 400 .
  • the layouts of the driving leads 300 overlapping with different second control regions 2012 are basically the same.
  • various via holes are arranged above the relatively fixed driving leads 300 in each second control area 2012, which can avoid the difference of the fan-out leads 400, simplify the design and preparation of the wiring substrate, and facilitate the design of the array substrate. , preparation and commissioning.
  • the wiring substrate with the second control region 2012 provided in this embodiment can still be applied to different microchips and used to prepare different array substrates.
  • the wiring substrate of this embodiment can be used to prepare a seventeenth array substrate having the first chip 010 .
  • the structure of the first control region 2011 of the seventeenth array substrate may be the same as that of any one of the first array substrate, the fifth array substrate, the ninth array substrate, and the thirteenth array substrate.
  • the second metal wiring layer 104 of the seventeenth array substrate may include four first pad groups P10 corresponding to the four device regions A one-to-one; patterns of the respective pad groups The pattern of the first pad group P10 in the first control region 2011 may be the same.
  • the first pad group P10 corresponding to the first device area A(1,1) and the first pad group P10 corresponding to the second device area A(1,2) are located in the first device area A(1,1) and the second device region A(1,2); and the first pad group P10 corresponding to the first device region A(1,1) is set close to the first device region A(1,1), and the second device region
  • the first pad group P10 corresponding to A(1,2) is disposed close to the second device area A(1,2).
  • the first pad group P10 corresponding to the third device region A(2,1) is between the first device region A(1,1) and the third device region A(2,1)
  • the first pad group P10 corresponding to the fourth device region A(2,2) is between the second device region A(1,2) and the fourth device region A(2,2).
  • the first pad group P10 corresponding to the third device region A(2,1) and the first pad group P10 corresponding to the fourth device region A(2,2) are at least partially connected to the reference voltage lead 330. overlap.
  • the first pad group P10 corresponding to the first device area A(1,1) and the first pad group P10 corresponding to the second device area A(1,2) are arranged along the second direction D, and the third The first pad group P10 corresponding to the device area A(2, 1) and the first pad group P10 corresponding to the fourth device area A(2, 2) are arranged along the second direction D.
  • each first pad group P10 to the device control circuit and the cascading manner between them may be the same as those of the first control area P10 .
  • the first pad groups P10 corresponding to each device area A in one signal channel can be cascaded in sequence, so that the output sub-pads P12 of the first pad group P10 corresponding to the (n-1)-th device area A are output sub-pads P12
  • the first input sub-pads P13 of the first pad group P10 corresponding to the n-th-level device region A are connected by connecting wires 500 .
  • the second end of the device control circuit in the device area A is connected to the output sub-pad P12 of the corresponding second pad group P20 through the connection lead 500 .
  • the second control region 2012 between the first end of the device control circuit of the first device region A(1, 1) and the first power supply voltage lead 310, by overlapping with the seventh power supply via HV7
  • the first end of the device control circuit of the second device area A(1, 2) and the second power supply voltage lead 350 are connected through the connecting lead 500 overlapping the ninth power supply via HV9;
  • the first end of the device control circuit in the third device area A(2,1) is connected with the first power supply voltage lead 310 through the connecting lead 500 overlapping the eighth power supply via HV8; the fourth device area A( 2, 2)
  • the first end of the device control circuit and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the tenth power supply via HV10.
  • the tenth reference via hole HR10 may not overlap with any second metal wiring layer 104 and is filled with the insulating protection layer 105 .
  • the four first pad groups P10 can be dispersedly arranged, avoiding two adjacent first pad groups P10.
  • the disk sets P10 are arranged close to each other, thereby preventing the two adjacent first chips from being arranged next to each other and causing a large shading of the light, thereby avoiding the poor light spot (mura) caused by the shading of the first chips.
  • the wiring substrate of this embodiment can be used to prepare an eighteenth array substrate having the second chip 020 .
  • the structure of the first control region 2011 of the eighteenth array substrate may be the same as that of any one of the second array substrate, the sixth array substrate, the tenth array substrate, and the fourteenth array substrate.
  • the second metal wiring layer 104 of the eighteenth array substrate may include a second pad group P20.
  • the patterns of the second pad group P20 in the first control area 2011 and the second control area 2012 may be the same.
  • the second pad group P20 may be located between the four device regions A.
  • the second pad group P20 in a second control region 2012, along the first direction C, the second pad group P20 is located between the first device region A(1,1) and the third device region A(2,1);
  • the second pad group P20 In the second direction D, the second pad group P20 is located between the first device region A(1,1) and the second device region A(1,2).
  • the seventh reference via HR6 At least one of the hole HR7 and the tenth reference via hole HR10 is connected with the overlapping connection lead 500 .
  • One of the driving data sub-pad P24 and the chip power sub-pad P23 is connected with the first input lead 320 through the connection lead 500 overlapping with the eighth input via HI8; the other is connected with the second input lead 340. During this time, it is connected through the connection lead 500 overlapping with the tenth input via HI10.
  • the four output sub-pads P12 are connected to the second ends of the device control circuits of the four device regions A, respectively.
  • the reference voltage sub-pad P21 of the second pad group P20 is located in the address sub-pad of the second pad group P20
  • the first direction C side of P25 ensures that the connection lead 500 connected to the reference voltage sub-pad P21 of the second pad group P20 can extend to overlap the tenth reference via HR10, and the connection lead 500 is connected to the reference voltage sub-pad P21 of the second pad group P20.
  • the voltage leads 330 completely overlap. In this way, when the connection lead 500 and the reference voltage lead 330 are short-circuited, the eighteenth array substrate can avoid defects.
  • the chip power sub-pad P23 and the first input lead 320 are connected through the connection lead 500 overlapping the eighth input via HI8; the driving data sub-pad P24 is connected with the second input lead 340 Between them, the connection leads 500 overlapping with the tenth input via hole HI10 are connected; the address sub-pad P25 and the address leads 360 are connected through the connecting leads 500 overlapping with the address via holes.
  • the first output sub-pad P221 can be connected to the second end of the device control circuit of the first device area A(1, 1) through the connecting wire 500; the second output sub-pad P222 can be connected to the second device area through the connecting wire 500 The second end of the device control circuit of A(1,2) is connected; the third output sub-pad P223 can be connected to the second end of the device control circuit of the third device area A(2,1) through the connecting lead 500; The four-output sub-pad P224 may be connected to the second end of the device control circuit of the fourth device region A(2, 2) through the connection lead 500 .
  • the first end of the device control circuit in the first device area A(1,1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the seventh power supply via HV7; the second device area A( 1,2) The first end of the device control circuit and the second power supply voltage lead 350 are connected through the connecting lead 500 overlapping the ninth power supply via HV9; the device in the third device area A(2,1) The first end of the control circuit and the first power supply voltage lead 310 are connected through the connecting lead 500 overlapping the eighth power supply via HV8; the first end of the device control circuit in the fourth device area A(2, 2) It is connected with the second power supply voltage lead 350 through the connection lead 500 overlapping with the tenth power supply via HV10.
  • the seventh input via HI7 , the ninth input via HI9 , the sixth reference via HR6 , and the seventh reference via in the second control area 2012 HR7 , the eighth reference via hole HR8 , and the ninth reference via hole HR9 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • the wiring substrate of this embodiment can be used to prepare a nineteenth array substrate having the third chip 030 .
  • the structure of the first control region 2011 of the nineteenth array substrate may be the same as that of any one of the third array substrate, the seventh array substrate, the eleventh array substrate, and the fifteenth array substrate.
  • the second metal wiring layer 104 of the nineteenth array substrate may include a third pad group P30.
  • the patterns of the third pad group P30 in the first control area 2011 and the second control area 2012 may be the same.
  • the third pad group P30 may be located between the four device regions A.
  • the third pad group P30 is located between the first device region A(1,1) and the third device region A(2,1);
  • the third pad group P30 is located between the first device region A(1,1) and the second device region A(1,2).
  • the seventh reference via HR6 At least one of the hole HR7 and the tenth reference via hole HR10 is connected with the overlapping connection lead 500 .
  • One of the driving data sub-pad P34 and the chip power sub-pad P33 is connected with the first input lead 320 through the connection lead 500 overlapping the eighth input via HI8; the other is connected with the second input lead 340. During this time, it is connected through the connection lead 500 overlapping with the tenth input via HI10.
  • the four output sub-pads are connected to the second ends of the device control circuits of the four device regions A, respectively.
  • each third pad group P30 is cascaded in sequence, wherein the gate signal sub-pad P35 of the third pad group P30 of the first stage and the address lead 360 overlap with the address via hole.
  • the connecting lead 500 is connected; between the relay signal sub-pad P36 of the third pad group P30 of the (n-1) stage and the gate signal sub-pad P35 of the third pad group P30 of the n-th stage, Connected by connecting leads 500 .
  • the reference voltage sub-pad P31 of the third pad group P30 is located in the third pad group P30
  • the relay signal sub-pad P36 is on the first direction C side.
  • the connection lead 500 connected to the reference voltage sub-pad P31 of the third pad group P30 may extend to overlap with the tenth reference via hole HR10 , and the connection lead 500 completely overlaps with the reference voltage lead 330 .
  • the nineteenth array substrate can avoid defects.
  • the chip power sub-pad P33 and the first input lead 320 are connected through the connection lead 500 overlapping the eighth input via HI8;
  • the driving data sub-pad P34 is connected with the second input lead 340 between, through the connection lead 500 overlapping the tenth input via HI10;
  • the first output sub-pad P321 can be connected to the second end of the device control circuit of the first device area A(1,1) through the connection lead 500 connected;
  • the second output sub-pad P222 can be connected to the second end of the device control circuit of the second device area A(1, 2) through the connecting lead 500;
  • the third output sub-pad P223 can be connected to the third through the connecting lead 500
  • the second end of the device control circuit of the device area A(2,1) is connected;
  • the fourth output sub-pad P224 can be connected to the second end of the device control circuit of the fourth device area A(2,2) through the connection lead 500 .
  • the first end of the device control circuit of the first device region A(1,1) and the first power supply voltage lead 310 are connected through the connection lead 500 overlapping the seventh power supply via HV7 ; Between the first end of the device control circuit of the second device region A (1, 2) and the second power supply voltage lead 350, connected by the connecting lead 500 overlapping with the ninth power supply via HV9; the third device region A The first end of the device control circuit of (2,1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping with the eighth power supply via HV8; The first end of the device control circuit and the first power supply voltage lead 310 are connected through a connection lead 500 overlapping with the tenth power supply via HV10.
  • the seventh input via HI7 , the ninth input via HI9 , the sixth reference via HR6 , and the seventh reference via in the second control area 2012 HR7 , the eighth reference via hole HR8 , and the ninth reference via hole HR9 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • the wiring substrate of this embodiment can be used to prepare a twentieth array substrate having the fourth chip 040 .
  • the structure of the first control region 2011 of the twentieth array substrate may be the same as any one of the fourth array substrate, the eighth array substrate, the twelfth array substrate, and the sixteenth array substrate.
  • the second metal wiring layer 104 of the twentieth array substrate may include a fourth pad group P40, wherein the fourth pad group P40 in the first control area 2011 and the second control area 2012 The pattern can be the same.
  • the fourth pad group P40 may be located between the four device regions A.
  • the fourth pad group P40 in a second control region 2012, along the first direction C, is located between the first device region A(1,1) and the third device region A(2,1); In the second direction D, the fourth pad group P40 is located between the first device region A(1,1) and the second device region A(1,2).
  • the fourth pad group P40 has two sub-pad columns, and each sub-pad column includes five sub-pads arranged along the first direction C.
  • the sub-pad column where the reference voltage sub-pad P41 is disposed may be located on a side close to the tenth reference via hole HR10.
  • the connection lead 500 connected to one of the reference voltage sub-pads 41 may extend to overlap with the tenth reference via hole HR10; the connection lead 500 connected to the other reference voltage sub-pad 41 may extend to overlap with the eighth reference via hole HR10
  • the via hole HR8 or the ninth reference via hole HR9 overlaps.
  • connection lead 500 is connected; the other is connected to the second input lead 340 through the connection lead 500 overlapping the tenth input via HI10; The second end is connected.
  • each fourth pad group P40 is cascaded in sequence, wherein the gate signal sub-pad P45 of the fourth pad group P40 of the first stage and the address lead 360 are connected to the address via
  • the stacked connection leads 500 are connected; between the relay signal sub-pad P46 of the fourth pad group P40 of the (n-1) stage and the gate signal sub-pad P45 of the fourth pad group P40 of the n-th stage Connected by connecting leads 500 .
  • the relay signal sub-pads P46 of the fourth pad group P40 are located at On the side of the second direction D of the reference voltage sub-pad P41, the reference voltage sub-pad P41 is located on the side of the second direction D of the tenth reference via hole HR10.
  • the connection lead 500 connected to one reference voltage sub-pad P41 of the fourth pad group P40 extends to overlap the tenth reference via hole HR10, and the connection lead 500 connected to the other reference voltage sub-pad P41 extends to overlap with the tenth reference via HR10.
  • Eight reference vias HR8 overlap.
  • the driving data sub-pad P44 and the first input lead 320 are connected through the connection lead 500 overlapping the eighth input via HI8; the chip power sub-pad P43 and the second input lead 340 are connected through the tenth
  • the connecting leads 500 overlapping the input vias HI10 are connected.
  • the first output sub-pad P421 can be connected to the second end of the device control circuit of the fourth device region A(2, 2) through the connecting lead 500; the second output sub-pad P422 can be connected to the third device region through the connecting lead 500 The second end of the device control circuit of A(2,1) is connected; the third output sub-pad P423 can be connected to the second end of the device control circuit of the second device area A(1,2) through the connecting lead 500; The four-output sub-pad P424 may be connected to the second end of the device control circuit of the first device region A(1,1) through the connection wire 500 .
  • the first end of the device control circuit in the first device area A(1,1) is connected to the first power supply voltage lead 310 through the connection lead 500 overlapping the seventh power supply via HV7; the third device area A( 2,1)
  • the first end of the device control circuit and the first power supply voltage lead 310 are connected through the connecting lead 500 overlapping the eighth power supply via HV8; the device in the second device area A(1,2)
  • the first end of the control circuit and the second power supply voltage lead 350 are connected through the connection lead 500 overlapping the ninth power supply via HV9; the first end of the device control circuit in the fourth device area A(2, 2) It is connected with the second power supply voltage lead 350 through the connection lead 500 overlapping with the tenth power supply via HV10.
  • the seventh input via hole HI7 , the ninth input via hole HI9 , the sixth reference via hole HR6 , and the seventh reference via hole in the second control region 2012 HR7 and the ninth reference via hole HR9 may not overlap with any of the second metal wiring layers 104 and are filled with the insulating protection layer 105 .
  • At least one address lead 360 may be disposed in one signal channel.
  • the insulating material layer 103 may be provided with address via holes exposing a partial region of the address leads 360 .
  • the second metal wiring layer 104 may be provided with a connection lead 500 overlapping with the address via hole, and the connection lead 500 may be connected with the chip pad group corresponding to the microchip, so as to connect to the microchip Provide the required signal.
  • two address leads 360 may be provided within one control region column 220 .
  • the address leads 360 include a first address lead 361 and a second address lead 362, wherein the first address lead 361 is disposed between the first power supply voltage lead 310 and the first input lead 320 , and the second address lead 361 is disposed between the second power supply voltage lead 350 and the second input lead 340 .
  • one of the address leads 360 may extend to the end of the control region column 220 away from the binding region B, and the other address leads 360 may only be arranged closest to In the control area 201 of the binding area B.
  • a first address lead 361 and a second address lead 362 are provided in one control area column 220; wherein, the first address lead 361 may extend away from the binding area B and be connected to the control area.
  • Each control area 201 in the column 220 overlaps, and the second address lead 362 only overlaps with the second control area 2012 , that is, it may only be located in the control area 201 close to the binding area B.
  • the number of address leads 360 provided on the wiring substrate is not less than the number of control area rows 210, and at least one address lead 360 is provided in one signal channel.
  • the address vias include at least a first address via HD1 and a second address via HD2.
  • the number of address leads 360 provided on the wiring substrate is equal to the number of control area rows 210 .
  • the first address via hole HD1 may be disposed close to one end of the address lead 360 , and at least one first address via hole HD1 is disposed in any one signal channel.
  • the microchip when the microchip is the first chip 010, the third chip 030 or the fourth chip 040, the microchip and the address lead 360 can be connected through the connection lead 500 overlapping the first address via HD1, and then receive Control of the strobe signal loaded on address pin 360.
  • the first address via hole HD1 for connecting the first-level microchip and the address leads 360 may be located in the same control area 201 as the first-level microchip.
  • each of the first address via holes HD1 may be linearly arranged along the second direction D.
  • the first address via hole HD1 may be located at an end of the wiring substrate away from the binding area B.
  • the first address via hole HD1 may be located at one end of the wiring substrate close to the bonding area B.
  • only one first address via hole HD1 may be provided in one signal channel.
  • the first address vias HD1 are provided in a one-to-one correspondence with each address lead 360 , wherein any one of the first address vias HD1 may expose a partial area of the corresponding address lead 360 .
  • the number of the first address vias HD1 may exceed the required number; when setting the second metal wiring layer 104, one of the first address vias HD1 may be selected in any signal channel as the corresponding signal channel.
  • the first address vias HD1 are used to electrically connect the address leads 360 to the cascaded first-level microchips, and the remaining first address vias HD1 may be filled with the insulating protection layer 105 .
  • the array substrate can more flexibly select the first address via hole HD1 overlapping with the connection lead 500 according to the wiring requirement of the second metal wiring layer 104 , and make other first address via hole HD1 not overlap with any connection lead 500 , and is filled with the insulating protective layer 105 .
  • At least one second address via hole HD2 is provided in any control area row 210 , and one second address via hole HD2 may be selected from the control area row 210 as the corresponding control area row 210 . of the second address via HD2.
  • the second address via holes HD2 corresponding to the respective control area rows 210 respectively expose different address leads 360 .
  • a second address via hole HD2 corresponding to the control area row 210 is provided in any control area row 210 , and the second address via hole HD2 corresponding to each control area row 210 respectively exposes partial areas of different address leads.
  • part of the first address via hole HD1 may be multiplexed into the second address via hole HD2.
  • the second metal wiring layer 104 may be provided with a one-to-one correspondence with each control area row 210 And a plurality of connection leads 500 as scan leads.
  • the scan lines overlap with each control area 201 of the corresponding control area row 210 , and overlap with the second address via hole HD2 corresponding to the control area row 210 .
  • Each address subpad P25 in the control area row 210 may be connected to the scan wire through the connection wire 500 .
  • the address lead 360 connected to the scan lead can be used to load a gate signal to the scan lead, so as to enable each second chip 020 in the control area row 210 to be enabled.
  • the scan wire may extend along the second direction D, and its two ends may be located in the two control areas 201 at both ends of the control area row 210 , respectively, and the scan wire passes through other control areas in the control area row 210 .
  • Area 201 Area 201.
  • the scan wires may extend linearly along the second direction D and overlap with one of the second address vias HD2 .
  • the scan lead may include an extension section and a connection section, wherein the extension section may extend along the second direction D without overlapping with any second address via hole HD2; the connection section is connected with the extension section and overlaps with one of the second address vias HD2.
  • the number of the second address vias HD2 on the wiring substrate is the same as the number of the control area rows 210 , and different address leads 360 are exposed respectively; wherein each of the second address vias HD2 and Each control area row 210 is set in a one-to-one correspondence, and any second address via hole HD2 is located in the corresponding control area row 210 .
  • the number of the second address vias HD2 is small, which can reduce the possible impact of opening the second address vias HD2 on the address leads 360 .
  • any one of the second address vias HD2 is the same as the number of the address leads 360 and corresponds one-to-one Provided, any one of the second address vias HD2 exposes the corresponding address leads 360 .
  • at least one second address via hole HD2 is disposed within the overlapping range of each address wire 360 and the control area row 210 . In this way, referring to FIG.
  • one second address via hole HD2 may be selected in one control area row 210 as the second address via hole HD2 corresponding to the control area row 210 ; the control area row 210 The corresponding second address via hole HD2 overlaps the connection lead 500 to drive the respective microchips within the control area row 210 . In this way, the flexibility of the array substrate wiring can be increased, and the design, preparation and debugging of the wiring substrate and the array substrate are also facilitated.
  • the address vias may further include third address vias HD3.
  • the third address via hole HD3 may be disposed close to one end of the address lead 360; wherein, along the first direction C, the first address via hole HD1 and the third address via hole HD3 may be distributed in the present disclosure, respectively both ends of the wiring substrate.
  • at least one third address via hole HD3 may be provided, and the number of address leads is at least two; at least one first address via hole HD1 and at least one third address via hole HD3 respectively expose different address leads .
  • the output pin 012 of the first chip 010 of the last stage and the address lead 360 can be connected through the connection lead 500 stacked with the third address via hole HD3, so that the The cascaded first chips 010 form a loop.
  • the microchip of the array substrate is the third chip 030 or the fourth chip 040
  • the output pins of the last stage of the third chip 030 or the fourth chip 040 and the address leads 360 can pass through the third address via hole HD3
  • the stacked connection leads 500 are connected, so that the cascaded third chips 030 or the fourth chips 040 form a loop.
  • first address via hole HD1 and the third address via hole HD3 are two relative concepts defined according to the connection relationship between the microchip and the address leads 360 in the array substrate; one address via hole is in one type of array substrate. It may be a first address via hole HD1, and in another array substrate, it may be a third address via hole HD3. It can also be understood that, in some embodiments I, at least part of the third address vias HD3 may be multiplexed into the second address vias HD2.
  • the first address via hole HD1 and the third address via hole HD3 are not provided at the same time.
  • two address leads may be provided in one control area column, and one first address via HD1 and one third address via HD3 may be provided.
  • the first address via HD1 exposes one of the address leads
  • the third address via HD3 exposes the other address lead.
  • the first address via hole HD1 and the third address via hole can be simultaneously provided HD3.
  • both ends of any one of the address leads 360 are exposed by the first address via hole HD1 and the third address via hole HD3, respectively.
  • the microchips of the first stage and the microchips of the last stage are respectively connected to different address leads 360 . In this way, the flexibility of wiring of the array substrate can be improved.
  • part of the address vias may be stacked with the connection leads 500 so that the address leads 360 can load signals to the microchip through the connection leads 500 stacked with the address vias.
  • the remaining address vias may not be stacked with any of the second metal wiring layers 104 and may be filled with insulating protective layers 105 .
  • the first metal wiring layer 102 may further have a first voltage distribution line 371 extending along the second direction D, and each driving lead 300 may be located on the first voltage distribution line The first direction C side of 371 .
  • One of the power supply voltage lead and the reference voltage lead 330 may extend along the opposite direction of the first direction C to be connected to the first voltage distribution line 371 .
  • the first supply voltage lead and the second supply voltage lead may extend in the opposite direction of the first direction to connect with the first voltage distribution line, or the reference voltage lead may extend in the opposite direction of the first direction to connect with the first voltage distribution line line connection. This allows each power supply voltage lead or each reference voltage lead 330 to be electrically connected to each other, thereby improving the anti-signal disturbance capability and voltage stability of the array substrate used for the wiring substrate.
  • the first metal wiring layer 102 may further have a second voltage distribution line 372 extending along the second direction D.
  • the first voltage distribution line 371 may be located between the second voltage distribution line 372 and each of the driving leads 300 .
  • One of the power supply voltage lead and the reference voltage lead 330 may extend in the opposite direction of the first direction C to be connected with the first voltage distribution line 371; the other driving lead 300 may extend in the opposite direction of the first direction C at most It is connected to the second voltage distribution line 372, and the driving lead 300 is not connected to the first voltage distribution line.
  • the second metal wiring layer 104 may be provided with jumper wires 373, the jumper wires 373 straddle the first voltage distribution line 371, and the second voltage distribution line 372 is connected to the above-mentioned voltage distribution line 372 through a via hole.
  • Another drive lead 300 is connected.
  • each reference voltage lead 330 may extend in the opposite direction of the first direction C to the first voltage distribution line 371. connect.
  • the first voltage distribution line 371 is located between the second voltage distribution line 372 and at least part of the power supply voltage lines, so that at least part of the power supply voltage lines and the second voltage distribution line 372 cannot pass through the second voltage distribution line Line 372 is electrically connected.
  • the second metal wiring layer 104 may be provided with a plurality of jumper wires 373 , and each power supply voltage that is disconnected from the second voltage distribution line 372 on the first metal wiring layer 102
  • the leads are arranged in a one-to-one correspondence with each of the jumper leads 373 .
  • the jumper lead 373 straddles the first voltage distribution line 371, one end is connected to the second voltage distribution line 372 through a via hole, and the other end can be connected to a corresponding power supply voltage lead through a via hole.
  • each power supply voltage lead is electrically connected to each other, which can realize mutual shunting between different power supply voltage leads, improve the anti-overload capability of the power supply voltage lead, and improve the anti-signal disturbance performance and stability of the array substrate. pressure performance.
  • the reference voltage leads 330 are electrically connected to each other, which can improve the anti-signal disturbance capability of the array substrate and improve the stability of the voltage on the reference voltage leads 330 .
  • the first voltage distribution line 371 may be located between two power supply voltage leads on the two most sides of the wiring substrate.
  • the power supply voltage leads on the two most sides may extend along the opposite direction of the first direction C to be connected with the second voltage distribution lines 372 .
  • each power supply voltage lead may extend along the opposite direction of the first direction C to be connected with the first voltage distribution line 371 .
  • the first voltage distribution line 371 is located between the second voltage distribution line 372 and the reference voltage lead 330 , so that the reference voltage lead 330 and the second voltage distribution line 372 cannot pass through the first metal wiring layer 102 electrical connection.
  • the second metal wiring layer 104 may be provided with jumper wires 373 which are arranged in a one-to-one correspondence with each reference voltage lead 330 .
  • the jumper lead 373 straddles the first voltage distribution line 371 , one end is connected to the second voltage distribution line 372 through a via hole, and the other end can be connected to the corresponding reference voltage lead 330 through a via hole.
  • each power supply voltage lead is electrically connected to each other, which can realize mutual shunting between different power supply voltage leads, improve the anti-overload capability of the power supply voltage lead, and improve the anti-signal disturbance performance and stability of the array substrate. pressure performance.
  • the reference voltage leads 330 are electrically connected to each other, which can improve the anti-signal disturbance capability of the array substrate and improve the stability of the voltage on the reference voltage leads 330 .
  • the jumper wire 373 may partially overlap with the device area A; at this time, the direction of the connection wire 500 in the device control circuit may be adjusted so that the connection wire 500 avoids the crossover Pick up line 373.
  • the relative positions of the functional devices 107 in the device region A are the same in different device regions A, which can ensure that the functional devices 107 are uniformly distributed on the array substrate.
  • the array substrate further includes a plurality of conductive connection parts 374 , and the adjacent first power supply voltage lead 310 and the second power supply voltage lead 350 are connected through a plurality of conductive connection parts 374 .
  • the two adjacent power supply voltage leads are connected to form a grid through a plurality of conductive connection parts 374, which can not only allow sufficient and effective signal shunting between the two power supply voltage leads, but also avoid two adjacent power supply
  • the voltage leads are completely merged into one power supply voltage lead, so that the metal area of the first metal wiring layer 102 accounts for too much.
  • two adjacent power supply voltage leads can also be completely combined into one power supply voltage lead, so as to reduce the impedance of the power supply voltage lead and improve its overload resistance performance.
  • the metal area ratio of the metal wiring layer can be adjusted by adjusting the spacing between different driving leads 300 and hollowing out some of the driving leads 300 to meet the fabrication process requirements of the array substrate.
  • the conductive connection portion 374 may be located on the first metal wiring layer 102, and the conductive connection portion 374 is located between and connected with two adjacent power supply voltage leads, so that the phase Adjacent two supply voltage leads and the conductive connections 374 therebetween form a grid.
  • part or all of the conductive connection portion 374 may also be located on the second metal wiring layer 104 .
  • the conductive connection portion 374 is located in the second metal wiring layer 104, and the conductive connection portion 374 is connected to two adjacent power supply voltage leads through via holes.
  • the conductive connection portion 374 may include a first portion and a second portion, wherein the first portion is located on the first metal wiring layer 102 and is connected to one of the power supply voltage leads, and the second portion is located on the second metal wiring layer 104 and passes through the The hole is connected to the first part and another supply voltage lead.
  • Embodiments of the present disclosure also provide a light-emitting module, the light-emitting module includes any of the array substrates described in the above-mentioned embodiments of the array substrate.
  • the light-emitting module can be a light-emitting module of a computer monitor, a light-emitting module of a mobile phone screen, a light-emitting module of a TV, or a light-emitting module of other liquid crystal displays, and it can be a direct-type light-emitting module of a transmissive liquid crystal display, It can also be a direct light-emitting module of a reflective liquid crystal display. Since the light-emitting module has any of the array substrates described in the above-mentioned embodiments of the array substrate, it has the same beneficial effects, and details are not described herein again in this disclosure.

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Abstract

本公开提供一种布线基板、阵列基板和发光模组，属于显示技术领域。该布线基板包括依次层叠设置的衬底基板、第一金属布线层和绝缘材料层，第一金属布线层设置有沿第一方向延伸的多个驱动引线，绝缘材料层设置有暴露驱动引线的多个过孔。通过对驱动引线的位置和过孔位置的调整，该布线基板可以适用于不同的微芯片，进而可以用于制备不同的阵列基板。

Description

布线基板、阵列基板和发光模组 技术领域
本公开涉及显示技术领域，具体而言，涉及一种布线基板、阵列基板和发光模组。
背景技术
Mini LED(迷你发光二极管)背光基板采用直下式设计，通过大数量的Mini LED排布，从而实现更小范围内的区域调光，相较于传统的背光设计，其光学性能更好，能够在更小的混光距离内实现更好的亮度均匀性以及更高的色彩对比度。
当前，存在适用于Mini LED背光基板的多种不同的微芯片，但是不同微芯片对Mini LED背光基板的走线分布要求并不相同，导致需要针对性地开发不同微芯片对应的背光基板，且不同背光基板的掩膜、中间基板等均不能共用。这不仅增加了不同背光基板的开发周期和成本，而且不利于简化工艺制程。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种布线基板、阵列基板和发光模组，降低发光模组的成本。
根据本公开的一个方面，提供一种布线基板，包括阵列分布的多个控制区域，所述多个控制区域排列成多个控制区域行和多个控制区域列；任意一个所述控制区域列包括沿第一方向排列的至少两个所述控制区域，任意一个所述控制区域行包括沿第二方向排列的至少两个所述控制区域；所述第二方向平行于所述布线基板所在平面且与所述第一方向相交；
任意一个所述控制区域包括阵列分布的四个器件区，所述器件区用于设置相互电连接的功能器件；任意一个所述控制区域内的所述四个器件区分别为第一器件区、第二器件区、第三器件区和第四器件区；其中，所述第一器件区为所述控制区域内在所述第一方向上位于第一行、在所述第二方向上位于第一列的所述器件区；第二器件区为所述控制区域内在所述第一方向上位于第一行、在所述第二方向上位于第二列的所述器件区；第三器件区为所述控制区域内在所述第一方向上位于第二行、在所述第二方向上位于第一列的所述器件区；第四器件区为所述控制区域内在所述第一方向上位于第二行、在所述第二方向上位于第二列的所述器件区；
所述布线基板包括依次层叠设置的衬底基板、第一金属布线层和绝缘材料层；所述第一金属布线层设置有沿所述第一方向延伸的驱动引线；在任意一个所述控制区域列内，所述驱动引线至少包括沿所述第二方向依次排列的第一电源电压引线、第一输入引线、参考电压引线、第二输入引线和第二电源电压引线；所述布线基板还具有至少一个沿所述第一方向延伸的信号通道，且任意一个所述信号通道包括至少一个所述控制区域列；在任意一个所述信号通道中，所述驱动引线还包括至少一个地址引线；
所述控制区域包括第一控制区域；在一个所述第一控制区域中，所述绝缘材料层设置有第一电源过孔至第六电源过孔、第一输入过孔至第四输入过孔、第一参考过孔和第二参考过孔；
所述第一电源过孔至所述第三电源过孔沿所述第一方向依次排列且分别暴露所述第一电源电压引线的部分区域；所述第一电源过孔位于所述器件区A(1,1)远离所述器 件区A(2,1)的一侧或者位于所述器件区A(1,1)与所述器件区A(2,1)之间；所述第二电源过孔位于所述器件区A(1,1)和所述器件区A(2,1)之间；所述第三电源过孔位于所述器件区A(2,1)远离所述器件区A(1,1)的一侧；
所述第四电源过孔至所述第六电源过孔沿所述第一方向依次排列且分别暴露所述第二电源电压引线的部分区域；所述第四电源过孔位于所述第二器件区远离所述第四器件区的一侧或者位于所述第二器件区与所述第四器件区之间；所述第五电源过孔位于所述第二器件区和所述第四器件区之间；所述第六电源过孔位于所述第四器件区远离所述第二器件区的一侧；
所述第一输入过孔和所述第二输入过孔分别暴露所述第一输入引线的部分区域；所述第一输入过孔位于所述第一器件区远离所述第三器件区的边缘与所述第三器件区靠近所述第一器件区的边缘之间；所述第二输入过孔位于所述第三器件区远离所述第一器件区的一侧；
所述第三输入过孔和所述第四输入过孔分别暴露所述第二输入引线的部分区域；所述第三输入过孔位于所述第二器件区远离所述第四器件区的边缘与所述第四器件区靠近所述第二器件区的边缘之间；所述第四输入过孔位于所述第四器件区远离所述第二器件区的一侧；
所述第一参考过孔和所述第二参考过孔均暴露所述参考电压引线的部分区域；沿所述第一方向，所述第一参考过孔位于所述第一器件区与所述第三器件区之间，所述第二参考过孔位于所述第三器件区远离所述与第一器件区的一侧；
在任意一个所述信号通道，所述绝缘材料层还设置有暴露所述至少一个地址引线的部分区域的至少一个地址过孔。
在本公开的一种示例性实施例中，在一个所述控制区域列中，所述第一电源过孔与所述第四电源过孔关于第一对称轴对称，所述第二电源过孔与所述第五电源过孔关于第二对称轴对称，所述第三电源过孔与所述第六电源过孔关于第三对称轴对称；所述第一对称轴、所述第二对称轴和所述第三对称轴沿所述第一方向延伸且相互重合。
在本公开的一种示例性实施例中，在一个所述控制区域列中，所述第一输入过孔与所述第三输入过孔关于第四对称轴对称，所述第二输入过孔与所述第五输入过孔关于第六对称轴对称；所述第四对称轴和所述第五对称轴沿所述第一方向延伸且相互重合。
在本公开的一种示例性实施例中，在一个所述第一控制区域中，沿所述第一方向，所述第一电源过孔和所述第四电源过孔位于所述第一器件区与所述第一参考过孔之间，所述第二电源过孔和所述第五电源过孔位于所述第三器件区与所述第一参考过孔之间；所述第三电源过孔和所述第六电源过孔位于所述第三器件区与所述第二参考过孔之间。
在本公开的一种示例性实施例中，在一个所述第一控制区域中，所述绝缘材料层还设置有暴露所述参考电压引线的部分区域的第三参考过孔和第四参考过孔；所述第三参考过孔与所述第一参考过孔关于第六对称轴对称，所述第四参考孔与所述第二参考过孔关于所述第七对称轴对称；所述第六对称轴和所述第七对称轴沿所述第一方向延伸且相互重合。
在本公开的一种示例性实施例中，在一个所述第一控制区域中，在所述第二方向上，所述第三参考过孔和所述第四参考过孔位于所述第一参考过孔和所述第二参考过孔远离所述第一电源电压引线的一侧；
在一个所述第一控制区域中，所述第一电源过孔、所述第一输入过孔、所述第一参考过孔、所述第四电源过孔、所述第三输入过孔和所述第三参考过孔组成第一过孔组；所述第三电源过孔、所述第二输入过孔和所述第二参考过孔、所述第六电源过孔、 所述第四输入过孔和所述第四参考过孔组成第二过孔组；
所述第一过孔组中各个过孔之间的相对位置，与所述第二过孔组中各个过孔之间的相对位置相同。
在本公开的一种示例性实施例中，在一个所述第一控制区域中，所述绝缘材料层还设置有暴露所述参考电压引线的部分区域的第五参考过孔，所述第五参考过孔位于四个所述器件区之间。
在本公开的一种示例性实施例中，在一个所述第一控制区域中，所述绝缘材料层还设置有暴露所述第一输入引线的部分区域的第五输入过孔；沿所述第一方向，所述第五输入过孔位于所述第一参考过孔与所述第三器件区之间；所述绝缘材料层还可以设置有暴露所述第二输入引线的部分区域的第六输入过孔；所述第六输入过孔与所述第五输入过孔关于第八对称轴对称，所述第八对称轴沿所述第一方向延伸。
在本公开的一种示例性实施例中，所述控制区域还包括第二控制区域；在任意一个所述控制区域列中，所述第二控制区域位于各个所述第一控制区域的所述第一方向的一侧；
在一个所述第二控制区域中，所述绝缘材料层设置有第七电源过孔至第十电源过孔、第七输入过孔至第十输入过孔、第六参考过孔至第十参考过孔；
所述第七电源过孔和所述第八电源过孔均暴露所述第一电源电压引线的至少部分区域，所述第九电源过孔和所述第十电源过孔均暴露所述第二电源电压引线的至少部分区域；所述第八电源过孔位于所述第七电源过孔的所述第一方向一侧，且位于所述第一器件区和所述第三器件区之间；所述第十电源过孔位于所述第九电源过孔的所述第一方向一侧，且位于所述第二器件区和所述第四器件区之间；
所述第七输入过孔和所述第八输入过孔均暴露所述第一输入引线的部分区域；所述第七输入过孔位于所述第一器件区远离所述第三器件区的一侧；所述第八输入过孔位于所述第一器件区和所述第三器件区之间；所述第九输入过孔和所述第十输入过孔均暴露所述第二输入引线的部分区域；所述第九输入过孔位于所述第二器件区远离所述第四器件区的一侧；所述第十输入过孔位于所述第二器件区和所述第四器件区之间；
所述第六参考过孔至所述第十参考过孔均暴露所述参考电压引线部分区域；其中，所述第六参考过孔和所述第七参考过孔沿所述第二方向排列且位于所述第一器件区和所述第三器件区之间；所述第八参考过孔位于所述第一器件区和所述第三器件区之间，所述第九参考过孔位于所述第二器件区和所述第四器件区之间，所述第十参考过孔位于所述第二控制区域的所述四个器件区之间。
在本公开的一种示例性实施例中，所述布线基板包括扇出区，所述第一金属布线层在所述扇出区设置有与各个所述驱动引线连接的扇出引线；其中，所述驱动引线与对应的所述扇出引线在所述第二控制区域连接。
在本公开的一种示例性实施例中，所述地址引线的数量不小于所述控制区域行的数量；
所述地址过孔包括第一地址过孔和第二地址过孔；所述第一地址过孔靠近所述地址引线的其中一端设置，且在任意一个所述信号通道内设置至少一个所述第一地址过孔；在任意一个所述控制区域行内设置有与所述控制区域行对应的所述第二地址过孔，各个所述控制区域行对应的所述第二地址过孔分别暴露不同所述地址引线的部分区域。
在本公开的一种示例性实施例中，所述地址过孔还包括第三地址过孔；沿所述第一方向，所述第一地址过孔和所述第三地址过孔分别分布于所述布线基板的两端；在一个所述信号通道内，所述地址引线的数量至少为两个，所述第三地址过孔的数量至 少为1，至少一个所述第一地址过孔和至少一个所述第三地址过孔分别暴露不同的所述地址引线。
在本公开的一种示例性实施例中，在一个所述控制区域列中设置两个所述地址引线，以及设置有一个所述第一地址过孔和一个所述第三地址过孔；所述第一地址过孔暴露其中一个所述地址引线，所述第三地址过孔暴露另一个所述地址引线。
在本公开的一种示例性实施例中，任意一个所述地址引线的两端，分别被所述第一地址过孔和所述第三地址过孔暴露。
在本公开的一种示例性实施例中，所述第二地址过孔的数量与所述控制区域行的数量相同，各个所述第二地址过孔与各个所述控制区域行一一对应设置；各个所述第二地址过孔分别暴露不同的所述地址引线，且任意一个所述第二地址过孔位于对应的所述控制区域行内。
在本公开的一种示例性实施例中，在任意一个所述控制区域行内，所述第二地址过孔的数量与所述地址引线的数量相同且一一对应设置，任意一个所述第二地址过孔暴露对应的所述地址引线。
在本公开的一种示例性实施例中，所述第一金属布线层还具有沿所述第二方向延伸的第一电压分布线，各个所述驱动引线位于所述第一电压分布线的所述第一方向一侧；所述第一电源电压引线和所述第二电源电压引线沿所述第一方向的相反方向延伸至与所述第一电压分布线连接，或者所述参考电压引线沿所述第一方向的相反方向延伸至与所述第一电压分布线连接。
在本公开的一种示例性实施例中，所述第一金属布线层还包括沿所述第二方向延伸的第二电压分布线；其中，所述第一电压分布线位于所述第二电压分布线与各个所述驱动引线之间。
根据本公开的另一个方面，提供一种阵列基板，包括上述的布线基板。
在本公开的一种示例性实施例中，所述阵列基板还包括依次层叠于所述布线基板的绝缘材料层远离所述衬底基板一侧的第二金属布线层和绝缘保护层，以及包括多个功能器件和多个微芯片；
其中，所述第二金属布线层包括多个连接引线、多个器件焊盘组和多个芯片焊盘组，所述功能器件与所述器件焊盘组绑定连接，所述微芯片与所述芯片焊盘组绑定连接；所述器件焊盘组和所述芯片焊盘组与所述连接引线连接；至少部分所述连接引线通过设于所述绝缘材料层上的至少部分过孔与所述第一金属布线层连接。
在本公开的一种示例性实施例中，在任意一个所述器件区内设置有器件控制电路，所述器件控制电路包括一个所述功能器件或者多个电连接的所述功能器件；
在所述第一控制区域，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第一电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第二电源过孔或者第三电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第四电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第五电源过孔或者第六电源过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在一个所述控制区域内，所述阵列基板设置有与四个所述器件区一一对应的四个所述芯片焊盘组；任意一个所述芯片焊盘组包括参考电压子焊盘、输出子焊盘、第一输入子焊盘和第二输入子焊盘；任意一个所述器件区内的所述器件控制电路的第二端，与所述器件区对应的所述芯片焊盘组的所述输出子焊盘之间通过所述连接引线连接；
在一个所述信号通道内，各个所述器件区依次编号，且编号为1的所述器件区位于所述信号通道在所述第一方向上的一端；各个所述器件区对应的所述芯片焊盘组按照所述器件区的编号顺序依次级联；编号为1的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘与其中一个所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述器件区对应的所述芯片焊盘组的所述输出子焊盘与编号为n的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述器件区的数量；
在任意一个所述第一控制区域中，所述第一器件区对应的所述芯片焊盘组的所述参考电压子焊盘和所述第二器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第一参考过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述参考电压子焊盘和所述第四器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第二参考过孔交叠的所述连接引线连接；所述第一器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第一输入过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第二输入过孔交叠的所述连接引线连接；所述第二器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第三输入过孔交叠的所述连接引线连接；所述第四器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第四输入过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在一个所述控制区域内，所述阵列基板设置有与四个所述器件区一一对应的四个所述芯片焊盘组；任意一个所述芯片焊盘组包括参考电压子焊盘、输出子焊盘、第一输入子焊盘和第二输入子焊盘；任意一个所述器件区内的所述器件控制电路的第二端，与所述器件区对应的所述芯片焊盘组的所述输出子焊盘之间通过所述连接引线连接；
在一个所述信号通道内，各个所述器件区依次编号，且编号为1的所述器件区位于所述信号通道在所述第一方向上的一端；各个所述器件区对应的所述芯片焊盘组按照所述器件区的编号顺序依次级联；编号为1的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘与其中一个所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述器件区对应的所述芯片焊盘组的所述输出子焊盘与编号为n的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述器件区的数量；
在任意一个所述第一控制区域中，所述第一器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第一输入过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第二输入过孔交叠的所述连接引线连接；所述第二器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第三输入过孔交叠的所述连接引线连接；所述第四器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第四输入过孔交叠的所述连接引线连接；
当所述布线基板设置有所述第三参考过孔和所述第四参考过孔时，在任意一个所述第一控制区域中，所述第一器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第一参考过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第二参考过孔交叠的所述连接引线连接；所述第二器件区对应的所述芯片焊 盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第三参考过孔交叠的所述连接引线连接；所述第四器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第四参考过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，当所述布线基板包括所述第二控制区域时，在任意一个所述第二控制区域内，所述第一器件区对应的所述芯片焊盘组和所述第二器件区对应的所述芯片焊盘组位于第一器件区和第二器件区之间；且所述第一器件区对应的所述芯片焊盘组靠近第一器件区设置，所述第二器件区对应的所述芯片焊盘组靠近所述第二器件区设置；在所述第一方向上，所述第三器件区对应的所述芯片焊盘组在所述第一器件区和所述第三器件区之间，所述第四器件区对应的所述芯片焊盘组在所述第二器件区和所述第四器件区之间；
在任意一个所述第二控制区域内所述第一器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第六参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第一输入引线之间通过与所述第七输入过孔交叠的所述连接引线连接；
在任意一个所述第二控制区域内所述第二器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第七参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第二输入引线之间通过与所述第九输入过孔交叠的所述连接引线连接；
在任意一个所述第二控制区域内所述第三器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第八参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接；
在任意一个所述第二控制区域内所述第四器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第九参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第二输入引线之间通过与所述第十输入过孔交叠的所述连接引线连接；
在任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、地址子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；所述参考电压子焊盘位于所述地址子焊盘的第一方向一侧；
在任意一个所述第一控制区域内，所述参考电压子焊盘位于所述地址子焊盘的第一方向一侧；所述参考电压子焊盘与所述参考电压引线之间通过与所述第二参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第三输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、地址子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
当所述布线基板设置有所述第五参考过孔时，在任意一个所述第一控制区域内，所述参考电压子焊盘与所述参考电压引线之间通过与所述第五参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第三输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、地址子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
当所述布线基板设置有所述第五输入过孔和所述第六输入过孔时，在任意一个所述第一控制区域内，所述参考电压子焊盘与所述参考电压引线之间通过所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第五输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第六输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，当所述布线基板包括所述第二控制区域时，在任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接；四个所述器件区内的所述器件控制电路的第二端一一对应地与四个所述输出子焊盘通过连接引线连接；
所述参考电压子焊盘与所述参考电压引线之间通过与所述第十参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第十输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的 所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述控制区域的数量；
在任意一个所述第一控制区域中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第二参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；
当所述布线基板包括所述第五参考过孔时，在任意一个所述第一控制区域中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第五参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述控制区域的数量；
当所述布线基板包括所述第五参考过孔和所述第六参考过孔时，在任意一个所述第一控制区域中，所述参考电压子焊盘与所述参考电压引线之间通过所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第五输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第六输入过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，当所述布线基板包括所述第二控制区域时，在 任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接；四个所述器件区内的所述器件控制电路的第二端一一对应地与四个所述输出子焊盘通过连接引线连接；
所述参考电压子焊盘与所述参考电压引线之间通过与所述第十参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第十输入过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括两个参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述控制区域的数量；
在任意一个所述第一控制区域中，在所述第二方向上，所述参考电压子焊盘位于所述选通信号子焊盘与所述第一参考过孔之间；其中一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第一参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括两个参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；
当所述布线基板包括所述第五参考过孔时，在任意一个所述第一控制区域中，在所述第二方向上，所述参考电压子焊盘位于所述选通信号子焊盘与所述第一参考过孔 之间；所述芯片焊盘组位于所述第五参考过孔的第二方向一侧；其中一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第一参考过孔交叠的所述连接引线连接；另一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第五参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
在本公开的一种示例性实施例中，当所述布线基板包括所述第二控制区域时，在任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接；四个所述器件区内的所述器件控制电路的第二端一一对应地与四个所述输出子焊盘通过连接引线连接；
其中一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第十参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第十输入过孔交叠的所述连接引线连接。
根据本公开的另一个方面，提供一种发光模组，包括上述的阵列基板。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开中第一芯片的各个引脚位置示意图。
图2为本公开中第一焊盘组的各个子焊盘的位置示意图。
图3为本公开中第二芯片的各个引脚位置示意图。
图4为本公开中第二焊盘组的各个子焊盘的位置示意图。
图5为本公开中第三芯片的各个引脚位置示意图。
图6为本公开中第三焊盘组的各个子焊盘的位置示意图。
图7为本公开中第四芯片的各个引脚位置示意图。
图8为本公开中第四焊盘组的各个子焊盘的位置示意图。
图9为本公开一种实施方式中布线基板的局部结构示意图，其中，图9中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图10为图9所示的布线基板在一个第一控制区域的局部放大示意图，其中，图10中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图11为本公开一种实施方式中第一阵列基板在一个第一控制区域的结构示意图；其中，图11仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第一芯片的第一焊盘组、各个器件区内的功能器件。
图12为本公开一种实施方式中第二阵列基板在一个第一控制区域的结构示意图；其中，图12仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第二芯片的第二焊盘组、各个器件区内的功能器件。
图13为本公开一种实施方式中第三阵列基板在一个第一控制区域的结构示意图； 其中，图13仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第三芯片的第三焊盘组、各个器件区内的功能器件。
图14为本公开一种实施方式中第四阵列基板在一个第一控制区域的结构示意图；其中，图14仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第四芯片的第四焊盘组、各个器件区内的功能器件。
图15为本公开一种实施方式中布线基板的局部结构示意图，其中，图15中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图16为图15所示的布线基板在一个第一控制区域的局部放大示意图，其中，图16中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图17为本公开一种实施方式中第五阵列基板在一个第一控制区域的结构示意图；其中，图17仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第一芯片的第一焊盘组、各个器件区内的功能器件。
图18为本公开一种实施方式中第六阵列基板在一个第一控制区域的结构示意图；其中，图18仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第二芯片的第二焊盘组、各个器件区内的功能器件。
图19为本公开一种实施方式中第七阵列基板在一个第一控制区域的结构示意图；其中，图19仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第三芯片的第三焊盘组、各个器件区内的功能器件。
图20为本公开一种实施方式中第八阵列基板在一个第一控制区域的结构示意图；其中，图20仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第四芯片的第四焊盘组、各个器件区内的功能器件。
图21为本公开一种实施方式中布线基板的局部结构示意图，其中，图21中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图22为图21所示的布线基板在一个第一控制区域的局部放大示意图，其中，图22中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图23为本公开一种实施方式中第九阵列基板在一个第一控制区域的结构示意图；其中，图23仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第一芯片的第一焊盘组、各个器件区内的功能器件。
图24为本公开一种实施方式中第十阵列基板在一个第一控制区域的结构示意图；其中，图24仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第二芯片的第二焊盘组、各个器件区内的功能器件。
图25为本公开一种实施方式中第十一阵列基板在一个第一控制区域的结构示意图；其中，图25仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第三芯片的第三焊盘组、各个器件区内的功能器件。
图26为本公开一种实施方式中第十二阵列基板在一个第一控制区域的结构示意图；其中，图26仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第四芯片的第四焊盘组、各个器件区内的功能器件。
图27为本公开一种实施方式中布线基板的局部结构示意图，其中，图27中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图28为图27所示的布线基板在一个第一控制区域的局部放大示意图，其中，图28中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图29为本公开一种实施方式中第十三阵列基板在一个第一控制区域的结构示意图；其中，图29仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第一芯片的第一焊盘组、各个器件区内的功能器件。
图30为本公开一种实施方式中第十四阵列基板在一个第一控制区域的结构示意图； 其中，图30仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第二芯片的第二焊盘组、各个器件区内的功能器件。
图31为本公开一种实施方式中第十五阵列基板在一个第一控制区域的结构示意图；其中，图31仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第三芯片的第三焊盘组、各个器件区内的功能器件。
图32为本公开一种实施方式中第十六阵列基板在一个第一控制区域的结构示意图；其中，图32仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第四芯片的第四焊盘组、各个器件区内的功能器件。
图33为本公开一种实施方式中布线基板的局部结构示意图，其中，图33中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图34为图33所示的布线基板在一个第二控制区域的局部放大示意图，其中，图34中仅示意了第一金属布线层和绝缘材料层所设置的至少部分过孔的相对位置。
图35为本公开一种实施方式中第十七阵列基板在一个第二控制区域的结构示意图；其中，图35仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第一芯片的第一焊盘组、各个器件区内的功能器件。
图36为本公开一种实施方式中第十八阵列基板在一个第二控制区域的结构示意图；其中，图36仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第二芯片的第二焊盘组、各个器件区内的功能器件。
图37为本公开一种实施方式中第十九阵列基板在一个第二控制区域的结构示意图；其中，图37仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第三芯片的第三焊盘组、各个器件区内的功能器件。
图38为本公开一种实施方式中第二十阵列基板在一个第二控制区域的结构示意图；其中，图38仅示意了驱动引线、绝缘材料层所设置的至少部分过孔的相对位置、连接引线(用粗线条表示)、用于绑定第四芯片的第四焊盘组、各个器件区内的功能器件。
图39为本公开一种实施方式的布线基板中，输入引线和参考电压引线的局部结构示意图。
图40为本公开一种实施方式的布线基板中，地址过孔和地址引线的相对位置示意图。
图41为本公开一种实施方式的阵列基板中，微芯片与地址引线电连接的结构示意图。
图42为本公开一种实施方式的阵列基板中，微芯片与地址引线电连接的结构示意图。
图43为本公开一种实施方式的布线基板中，地址过孔和地址引线的相对位置示意图。
图44为本公开一种实施方式的阵列基板中，微芯片与地址引线电连接的结构示意图。
图45为本公开一种实施方式的阵列基板中，微芯片与地址引线电连接的结构示意图。
图46为本公开一种实施方式的阵列基板，在远离绑定区一端的局部结构示意图。
图47为本公开一种实施方式的阵列基板的局部结构示意图，其中，图47没有示出与器件焊盘组绑定连接的功能器件。
图48为本公开一种实施方式中，布线基板在图47的MN位置的剖切结构示意图。
图49为本公开一种实施方式中，阵列基板在图47的MN位置的剖切结构示意图，其中，图49没有示出与器件焊盘组绑定连接的功能器件。
图50为本公开一种实施方式中，第一金属布线层在靠近绑定区的一端的结构示意 图。
附图标记说明：
101、衬底基板；102、第一金属布线层；1021、铜种子层；1022、铜生长层；103、绝缘材料层；1031、第一钝化层；1032、平坦化有机材料层；104、第二金属布线层；105、绝缘保护层；1051、第二钝化层；1052、有机保护层；106、微芯片；107、功能器件；108、缓冲层；201、控制区域；210、控制区域行；220、控制区域列；2011、第一控制区域；2012、第二控制区域；300、驱动引线；301、凸出部；302、容置缺口；303、第一支撑金属部；304、第二支撑金属部；305、第三支撑金属部；306、第四支撑金属部；310、第一电源电压引线；320、第一输入引线；330、参考电压引线；340、第二输入引线；350、第二电源电压引线；360、地址引线；361、第一地址引线；362、第二地址引线；371、第一电压分布线；372、第二电压分布线；373、跨接引线；374、导电连接部；400、扇出引线；500、连接引线；010、第一芯片；011、参考电压引脚；012、输出引脚；013、第一输入引脚；014、第二输入引脚；P10、第一焊盘组；P11、参考电压子焊盘；P12、输出子焊盘；P13、第一输入子焊盘；P14、第二输入子焊盘；020、第二芯片；021、参考电压引脚；0221、第一输出引脚；0222、第二输出引脚；0223、第三输出引脚；0224、第四输出引脚；023、芯片电源引脚；024、驱动数据引脚；025、地址引脚；P20、第二焊盘组；P21、参考电压子焊盘；P221、第一输出子焊盘；P222、第二输出子焊盘；P223、第三输出子焊盘；P224、第四输出子焊盘；P23、芯片电源子焊盘；P24、驱动数据子焊盘；P25、地址子焊盘；030、第三芯片；031、参考电压引脚；0321、第一输出引脚；0322、第二输出引脚；0323、第三输出引脚；0324、第四输出引脚；033、芯片电源引脚；034、驱动数据引脚；035、选通信号引脚；036、中继信号引脚；P30、第三焊盘组；P31、参考电压子焊盘；P321、第一输出子焊盘；P322、第二输出子焊盘；P323、第三输出子焊盘；P324、第四输出子焊盘；P33、芯片电源子焊盘；P34、驱动数据子焊盘；P35、选通信号子焊盘；P36、中继信号子焊盘；040、第四芯片；041、参考电压引脚；0421、第一输出引脚；0422、第二输出引脚；0423、第三输出引脚；0424、第四输出引脚；043、芯片电源引脚；044、驱动数据引脚；045、选通信号引脚；046、中继信号引脚；P40、第四焊盘组；P41、参考电压子焊盘；P421、第一输出子焊盘；P422、第二输出子焊盘；P423、第三输出子焊盘；P424、第四输出子焊盘；P43、芯片电源子焊盘；P44、驱动数据子焊盘；P45、选通信号子焊盘；P46、中继信号子焊盘；P50、器件焊盘组；P51、第一器件子焊盘；P52、第二器件子焊盘；HV1、第一电源过孔；HV2、第二电源过孔；HV3、第三电源过孔；HV4、第四电源过孔；HV5、第五电源过孔；HV6、第六电源过孔；HV7、第七电源过孔；HV8、第八电源过孔；HV9、第九电源过孔；HV10、第十电源过孔；HI1、第一输入过孔；HI2、第二输入过孔；HI3、第三输入过孔；HI4、第四输入过孔；HI5、第五输入过孔；HI6、第六输入过孔；HI7、第七输入过孔；HI8、第八输入过孔；HI9、第九输入过孔；HI10、第十输入过孔；HR1、第一参考过孔；HR2、第二参考过孔；HR3、第三参考过孔；HR4、第四参考过孔；HR5、第五参考过孔；HR6、第六参考过孔；HR7、第七参考过孔；HR8、第八参考过孔；HR9、第九参考过孔；HR10、第十参考过孔；HD1、第一地址过孔；HD2、第二地址过孔；HD3、第三地址过孔；A、器件区；B、绑定区；C、第一方向；D、第二方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中 相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在相关技术中，用作主动驱动式Mini LED基板的阵列基板，可以包括依次层叠设置的衬底基板、第一金属布线层、绝缘材料层、第二金属布线层、绝缘保护层，以及包括绑定于第二金属布线层上的微芯片和发光元件。其中，第一金属布线层可以设置有驱动引线；第二金属布线层设置有用于绑定发光元件的器件焊盘组和用于绑定微芯片的芯片焊盘组，还设置有用于使得器件焊盘组、芯片焊盘组和驱动引线连接的连接引线。在微芯片的控制下，发光元件可以受控地发光。在相关技术中，存在可以用于阵列基板的多种不同的微芯片。
示例性地，参见图1，第一芯片010作为一种微芯片，具有四个不同的引脚，即第一输入引脚013、第二输入引脚014、参考电压引脚011和输出引脚012。其中，四个引脚分布在一个矩形区域内，且分别位于矩形区域的四个顶角。参考电压引脚011用于向第一芯片010加载参考电压GND，第一输入引脚013用于向第一芯片010加载第一输入信号Pwr，第二输入引脚014用于向第一芯片010加载第二输入信号Di。
第一芯片010可以被配置为，根据第一输入引脚013所加载的第一输入信号Pwr和第二输入引脚014上所加载的第二输入信号Di，在第一时间段内通过输出引脚012输出中继信号，以及在第二时间段内通过输出引脚012为发光元件提供发光通路。其中，中继信号为地址信号或者选通信号。当一个第一芯片010的第二输入引脚014加载该中继信号后，该第一芯片010可以接收加载于第一输入引脚013上的第一输入信号Pwr。第一输入信号Pwr为电力线载波通讯信号，其可以向第一芯片010提供芯片工作电压VCC的同时提供驱动数据。该第一芯片010应用于阵列基板时，一个或者多个相互连接的发光元件可以组成一个发光区，且一个发光区可以与一个第一芯片010的输出引脚012连接。如此，一个第一芯片010可以驱动一个发光区内，且多个第一芯片010可以依次级联形成一个信号通道。在一个信号通道内，第n级第一芯片010响应第(n-1)级第一芯片010的中继信号，并向第(n+1)级第一芯片010发送中继信号，进而实现对各级第一芯片010的控制。
参见图2，为了与第一芯片010连接，在阵列基板上需要设置作为芯片焊盘组的第一焊盘组P10，第一焊盘组P10具有与第一芯片010的各个引脚一一对应的多个子焊盘。第一焊盘组P10可以包括用于与第一芯片010的参考电压引脚011绑定连接的参考电压子焊盘P11、用于与第一芯片010的输出引脚012绑定连接的输出子焊盘P12、用于与第一芯片010的第一输入引脚013绑定连接的第一输入子焊盘P13、用于与第一芯片010的第二输入引脚014绑定连接的第二输入子焊盘P14。
再示例性地，参见图3，第二芯片020作为一种微芯片，具有八个不同的引脚，即芯片电源引脚023、驱动数据引脚024、地址引脚025、参考电压引脚011和四个输出引脚(包括第一输出引脚0221、第二输出引脚0222、第三输出引脚0223、第四输出引脚0224)。其中，八个引脚分布在一个矩形区域内，矩形区域的四个顶角分别设置四个输出引脚，在矩形区域的四个边缘的中间分别设置芯片电源引脚023、驱动数据引脚024、地址引脚025、参考电压引脚021。芯片电源引脚023和驱动数据引脚024分别位于相对设置的两边缘上。其中，芯片电源引脚023用于向第二芯片020加载芯片工作电压VCC，驱动数据引脚024用于向第二芯片020加载驱动数据Data，参考电压引脚021用于向第二芯片020加载参考电压GND，地址引脚025用于向第二芯片020加载选通信号，四个输出引脚分别用于加载第二芯片020输出的驱动信号。
第二芯片020被配置为，在地址引脚025上所加载的选通信号的控制下，接收驱动数据引脚024上所加载的驱动数据Data；然后，根据所接收的驱动数据Data、芯片电源引脚023上所加载的芯片工作电压VCC、参考电压引脚021上所加载的参考电压GND，通过四个输出引脚分别为发光元件提供发光通路。当该第二芯片020应用于阵列基板时，一个或者多个相互连接的发光元件可以组成一个发光区，且一个发光区可以与一个第二芯片020的一个输出引脚连接。如此，第二芯片020的任意一个输出引脚可以用于控制一个发光区；即一个第二芯片020可以控制四个发光区各自独立地发光。多个第二芯片020可以排列成多行，阵列基板通过逐行扫通各个第二芯片行，实现对各个第二芯片020的控制。
参见图4，为了与第二芯片020完成连接，在阵列基板上需要设置作为芯片焊盘组的第二焊盘组P20，第二焊盘组P20包括八个子焊盘，分别为用于与芯片电源引脚023绑定连接的芯片电源子焊盘P23、用于与驱动数据引脚024绑定连接的驱动数据子焊盘P24、用于与地址引脚025绑定连接的地址子焊盘P25、用于与参考电压引脚011绑定连接的参考电压子焊盘P11，以及用于与四个输出引脚一一对应绑定连接的四个输出子焊盘。其中，四个输出子焊盘包括用于与第一输出引脚0221绑定连接的第一输出子焊盘P221、用于与第二输出引脚0222绑定连接的第二输出子焊盘P222、用于与第三输出引脚0223绑定连接的第三输出子焊盘P223和用于与第四输出引脚0224绑定连接的第四输出子焊盘P224。参见图4，八个子焊盘分布在一个矩形区域内，矩形区域的四个顶角分别设置四个输出子焊盘，在矩形区域的四个边缘的中间分别设置芯片电源子焊盘P23、驱动数据子焊盘P24、地址子焊盘P5、参考电压子焊盘P21。芯片电源子焊盘P23和驱动数据子焊盘P24分别位于相对设置的两边缘上，参考电压子焊盘P11和地址子焊盘P25分别位于相对设置的两边缘上；参考电压子焊盘P11还可以向矩形区域的中心延伸。
再示例性地，参见图5，第三芯片030作为一种微芯片，包括九个引脚，即芯片电源引脚033、驱动数据引脚034、选通信号引脚035、中继信号引脚036、参考电压引脚031和四个输出引脚，四个输出引脚分别包括第一输出引脚0321、第二输出引脚0322、第三输出引脚0323和第四输出引脚0324。九个引脚呈三行三列阵列分布于一矩形区域内，矩形区域的四个顶角分别设置四个输出引脚，矩形区域的中心位置设置选通信号引脚035，矩形区域的四个边缘分别设置中继信号引脚036、芯片电源引脚033、参考电压引脚031和驱动数据引脚034。其中，芯片电源引脚033和驱动数据引脚034分别位于相对的两个边缘上，中继信号引脚036和参考电压引脚031分别位于相对的两个边缘上。其中，芯片电源引脚033用于向第三芯片030加载芯片工作电压VCC，驱动数据引脚034用于向第三芯片030加载驱动数据Data，参考电压引脚031用于向第三芯片030加载参考电压GND，选通信号引脚035用于向第三芯片030加载选通信号，中继信号引脚036用于加载第三芯片030输出的中继信号，四个输出引脚分别用于加载第三芯片030输出的驱动信号。其中，中继信号为一种选通信号，当一个第三芯片030的选通信号引脚035加载有中继信号时，该第三芯片030可以接收加载于驱动数据引脚034上的驱动数据Data。
第三芯片030被配置为，根据选通信号引脚035上所加载的选通信号或者中继信号，以及根据驱动数据引脚034上所加载的驱动数据Data，通过中继信号引脚036输出中继信号，以及通过四个输出引脚分别为发光元件提供发光通路。该第三芯片030应用于阵列基板时，一个或者多个相互连接的发光元件可以组成一个发光区，且一个发光区可以与一个第三芯片030的一个输出引脚连接。一个第三芯片030的四个输出引脚可以分别驱动一个发光区，即一个第三芯片030可以驱动四个发光区。多个第三芯片030可以依次级联形成一个信号通道；在一个信号通道内，第一级第三芯片030响应选通信号而向第二级第三芯片030发送中继信号，第n级级第三芯片030响应第(n-1)级第三芯片030的中继信号并向第(n+1)级第三芯片030发送中继信号，进而实现对各级第三芯片030的控制。
参见图6，为了与第三芯片030实现连接，在阵列基板上需要设置作为芯片焊盘组的 第三焊盘组P30，第三焊盘组P30包括与第三芯片030的九个引脚一一对应的九个子焊盘，分别为用于与芯片电源引脚033绑定连接的芯片电源子焊盘P33、用于与驱动数据引脚034绑定连接的驱动数据子焊盘P34、用于与选通信号引脚035绑定连接的选通信号子焊盘P35、用于与中继信号引脚036绑定连接的中继信号子焊盘P36、用于与参考电压引脚031绑定连接的参考电压子焊盘P31和用于与四个输出引脚一一对应绑定连接的四个输出子焊盘。四个输出子焊盘分别包括第一输出子焊盘P321、第二输出子焊盘P322、第三输出子焊盘P323和第四输出子焊盘P324。九个子焊盘呈三行三列阵列分布于一矩形区域内，矩形区域的四个顶角分别设置四个输出子焊盘，矩形区域的中心位置设置选通信号子焊盘P35，矩形区域的四个边缘分别设置中继信号子焊盘P36、芯片电源子焊盘P33、参考电压子焊盘P31和驱动数据子焊盘P34。其中，芯片电源子焊盘P33和驱动数据子焊盘P34分别位于相对的两个边缘上，中继信号子焊盘P36和参考电压子焊盘P31分别位于相对的两个边缘上。
再示例性地，参见图7，第四芯片040作为一种微芯片，包括十个引脚，即芯片电源引脚043、驱动数据引脚044、选通信号引脚045、中继信号引脚046、两个参考电压引脚041和四个输出引脚。四个输出引脚分别包括第一输出引脚0421、第二输出引脚0422、第三输出引脚0423和第四输出引脚0424。十个引脚呈两列五行分布于一个矩形区域内，其中，第一列依次设置第一输出引脚0421、中继信号引脚046、芯片电源引脚043、选通信号引脚045和第三输出引脚0423；第二列依次设置第二输出引脚0422、参考电压引脚041、驱动数据引脚044、参考电压引脚041和第四输出引脚0424。其中，芯片电源引脚043用于向第四芯片040加载芯片工作电压VCC，驱动数据引脚044用于向第四芯片040加载驱动数据Data，参考电压引脚041用于向第四芯片040加载参考电压GND，选通信号引脚045用于向第四芯片040加载选通信号，中继信号引脚046用于加载第四芯片040输出的中继信号，四个输出引脚用于加载第四芯片040输出的驱动信号。其中，中继信号为一种选通信号，当一个第四芯片040的选通信号引脚045加载有中继信号时，该第四芯片040可以接收加载于驱动数据引脚044上的驱动数据Data。
第四芯片040被配置为，根据选通信号引脚045上所加载的选通信号或者中继信号，以及根据驱动数据引脚044上所加载的驱动数据，通过中继信号引脚046输出中继信号，以及通过四个输出引脚分别为发光元件提供发光通路。该第四芯片040应用于阵列基板时，一个或者多个相互连接的发光元件可以组成一个发光区，且一个发光区可以与一个第四芯片030的一个输出引脚连接。这样，第四芯片040的四个输出引脚可以分别驱动一个发光区，即一个第四芯片040可以驱动四个发光区。多个第四芯片040可以依次级联形成一个信号通道；在一个信号通道内，第n级第四芯片040响应第(n-1)级第四芯片040的中继信号并向第(n+1)级第四芯片040发送中继信号，进而实现对各个第四芯片040的控制。
参见图8，为了与第四芯片040完成电气连接，在阵列基板上需要设置作为芯片焊盘组的第四焊盘组P40，第四焊盘组P40包括与第四芯片040的十个引脚一一对应的十个子焊盘，分别为用于与芯片电源引脚043绑定连接的芯片电源子焊盘P43、用于与驱动数据引脚044绑定连接的驱动数据子焊盘P44、用于与选通信号引脚045绑定连接的选通信号子焊盘P45、用于与中继信号引脚046绑定连接的中继信号子焊盘P46、用于与两个参考电压引脚041一一对应的绑定连接的两个参考电压子焊盘P41、用于与四个输出引脚一一对应的绑定连接的四个输出子焊盘。四个输出子焊盘分别包括用于与第一输出引脚0421绑定连接的第一输出子焊盘P421、用于与第二输出引脚0422绑定连接的第二输出子焊盘P422、用于与第三输出引脚0423绑定连接的第三输出子焊盘P423和用于与第四输出引脚0424绑定连接的第四输出子焊盘P424。十个子焊盘呈两列五行分布于一个矩形区域内，其中，第一列依次设置第一输出子焊盘P421、中继信号子焊盘P46、芯片电源子焊盘P43、选通信号子焊盘P45和第三输出子焊盘P423；第二列依次设置第二输出子焊盘P422、参 考电压子焊盘P41、驱动数据子焊盘P44、参考电压子焊盘P41和第四输出子焊盘P424。
由上可知，不同微芯片的引脚数量、各个引脚用于加载的信号、加载相同信号的引脚的位置分布等均存在差异，不同微芯片所能够驱动的发光区的数量也可能存在差异。这导致，在形成阵列基板时，每一种阵列基板对位于第一金属布线层的驱动引线的设置、位于第二金属布线层的连接引线和器件焊盘组的设置均具有不同的要求，使得不同的阵列基板在结构上存在很大的差异。
不仅如此，在相关技术中，在制备阵列基板时，第一金属布线层的驱动引线和第二金属布线层的连接引线之间容易出现不受控的短接不良。如果随意调整连接引线，则可能会导致连接引线与不同信号的驱动引线之间发生短路不良的概率增大，将导致阵列基板的良率降低。
为了简化不同阵列基板的制备工艺，降低不同阵列基板的制备成本且不降低阵列基板的良率，本公开提供一种布线基板。参见图48，本公开的布线基板包括依次层叠设置的衬底基板101、第一金属布线层102和绝缘材料层103，其可以用于进一步制备至少两种不同类型的阵列基板，且每种类型的阵列基板上所采用的微芯片的类型可以不同。换言之，在本公开提供的布线基板的基础上，参见图49，可以进一步制备所需的第二金属布线层104和绝缘保护层105，并绑定功能器件(图49中未示出)和所需的微芯片(图49中未示出)，获得所需的阵列基板。如此，本公开的布线基板可以作为一种中间基板而适用于不同类型的阵列基板，使得不同类型的阵列基板可以在制备布线基板阶段采用相同的工艺、物料和设备，例如共用相同的掩膜板等，进而降低不同类型的阵列基板的成本，并有利于提高不同类型的阵列基板的产能和良率。
在本公开提供的布线基板中，参见图48，绝缘材料层103可以设置有多个暴露第一金属布线层102的过孔。在基于本公开的布线基板制备阵列基板时，参见图49，第二金属布线层104可以通过这些过孔中的至少部分过孔与第一金属布线层102连接，且这些过孔中的其余部分过孔可以被绝缘保护层105所填充。当基于本公开的布线基板制备不同的阵列基板时，在一种阵列基板中用于使得第二金属布线层104与第一金属布线层102连接的过孔，在另一种阵列基板中可以依然用于使得第二金属布线层104与第一金属布线层102连接，也可以被绝缘保护层105所填充而不与第二金属布线层104交叠。当然地，当基于本公开的布线基板制备不同的阵列基板时，在一种阵列基板中被绝缘保护层105所填充且不与第二金属布线层104交叠的过孔，在另一种阵列基板中可以用于使得第二金属布线层104与第一金属布线层102连接，也可以依然被绝缘保护层105所填充而不与第二金属布线层104交叠。如此，本公开的布线基板的绝缘材料层103可以通过设置冗余过孔的方式，使得其能够适用于不同类型的阵列基板。
在本公开中，当描述两个结构交叠时，指的是一个结构在衬底基板上的正投影与另一个结构在衬底基板上的正投影存在重合部分。当描述两个结构完全交叠时，指的是其中一个结构在衬底基板上的正投影完全位于另一个结构在衬底基板上的正投影内。
在本公开的布线基板和阵列基板中，衬底基板101可以为无机材料的衬底基板，也可以为有机材料的衬底基板。举例而言，在本公开的一种实施方式中，衬底基板的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。
可选地，在本公开的一种实施方式中，衬底基板101可以为玻璃基板。
可选地，从图案和功能上，第一金属布线层102可以包括驱动引线和与驱动引线连接 的扇出引线。在本公开的一种实施方式中，第一金属布线层102还可以包括与扇出引线连接的绑定焊盘，可以理解的是，第一金属布线层中作为绑定焊盘的区域，表面没有任何其他绝缘膜层覆盖，以保证与印刷电路板等外部信号源电路实现电气连接。
从层级结构上，第一金属布线层102可以包括一层金属，也可以包括多层金属。示例性地，参见图48，第一金属布线层102可以包括依次层叠于衬底基板101一侧的铜种子层1021和铜生长层1022。其中，在一些实施方式中，铜生长层1022可以设置于铜种子层1021远离衬底基板101的表面，可以暴露铜种子层1021的至少部分侧面，例如铜种子层1021和铜生长层1022在衬底基板101上的正投影大致相重合。在另一些实施方式中，铜生长层1022可以完全包覆铜种子层1021的侧面和其远离衬底基板101的表面。
在一些实施方式中，铜种子层1021可以通过磁控溅射方法形成，铜生长层1022可以为通过电镀或者化学镀的方法形成。可选地，铜种子层1021可以包括依次层叠于衬底基板101一侧的第一金属粘附层和第一铜金属层，第一金属粘附层可以增强第一铜金属层与衬底基板101之间的结合力；第一金属粘附层的材料可以为含有钼的合金材料，例如可以为钼铌合金、钼铌铜合金等。可选的，第一金属布线层102还可以包括位于铜生长层1022远离衬底基板101的一侧的第一金属保护层，第一金属保护层可以避免铜生长层1022的表面被氧化；第一金属保护层的材料可以为含有镍或者钼的合金，例如可以为铜镍合金、钼铌合金、钼钛镍(MTD)合金等。在一些实施方式中，第一金属布线层102还可以包括位于第一金属布线层102远离衬底基板101一侧的表面的刻蚀阻挡层，以便在制备阵列基板的第二金属布线层104时减少或者避免对第一金属布线层102的刻蚀。刻蚀阻挡层的材料可以为导电金属氧化物，例如可以为氧化铟锌。
可以采用多种不同的方法制备第一金属布线层102。示例性地，在本公开的一种实施方式中，可以先形成覆盖衬底基板101的未图案化的铜种子层1021，然后采用电镀铜的方法沉积铜以形成未图案化的铜生长层1022，最后对图案化的铜种子层1021和未图案化的铜生长层1022进行图案化，以获得第一金属布线层102。再示例性地，在本公开的另一种实施方式中，可以先形成图案化的铜种子层1021，然后形成一覆盖衬底基板101且暴露铜种子层1021的图案限定层，再采用电镀铜的方法在图案化的铜种子层1021上形成图案化的铜生长层1022，获得第一金属布线层102；去除图案限定层。再示例性地，在本公开的另一种实施方式中，可以先形成覆盖衬底基板101的未图案化的铜种子层1021，然后在铜种子层1021远离衬底基板101的一侧形成图案限定层，图案限定层仅暴露需要形成铜生长层1022的位置；然后，通过电镀铜的方法在未图案化的铜种子层1021上形成图案化的铜生长层1022，去除图案限定层后对未图案化的铜种子层1021进行图案化，获得第一金属布线层102。
可以理解的是，第一金属布线层也可以通过多次磁控溅射的方法形成。示例性地，可以通过多次磁控溅射形成第一金属布线材料层，且每次磁控溅射形成的金属层的厚度不大于1微米；然后对第一金属布线材料层进行图案化，以形成第一金属布线层。再示例性地，可以依次形成多个图案相同的金属布线亚层，各个金属布线亚层依次层叠形成第一金属布线层。在形成任意一个金属布线亚层时，可以先通过磁控溅射形成一金属布线材料亚层，且金属布线材料亚层的厚度不大于1微米；然后对金属布线材料亚层进行图案化操作，以形成金属布线亚层。
可以理解的是，上述对第一金属布线层的结构、材料和制备方法的介绍仅为对第一金属布线层的示例性介绍；在本公开的其他实施方式中，第一金属布线层可以呈现出其他的膜层结构，或者采用其他的材料，或者采用其他的方法制备。
可选地，参见图48，绝缘材料层103可以包括平坦化有机材料层1032。平坦化有机材料层1032的材料可以为有机材料，例如可以为聚酰亚胺、环氧树脂、酚醛树脂或者其他有机材料。在本公开的一种实施方式中，平坦化有机材料层1032可以为含有光敏剂的 有机材料。平坦化有机材料层1032可以为阵列基板的第二金属布线层提供平坦化表面，并调整第一金属布线层和第二金属布线层之间的电容值。
可选地，参见图48，绝缘材料层103还可以包括第一钝化层1031，第一钝化层1031位于平坦化有机材料层1032和第一金属布线层102之间，用于保护第一金属布线层102。第一钝化层1031的材料可以为无机电介质材料，例如可以为氮化硅、氧化硅或者氮氧化硅。在本公开的一种实施方式中，第一钝化层1031的材料可以为氮化硅。
可选地，本公开的布线基板和阵列基板还可以包括缓冲层108，缓冲层108位于衬底基板101与第一金属布线层102之间，用于消除第一金属布线层102和绝缘材料层103对衬底基板101的应力。缓冲层108的材料可以为无机电介质材料，例如可以为氮化硅、氧化硅或者氮氧化硅。在本公开的一种实施方式中，缓冲层108的材料可以为氮化硅。
参见图49，在本公开提供的阵列基板中，可以包括本公开提供的布线基板，以及包括依次层叠于布线基板表面的第二金属布线层104和绝缘保护层105，以及包括有功能器件(图49中未示出)和微芯片(图49中未示出)。其中，第二金属布线层104位于绝缘材料层103远离衬底基板101的一侧，且通过位于绝缘材料层103上的过孔与第一金属布线层102连接。可以理解的是，在一些实施方式中，绝缘材料层103上的部分过孔并不用于第一金属布线层102和第二金属布线层104连接，且被绝缘保护层105所填充。换言之，在一种阵列基板中，绝缘材料层103上的至少部分过孔可以被绝缘保护层105所填充。
第二金属布线层104可以包括依次层叠设置的第二金属粘附层和第二铜金属层，第二金属粘附层用于增强第二铜金属层与平坦化有机材料层1032之间的结合力；第二金属粘附层的材料可以为含有钼的合金材料，例如可以为钼铌合金、钼铌铜合金等。进一步地，第二金属布线层104还可以包括位于第二铜金属层远离衬底基板101一侧的第二金属保护层，以避免第二铜金属层的表面被氧化，并用于提高功能器件和微芯片与第二金属布线层104之间的结合力。第二金属保护层的材料可以为含有镍的合金，例如可以为铜镍合金或者铜钛合金。其中，从图案和功能上，第二金属布线层104可以包括多个用于绑定功能器件的器件焊盘组、多个用于绑定微芯片的芯片焊盘组和多个连接引线500。其中，在阵列基板中，功能器件与器件焊盘组绑定连接，微芯片与芯片焊盘组绑定连接，器件焊盘组和芯片焊盘组与连接引线500连接。至少部分连接引线500通过设于绝缘材料层103上的至少部分过孔与第一金属布线层102连接。
可选地，这些连接引线500中的至少部分，可以沿第二方向D延伸，或者至少部分沿第二方向D延伸，以减少部分连接引线500与部分驱动引线之间的交叠长度，降低绝缘材料层103局部失效而产生短路不良的风险。进一步地，对于一些连接引线500，尤其对于与多个不同的驱动引线交叠的连接引线500，当连接引线500弯折时，连接引线500的至少部分引线段可以沿第二方向D延伸，其余引线段可以沿第一方向延伸。
示例性地，在一些实施方式中，参见图31至图33，与第一输入引线或者第二输入引线电连接的连接引线可以沿第二方向延伸且不经过弯折，以使得这些连接引线500的延伸方向与驱动引线的延伸方向垂直，进而使得这些连接引线可以减少与参考电压引线之间的交叠长度，降低出现短路不良的风险。再示例性地，在本公开的另一种实施方式中，参见图24至图26，与第一输入引线或者第二输入引线连接的连接引线可以沿第二方向延伸至与输入引线交叠的位置，然后弯折并沿第一方向继续延伸至输入过孔交叠。这些连接引线500的沿第二方向延伸的引线段与参考电压引线之间具有较小的交叠长度，因此可以避免升高阵列基板的短路不良。这些连接引线的沿第一方向延伸的引线段可以与第一输入引线或者第二输入引线交叠，因此即便发生短路也不会导致这些连接引线上的电位的改变，即不会表现出短路不良。
绝缘保护层105可以包括有机保护层1052，有机保护层1052可以包括有机绝缘材料，例如可以含有树脂材料。可选的，有机保护层1052中还可以包含有无机材料，例如可以 包括分散于树脂中的无机颗粒。示例性地，有机保护层1052可以为分散有纳米氧化钛颗粒的丙烯酸类单体交联固化而形成的有机-无机复合层。
可选地，绝缘保护层105还可以包括位于有机保护层1052与第二金属布线层104之间的第二钝化层1051。第二钝化层1051用于保护第二金属布线层104，其材料可以为无机电介质材料，例如可以为氮化硅、氧化硅或者氮氧化硅。在本公开的一种实施方式中，第二钝化层1051的材料可以为氮化硅。
绝缘保护层105上可以具有暴露器件焊盘组的各个子焊盘和芯片焊盘组的各个子焊盘的过孔，以便在阵列基板上绑定连接功能器件和微芯片。
在本公开中，阵列基板可以绑定有功能器件和微芯片，微芯片用于控制各个功能器件。其中，功能器件可以为电流驱动的元件，例如可以为发热元件、发光元件、发声元件等，也可以为实现感测功能的电子元件，例如光敏元件、热敏元件等。在一些实施方式中，功能器件可以为发光元件，例如可以为Micro LED或者Mini LED。在另外一些实施方式中，部分功能器件可以为发光元件，另外一部分功能器件可以为传感器，例如可以为温度传感器、压力传感器、红外传感器等电子元件。
参见图9、图15、图21、图27和图33，本公开提供的布线基板具有阵列分布的多个控制区域201，多个控制区域201排列成多个控制区域行210和多个控制区域列220。任意一个控制区域列220包括沿第一方向C排列的多个控制区域201，任意一个控制区域行210包括沿第二方向D排列的多个控制区域201；第二方向D平行于布线基板所在平面且与第一方向C相交。
可选地，第二方向D与第一方向C之间的夹角可以为85°～90°。在本公开的一种实施方式中，第二方向D与第一方向C之间垂直。
参见图9、图15、图21、图27和图33，任意一个控制区域201包括阵列分布的四个器件区A，器件区A用于设置相互电连接的功能器件107。在本公开的阵列基板中，在一个器件区A可以设置有器件控制电路，器件控制电路包括一个功能器件或者多个电连接的功能器件。示例性地，参见图11，在本公开的一种实施方式中，一个控制电路可以包括依次串联的四个发光元件。进一步地，参见图47，器件控制电路可以包括位于第二金属布线层104的连接引线500和与功能器件(图47中未示出)对应的器件焊盘组P50，器件焊盘组P50与连接引线500连接且与功能器件绑定连接。示例性地，在本公开的一种实施方式中，一个器件焊盘组P50包括成对设置的第一器件子焊盘P51和第二器件子焊盘P52，第一器件子焊盘P51和第二器件子焊盘P52分别用于与发光元件的正负电极绑定连接。
在一些实施方式中，布线基板上的各个器件区A，可以阵列分布。其中，2*2相邻的四个器件区A可以组成本公开的一个控制区域201。
参见图10、图16、图22、图28和图34，在一个控制区域201内，四个器件区A可以编号为第一器件区A(1,1)、第二器件区A(1,2)、第三器件区A(2,1)、第四器件区A(2,2)。其中，第一器件区A(1,1)为控制区域201内在第一方向C上位于第一行、在第二方向D上位于第一列的器件区A；第二器件区A(1,2)为控制区域201内在第一方向C上位于第一行、在第二方向D上位于第二列的器件区A；第三器件区A(2,1)为控制区域201内在第一方向C上位于第二行、在第二方向D上位于第一列的器件区A；第四器件区A(2,2)为控制区域201内在第一方向C上位于第二行、在第二方向D上位于第二列的器件区A。
参见图9、图15、图21、图27和图33，在本公开的布线基板和阵列基板中，第一金属布线层102设置有沿第一方向C延伸的驱动引线300。其中，在任意一个控制区域列220内，驱动引线300至少包括沿第二方向D依次排列的第一电源电压引线310、第一输入引线320、参考电压引线330、第二输入引线340和第二电源电压引线350。布线基板还具有至少一个沿第一方向C延伸的信号通道，且任意一个信号通道包括至少一个控制区域列 220；在任意一个信号通道中，驱动引线300至少还包括一个地址引线360。在一些实施方式中，一个信号通道包括一个控制区域列220。
第一电源电压引线310和第二电源电压引线350可以为布线基板和阵列基板的电源电压引线；第一输入引线320和第二输入引线340可以为布线基板和阵列基板的输入引线。绝缘材料层103可以设置有暴露电源电压引线(第一电源电压引线310或者第二电源电压引线350)部分区域的电源过孔，以便器件控制电路的一端通过电源过孔与电源电压引线连接。绝缘材料层103可以设置有暴露参考电压引线330部分区域的参考过孔，参考电压引线330通过参考过孔向微芯片的参考电压引脚供电。绝缘材料层103可以设置有暴露输入引线(第一输入引线320或者第二输入引线340)部分区域的输入过孔，以便微芯片的部分引脚通过输入过孔与输入引线连接。
参见图9、图15、图21、图27和图33，控制区域201可以包括第一控制区域2011。在一个第一控制区域2011，绝缘材料层103设置有第一至第六电源过孔、第一至第四输入过孔、第一参考过孔HR1和第二参考过孔HR2。
参见图10、图16、图22和图28，第一电源过孔HV1、第二电源过孔HV2和第三电源过孔HV3沿第一方向C依次排列且暴露第一电源电压引线310的部分区域；第一电源过孔HV1位于第一器件区A(1,1)远离第三器件区A(2,1)的一侧或者位于第一器件区A(1,1)和第三器件区A(2,1)之间；第二电源过孔HV2位于第一器件区A(1,1)和第三器件区A(2,1)之间；第三电源过孔HV3位于第三器件区A(2,1)远离第一器件区A(1,1)的一侧。第四电源过孔HV4、第五电源过孔HV5和第六电源过孔HV6沿第一方向C依次排列且暴露第二电源电压引线350的部分区域。第四电源过孔HV4位于第二器件区A(1,2)远离第四器件区A(2,2)的一侧或者位于第二器件区A(1,2)和第四器件区A(2,2)之间；第五电源过孔HV5位于第二器件区A(1,2)和第四器件区A(2,2)之间；第六电源过孔HV6位于第四器件区A(2,2)远离第二器件区A(1,2)的一侧。
在布线基板中，第一电源过孔HV1和第四电源过孔HV4的具体位置可以预先根据器件区A的器件控制电路的设置方式进行确定。器件区A内的器件控制电路可以具有第一端和第二端，其中第二端用于与微芯片电连接，第一端用于通过与电源过孔交叠的连接引线与电源电压引线连接。在尽量减小器件控制电路中的连接引线的长度的设计原则下，器件控制电路的第一端可以靠近器件区的一个顶角，且该顶角在第二方向上位于器件区远离参考电压引线的一侧。在第一器件区A(1,1)和第二器件区A(1,2)中，当该顶角在第一方向上位于器件区的第一方向一侧时，第一电源过孔HV1可以位于第一器件区A(1,1)靠近第三器件区A(2,1)的一侧，第四电源过孔HV4可以位于第二器件区A(1,2)靠近第四器件区A(2,2)的一侧。在第一器件区A(1,1)和第二器件区A(1,2)中，当该顶角在第一方向上位于器件区的第一方向的相反方向一侧时，第一电源过孔HV1可以位于第一器件区A(1,1)远离第三器件区A(2,1)的一侧，第四电源过孔HV4可以位于第二器件区A(1,2)远离第四器件区A(2,2)的一侧。
在一些实施方式中，器件区A设置有N*N个阵列分布且依次串联的功能器件107。当N为不小于2的偶数时，第一电源过孔HV1可以位于第一器件区A(1,1)靠近第三器件区A(2,1)的一侧，第四电源过孔HV4可以位于第二器件区A(1,2)靠近第四器件区A(2,2)的一侧。当N为不小于2的奇数时，第一电源过孔HV1可以位于第一器件区A(1,1)远离第三器件区A(2,1)的一侧，第四电源过孔HV4可以位于第二器件区A(1,2)远离第四器件区A(2,2)的一侧。这样，可以尽量简化第一器件区A(1,1)和第二器件区A(1,2)内的连接引线500的设置方式。可以理解的是，由于第二电源过孔HV2和第三电源过孔HV3位于第三器件区A(2,1)的两侧，因此第三器件区A(2,1)内的器件控制电路可以根据连接引线500的布线要求来连接至第二电源过孔HV2和第三电源过孔HV3中的一个。相应地，由于第五电源过孔HV5和第六电源过孔HV6位于第四器件区A (2,2)的两侧，因此第四器件区A(2,2)内的器件控制电路可以根据连接引线500的布线要求来连接至第五电源过孔HV5和第六电源过孔HV6中的一个。
在另外的一些实施方式中，本公开的布线基板在第一控制区域2011设置有两个第一电源过孔HV1和两个第四电源过孔HV4。其中，两个第一电源过孔HV1分别位于第一器件区A(1,1)的两侧，两个第四电源过孔HV4分别位于第二器件区A(1,2)的两侧。这样，阵列基板可以根据第二金属布线层的布线需要，选择其中一个第一电源过孔HV1用于实现第一器件区A(1,1)内的器件控制电路与第一电源电压引线310的电连接，选择其中一个第四电源过孔HV4用于实现第二器件区A(1,2)内的器件控制电路与第五电源电压引线350的电连接。
第一输入过孔HI1和第二输入过孔HI2暴露第一输入引线320的部分区域；第一输入过孔HI1位于第一器件区A(1,1)远离第三器件区A(2,1)的边缘与第三器件区A(2,1)靠近第一器件区A(1,1)的边缘之间；第二输入过孔HI2位于第三器件区A(2,1)远离第一器件区A(1,1)的一侧。第三输入过孔HI3和第四输入过孔HI4暴露第二输入引线340的部分区域。第三输入过孔HI3位于第二器件区A(1,2)远离第四器件区A(2,2)的边缘与第四器件区A(2,2)靠近第二器件区A(1,2)的边缘之间；第四输入过孔HI4位于第四器件区A(2,2)远离第二器件区A(1,2)的一侧。
第一参考过孔HR1和第二参考过孔HR2均暴露参考电压引线330的部分区域；沿第一方向C，第一参考过孔HR1位于第一器件区A(1,1)与第三器件区A(2,1)之间，第二参考过孔HR2位于第三器件区A(2,1)远离与第一器件区A(1,1)的一侧。
在任意一个信号通道区域，绝缘材料层103还设置有暴露地址引线360的部分区域的至少一个地址过孔。
可选地，参见图50，布线基板还可以具有扇出区和绑定区B，其中，第一金属布线层102在扇出区设置有与各个驱动引线300一一对应连接的扇出引线400，绑定区B设置有与各个扇出引线400一一对应连接的绑定焊盘。参见图50，在本公开的一种实施方式中，扇出引线400和绑定焊盘位于对应的驱动引线300的第一方向C一侧；即，沿第一方向C，绑定区B位于布线基板的末端。在本公开的另一种实施方式中，驱动引线位于对应的扇出引线和绑定焊盘的第一方向C一侧；即，沿第一方向C，绑定区B位于布线基板的起始端。
在一些实施方式中，绑定区B可以靠近布线基板的一边缘设置，例如位于布线基板在第一方向C上的边缘或者第一方向C的相反方向上的边缘。本公开的布线基板和阵列基板在绑定区B内可以设置有至少一排绑定焊盘。进一步地，同一排绑定焊盘中，各个绑定焊盘可以沿第二方向D排列。在本公开的一种实施方式中，各个绑定焊盘沿第二方向D排列为一排，且与各个驱动引线300一一对应设置。
可选地，相邻两个信号通道中的相邻两个电源电压引线所对应连接的两个绑定焊盘，相互连接为一个整体。更进一步地，与相邻的两个电源电压引线连接的两个扇出引线400，也可以相互连接而成为一个整体。如此，相当于相邻两个电源电压引线通过同一扇出引线400连接至同一绑定焊盘。可选的，绑定区设置有沿第二方向D等间距设置的多个绑定电极，且各个绑定电极的宽度相同。一个或者多个相邻的绑定电极可以连接至同一扇出引线，在整体上作为与该绑定引线连接的绑定焊盘。当一个绑定焊盘所包括的绑定电极的数量越多，则该绑定焊盘的宽度越大。
本公开提供的布线基板，可以适用于至少两种不同的微芯片，以制备出具有不同微芯片的不同的阵列基板。这些阵列基板包括本公开提供的布线基板，以及层叠于布线基板的绝缘材料层103远离衬底基板101一侧的第二金属布线层104和绝缘保护层105，且还绑定有微芯片和功能器件。
可选地，在基于本公开的布线基板的阵列基板中，在第一控制区域2011，第二电源过 孔HV2和第三电源过孔HV3中的一个用于与连接引线500交叠，以使得第三器件区A(2,1)中的器件控制电路与第一电源电压引线310连接；另一个可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。第五电源过孔HV5和第六电源过孔HV6中的一个用于与连接引线500交叠，以使得第四器件区A(2,2)中的器件控制电路与第二电源电压引线350连接；另一个可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
本公开提供的布线基板，可以用于制备具有第一芯片的阵列基板，例如可以用于制备第一阵列基板。其中，第一阵列基板的衬底基板101、第一金属布线层102和绝缘材料层103的形成该实施方式中的布线基板。图11示出了一种第一阵列基板在一个第一控制区域2011内的结构示意图；其中，图11仅仅示出了驱动引线300、绝缘材料层103所设置的至少部分过孔的位置、连接引线500(用粗线条表示)、用于绑定第一芯片的第一焊盘组P10、各个器件区A内的功能器件107等。
参见图11，该第一阵列基板在一个第一控制区域2011内，可以设置有与四个器件区A一一对应的四个第一焊盘组P10；任意一个第一焊盘组P10位于对应的器件区A的第一方向C一侧。第二器件区A(1,2)对应的第一焊盘组P10位于第一器件区A(1,1)对应的第一焊盘组P10的第二方向D一侧；第四器件区A(2,2)对应的第一焊盘组P10位于第三器件区A(2,1)对应的第一焊盘组P10的第二方向D一侧。
在该第一阵列基板的第一控制区域2011中，第一器件区A(1,1)对应的第一焊盘组P10的参考电压子焊盘P11和第二器件区A(1,2)对应的第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间，通过与第一参考过孔HR1交叠的连接引线500连接。
第三器件区A(2,1)对应的第一焊盘组P10的参考电压子焊盘P11和第四器件区A(2,2)对应的第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间，通过与第二参考过孔HR2交叠的连接引线500连接。这可以使得各个第一焊盘组P10的参考电压子焊盘P11均与参考电压引线330电连接。进一步地，在该第一阵列基板的第一控制区域2011中，与第一参考过孔HR1交叠的连接引线500和与第二参考过孔HR2交叠的连接引线500，其在第一金属布线层102上的正投影均不超出参考电压引线330的范围内。如此，即便绝缘材料层103发生布局失效而使得这些连接引线500与参考电压引线330发生短路，也不会改变这些引线上的电压而引起不良。
在第一阵列基板的一个信号通道内，各个器件区A可以依次编号，其中编号为1的器件区A对应的第一焊盘组P10可以位于该信号通道在其延伸方向上的一端，例如可以位于靠近绑定区B的一端或者位于远离绑定区B的一端。在该信号通道内，各个器件区A对应的第一焊盘组P10可以按照Z形逐行逐列依次编号，或者按照S形逐行逐列依次编号，或者按照N形逐列逐行依次编号，或者按照U形或者倒U形逐列逐行依次编号。其中，在本公开中，行方向为沿第二方向D或者其相反方向的方向，列方向为沿第一方向C或者其相反方向的方向。在一个信号通道内，各个器件区A对应第一焊盘组P10可以按照编号顺序依次级联，其中，编号为1的器件区A对应的第一焊盘组P10的第二输入子焊盘P14与其中一个地址引线360之间，通过与地址过孔交叠的连接引线50连接。编号为(n-1)的器件区A对应的第一焊盘组P10的输出子焊盘P12与编号为n的器件区A对应的第一焊盘组P10的第二输入子焊盘P14通过连接引线500连接。n为大于1的整数且不大于一个信号通道内的器件区的数量。
举例而言，在第一阵列基板的一种实施方式中，第一器件区A(1,1)对应的第一焊盘组P10、第二器件区A(1,2)对应的第一焊盘组P10、第三器件区A(2,1)对应的第一焊盘组P10和第四器件区A(2,2)对应的第一焊盘组P10依次级联。其中，第一器件区A(1,1)对应的第一焊盘组P10的输出子焊盘P12与第二器件区A(1,2)对应的第一焊盘组P10的第二输入子焊盘P14连接，第二器件区A(1,2)对应的第一焊盘组P10的输出子焊盘P12与第三器件区A(2,1)对应的第一焊盘组P10的第二输入子焊盘P14连接， 第三器件区A(2,1)对应的第一焊盘组P10的输出子焊盘P12与第四器件区A(2,2)对应的第一焊盘组P10的第二输入子焊盘P14连接。在相邻的两个控制区域201中，位于第一方向C的相反方向一侧的控制区域201的第四器件区A(2,2)对应的第一焊盘组P10的输出子焊盘P12，与位于第一方向C一侧的控制区域201的第一器件区A(1,1)对应的第一焊盘组P10的第二输入子焊盘P14连接。
参见图11，第一阵列基板在器件区A内设置有器件控制电路，其中，器件控制电路的第一端与电源电压引线之间通过与电源过孔交叠的连接引线500连接；器件控制电路的第二端与该器件区A对应的第一焊盘组P10的输出子焊盘P12之间，通过连接引线500连接。参见图47，器件控制电路的第一端可以为位于电源电压引线上的一个器件焊盘组P50中的第一器件子焊盘P51，器件控制电路的第二端可以为在第一方向C上靠近对应的第一芯片010且在第二方向D上靠近参考电压引线330的轴线的一个器件焊盘组P50中的第二器件子焊盘P52。如此，可以尽量减少连接第一芯片010的输出引脚012与器件控制电路的第二端之间的连接引线500的长度，减少这些连接引线500与参考电压引线330之间的交叠长度，进而降低这些连接引线500与参考电压引线330之间发生短路不良的风险。
举例而言，在本公开的一种实施方式中，在一个器件区A内设置有串联且呈2*2阵列分布的四个发光元件；其中，第一个发光元件与电源电压引线之间通过与电源过孔交叠的连接引线500连接，第四个发光元件与第一焊盘组P10的输出子焊盘P12之间通过连接引线500连接。串联四个发光元件的三根连接引线500，在整体是呈开口朝向第一方向C的凵字型分布。在该实施方式中，在第一控制区域2011内，第一电源过孔HV1可以设置于第一器件区A(1,1)的第一方向C一侧，第四电源过孔HV4可以设置于第二器件区A(1,2)的第一方向C一侧。第一器件区A(1,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV1交叠的连接引线500连接。第二器件区A(1,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第四电源过孔HV4交叠的连接引线500连接。第三器件区A(2,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第三电源过孔HV3交叠的连接引线500连接。第四器件区A(2,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第六电源过孔HV6交叠的连接引线500连接。
在第一控制区域2011内，第一器件区A(1,1)对应的第一焊盘组P10的第一输入子焊盘P13与第一输入引线320之间，通过与第一输入过孔HI1交叠的连接引线500连接；第三器件区A(2,1)对应的第一焊盘组P10的第一输入子焊盘P13与第一输入引线320之间，通过与第二输入过孔HI2交叠的连接引线500连接；第二器件区A(1,2)对应的第一焊盘组P10的第一输入子焊盘P13与第二输入引线340之间，通过与第三输入过孔HI3交叠的连接引线500连接；第四器件区A(2,2)对应的第一焊盘组P10的第一输入子焊盘P13与第二输入引线340之间，通过与第四输入过孔HI4交叠的连接引线500连接。
该第一阵列基板中，第一电源电压引线310和第二电源电压引线350可以用于加载驱动器件控制电路的电源电压VLED，例如加载驱动器件控制电路中的各个发光元件发光的电源电压VLED。参考电压引线330可以用于加载参考电压GND。第一输入引线320和第二输入引线340中的一个可以用于加载第一输入信号Pwr。在一个信号通道内，至少一个地址引线360可以用于加载第二输入信号Di。如此，在各个驱动引线300的控制下，各个第一芯片010和功能器件107可以正常工作。
在本公开的一些实施方式中，参见图39，布线基板相邻的输入引线(例如第一输入引线320和第二输入引线340)和参考电压引线330中，输入引线设置有向参考电压引线330一侧凸出的凸出部301，且参考电压引线330设置有与参考电压引线330的凸出部301相对应且能够容置该凸出部301的容置缺口302。相应的，在第一阵列基板中，第一焊盘 组P10可以靠近该凸出部301设置，使得第一焊盘组P10的第一输入子焊盘P13在第一金属布线层102上的正投影位于输入引线的凸出部301上，且使得第一焊盘组P10的参考电压子焊盘P11在第一金属布线层102上的正投影位于参考电压引线330上。换言之，参见图39，输入引线的凸出部301的至少部分可以作为第一支撑金属部303，第一支撑金属部303可以与第一焊盘组P10的输入子焊盘完全交叠；参考电压引线330靠近容置缺口302的至少部分可以作为第二支撑金属部304，第二支撑金属部304可以与第一焊盘组P10的参考电压子焊盘P11完全交叠。与参考电压子焊盘P11连接且与参考过孔交叠的连接引线500，可以参考电压引线330完全交叠。如此，绝缘材料层103的绝缘失效而导致的短路不良风险被进一步降低。
进一步地，参见图39，在布线基板中，第一金属布线层102还可以设置有第三支撑金属部305和第四支撑金属部306，第三支撑金属部305和第四支撑金属部306均位于输入引线和参考电压引线330之间，且与输入引线和参考电压引线330绝缘设置。其中，第三支撑金属部305在衬底基板101上的正投影，与输出子焊盘P12在衬底基板101上的正投影重合；第二支撑金属部304在衬底基板101上的正投影，与第二输入子焊盘P14在衬底基板101上的正投影重合。这样，可以使得第一焊盘组P10的各个子焊盘与衬底基板101的距离基本相同，利于第一芯片010的绑定。
本公开提供的布线基板，还可以用于制备具有第二芯片020的阵列基板，例如可以用于制备第二阵列基板。其中，第二阵列基板的衬底基板101、第一金属布线层102和绝缘材料层103的形成该实施方式中的布线基板。图12示出了一种第二阵列基板在一个第一控制区域2011内的结构示意图；其中，图12仅仅示出了驱动引线300、绝缘材料层103所设置的各个过孔的位置、连接引线500(用粗线条表示)、用于绑定第二芯片020的第二焊盘组P20、各个器件区A内的功能器件107等。
参见图12，该第二阵列基板在一个第一控制区域2011内可以设置有一个用于绑定第二芯片020的第二焊盘组P20，第二焊盘组P20可以位于第一控制区域2011内的四个器件区A之间。换言之，在一个第一控制区域2011内，在沿第一方向C上，第二焊盘组P20位于第一器件区A(1,1)与第三器件区A(2,1)之间；在沿第二方向D上，第二焊盘组P20位于第一器件区A(1,1)与第二器件区A(1,2)之间。其中，第二焊盘组P20的参考电压子焊盘P21位于第二焊盘组P20的地址子焊盘P25的第一方向C一侧，以保证与第二焊盘组P20的参考电压子焊盘P21连接的连接引线500能够延伸至与第二参考过孔HR2交叠，且该连接引线500与参考电压引线330完全交叠。这样，在该连接引线500与参考电压引线330短路时，第二阵列基板可以避免呈现不良。其中，芯片电源子焊盘P23和驱动数据子焊盘P24中的一个，与第一输入引线320之间通过与第一输入过孔HI1交叠的连接引线500连接；另一个与第二输入引线340之间，通过与第三输入过孔HI3交叠的连接引线500连接。四个输入子焊盘，分别与四个器件区内的器件控制电路的第二端通过连接引线500连接。
可选地，参见图12，在该第二阵列基板中，第二焊盘组P20的芯片电源子焊盘P23位于驱动数据子焊盘P24的第二方向D的相反方向一侧。如此，第二焊盘组P20的芯片电源子焊盘P23与第一输入引线320之间，可以通过用于第一输入过孔HI1交叠的连接引线500连接；第二焊盘组P20的驱动数据子焊盘P24与第二输入引线340之间，可以通过用于第三输入过孔HI3交叠的连接引线500连接。第二焊盘组P20的地址子焊盘P25与地址引线360之间，可以通过与地址过孔交叠的连接引线500连接。
参见图12，在该第二阵列基板的第一控制区域2011中，第一器件区A(1,1)中的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV1交叠的连接引线500连接；第一器件区A(1,1)中的器件控制电路的第二端与第二焊盘组P20的第一输出子焊盘P221之间，通过连接引线500连接。第二器件区A(1,2)中的器件控制 电路的第一端与第二电源电压引线350之间，通过与第四电源过孔HV4交叠的连接引线500连接；第二器件区A(1,2)中的器件控制电路的第二端与第二焊盘组P20的第二输出子焊盘P222之间，通过连接引线500连接。第三器件区A(2,1)中的器件控制电路的第一端与第一电源电压引线310之间，通过与第二电源过孔HV2或者第三电源过孔HV3交叠的连接引线500连接；第三器件区A(2,1)中的器件控制电路的第二端与第二焊盘组P20的第三输出子焊盘P223之间，通过连接引线500连接。第四器件区A(2,2)中的器件控制电路的第一端与第二电源电压引线320之间，通过与第五电源过孔HV5或者第六电源过孔HV6交叠的连接引线500连接；第四器件区A(2,2)中的器件控制电路的第二端与第二焊盘组P20的第四输出子焊盘P224之间，通过连接引线500连接。其中，器件控制电路的第一端可以为位于电源电压引线上的一个器件焊盘组P50中的一个子焊盘，器件控制电路的第二端可以为在第一方向C上靠近第二芯片020且在第二方向D上靠近参考电压引线330的轴线的一个器件焊盘组P50中的一个子焊盘。这可以尽量减少第二芯片020的输出引脚012与器件控制电路的第二端之间的连接引线500的长度，减少这些连接引线500与参考电压引线330之间的交叠长度，进而降低这些连接引线500与参考电压引线330之间发生短路不良的风险。
可选地，在至少部分控制区域内，第一器件区A(1,1)内的器件控制电路存在连接各个功能器件的连接引线，第三器件区A(2,1)内的器件控制电路存在连接各个功能器件的连接引线，第一器件区A(1,1)的这些连接引线与第三器件区A(2,1)内的这些连接引线关于一对称轴对称，且该对称轴平行于第二方向。第二器件区A(1,2)内的器件控制电路存在连接各个功能器件的连接引线，第四器件区A(2,2)内的器件控制电路存在连接各个功能器件的连接引线，第二器件区A(1,2)的这些连接引线与第四器件区A(2,2)内的这些连接引线关于一对称轴对称，且该对称轴平行于第二方向。
示例性地，在本公开的一种实施方式中，在一个器件区A内设置有串联且呈2*2阵列分布的四个发光元件；其中，第一个发光元件与电源电压引线之间，通过与电源过孔交叠的连接引线500连接；第四个发光元件通过连接引线500连接至第二焊盘组P20的输出子焊盘P12。在第一器件区A(1,1)和第二器件区A(1,2)中，串联四个发光元件的三根连接引线500，在整体是呈开口朝向第一方向C的凵字型分布。在第三器件区A(2,1)和第四器件区A(2,2)中，串联四个发光元件的三根连接引线500，在整体是呈开口朝向第一方向C的相反方向的凵字型分布。在该实施方式中，在第一控制区域2011内，第一电源过孔HV1可以设置于第一器件区A(1,1)的第一方向C一侧，第四电源过孔HV4可以设置于第二器件区A(1,2)的第一方向C一侧。第一器件区A(1,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV1交叠的连接引线500连接。第三器件区A(2,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第二电源过孔HV2交叠的连接引线500连接。第二器件区A(1,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第四电源过孔HV4交叠的连接引线500连接。第四器件区A(2,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第五电源过孔HV5交叠的连接引线500连接。
该第二阵列基板中，第一电源电压引线310和第二电源电压引线350可以用于加载驱动器件控制电路的电源电压VLED，例如加载驱动器件控制电路中的各个发光元件发光的电源电压VLED。参考电压引线330可以用于加载参考电压GND。第一输入引线320可以用于加载芯片工作电压VCC，第二输入引线340可以用于加载驱动数据Data。至少部分地址引线360可以用于加载选通信号。如此，在各个驱动引线300的控制下，各个第二芯片020和功能器件107可以正常工作。
可选地，在该第二阵列基板的第一控制区域2011中，第一参考过孔HR1、第二输入过孔HI2、第四输入过孔HI4可以不与任何第二金属布线层104交叠，且被绝缘保护层105 填充。
本公开提供的布线基板，可以用于制备具有第三芯片030的阵列基板，例如可以用于制备第三阵列基板。其中，第三阵列基板的衬底基板101、第一金属布线层102和绝缘材料层103的形成该实施方式中的布线基板。示例性地，图13示出了一种第三阵列基板在一个第一控制区域2011内的结构示意图；其中，图13仅仅示出了驱动引线300、绝缘材料层103所设置的各个过孔的位置、连接引线500(用粗线条表示)、用于绑定第三芯片030的第三焊盘组P30、各个器件区A内的功能器件107等。
参见图13，该第三阵列基板在一个第一控制区域2011内可以设置有一个用于绑定第三芯片030的第三焊盘组P30，第三焊盘组P30可以位于第一控制区域2011内的四个器件区A之间。换言之，在一个第一控制区域2011内，在沿第一方向C上，第三焊盘组P30位于第一器件区A(1,1)与第三器件区A(2,1)之间；在沿第二方向D上，第三焊盘组P30位于第一器件区A(1,1)与第二器件区A(1,2)之间。可选地，第三焊盘组P30的参考电压子焊盘P31位于第三焊盘组P30的中继信号子焊盘P36的第一方向C一侧，这更利于第三焊盘组P30的参考电压子焊盘P31连接的连接引线500延伸至与第二参考过孔HR2交叠，且该连接引线500与参考电压引线330完全交叠。这样，在该连接引线500与参考电压引线330短路时，第三阵列基板可以避免呈现不良。
该第三阵列基板的一个第一控制区域2011内，参考电压子焊盘P31与参考电压引线330之间可以通过与第二参考过孔HR2交叠的连接引线500连接；芯片电源子焊盘P33和驱动数据子焊盘P34中的一个与第一输入引线320之间通过与第一输入过孔HI1交叠的连接引线500连接，另一个与第二输入引线340之间通过与第三输入过孔HI3交叠的连接引线500连接。
示例性地，参见图13，在该第三阵列基板中，第三焊盘组P30的芯片电源子焊盘P33位于驱动数据子焊盘P34的第二方向D的相反方向一侧。如此，第三焊盘组P30的芯片电源子焊盘P33与第一输入引线320之间，通过与第一输入过孔HI1交叠的连接引线500连接。第三焊盘组P30的驱动数据子焊盘P34与第二输入引线340之间，通过与第三输入过孔HI3交叠的连接引线500连接。
参见图13，在该第三阵列基板的第一控制区域2011中，第一器件区A(1,1)中的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV1交叠的连接引线500连接；第一器件区A(1,1)中的器件控制电路的第二端通过连接引线500与第三焊盘组P30的第一输出子焊盘P321连接。第二器件区A(1,2)中的器件控制电路的第一端与第二电源电压引线350之间，通过与第四电源过孔HV4交叠的连接引线500连接；第二器件区A(1,2)中的器件控制电路的第二端通过连接引线500与第三焊盘组P30的第二输出子焊盘P322连接。第三器件区A(2,1)中的器件控制电路的第一端与第一电源电压引线310之间，通过与第二电源过孔HV2和第三电源过孔HV3中的一个交叠的连接引线500连接；第三器件区A(2,1)中的器件控制电路的第二端通过连接引线500与第三焊盘组P30的第三输出子焊盘P323连接。第四器件区A(2,2)中的器件控制电路的第一端与第二电源电压引线350之间，通过与第五电源过孔HV5和第六电源过孔HV6中的一个交叠的连接引线500连接；第四器件区A(2,2)中的器件控制电路的第二端通过连接引线500与第三焊盘组P30的第四输出子焊盘P324连接。其中，器件控制电路的第一端可以为位于电源电压引线上的一个器件焊盘组P50中的一个子焊盘，器件控制电路的第二端可以为在第一方向C上靠近第三芯片030且在第二方向D上靠近参考电压引线330的轴线的一个器件焊盘组P50中的一个子焊盘。这可以尽量减少第三芯片030的输出引脚与器件控制电路的第二端之间的连接引线500的长度，减少这些连接引线500与参考电压引线330之间的交叠长度，进而降低这些连接引线500与参考电压引线330之间发生短路不良的风险。
可选地，在至少部分控制区域内，第一器件区A(1,1)内的器件控制电路存在连接各个功能器件的连接引线，第三器件区A(2,1)内的器件控制电路存在连接各个功能器件的连接引线，第一器件区A(1,1)的这些连接引线与第三器件区A(2,1)内的这些连接引线关于一对称轴对称，且该对称轴平行于第二方向。第二器件区A(1,2)内的器件控制电路存在连接各个功能器件的连接引线，第四器件区A(2,2)内的器件控制电路存在连接各个功能器件的连接引线，第二器件区A(1,2)的这些连接引线与第四器件区A(2,2)内的这些连接引线关于一对称轴对称，且该对称轴平行于第二方向。
示例性地，参见图13，在本公开的一种实施方式中，在一个器件区A内设置有串联且呈2*2阵列分布的四个发光元件；其中，第一个发光元件与电源电压引线之间，通过与电源过孔交叠的连接引线500连接；第四个发光元件通过连接引线500连接至第三焊盘组P30的输出子焊盘。在第一器件区A(1,1)和第二器件区A(1,2)中，串联四个发光元件的三根连接引线500，在整体是呈开口朝向第一方向C的凵字型分布。在第三器件区A(2,1)和第四器件区A(2,2)中，串联四个发光元件的三根连接引线500，在整体是呈开口朝向第一方向C的相反方向的凵字型分布。在该实施方式中，在第一控制区域2011内，第一电源过孔HV1可以设置于第一器件区A(1,1)的第一方向C一侧，第四电源过孔HV4可以设置于第二器件区A(1,2)的第一方向C一侧。第一器件区A(1,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV1交叠的连接引线500连接。第三器件区A(2,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV2交叠的连接引线500连接。第二器件区A(1,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第四电源过孔HV4交叠的连接引线500连接。第四器件区A(2,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第五电源过孔HV5交叠的连接引线500连接。
在该第三阵列基板的一个信号通道内，各个控制区域201可以依次编号，其中，编号为1的控制区域201可以位于该信号通道在其延伸方向上的一端，例如可以位于靠近绑定区B的一端或者位于远离绑定区B的一端。当一个信号通道内仅具有一个控制区域列220时，各个控制区域201可以沿第一方向C或者第一方向C的相反方向依次编号。当一个信号通道内具有多个控制区域列220时，在该信号通道内，各个控制区域201可以按照Z形逐行逐列依次编号，或者按照S形逐行逐列依次编号，或者按照N形逐列逐行依次编号，或者按照U形或者倒U形逐列逐行依次编号。在一个信号通道内，各个控制区域201中的第三焊盘组P30可以按照控制区域201的编号顺序依次级联，其中，编号为1的控制区域201中的第三焊盘组P30的选通信号子焊盘P35与地址引线360之间，通过与地址过孔交叠的连接引线500连接。编号为(n-1)的控制区域201中的第三焊盘组P30的中继信号子焊盘P36与编号为n的控制区域201中的第三焊盘组P30的选通信号子焊盘P35通过连接引线500连接。如此，该第三阵列基板在一个信号通道内，可以实现各个第三芯片030的相互级联，进而实现对该信号通道内的各个器件控制电路的控制。n为大于1的正整数，且不大于一个信号通道内的控制区域的数量。
在该第三阵列基板中，第一电源电压引线310和第二电源电压引线350可以用于加载驱动器件控制电路的电源电压VLED，例如加载驱动器件控制电路中的各个发光元件发光的电源电压VLED。参考电压引线330可以用于加载参考电压GND。第一输入引线320可以用于加载芯片工作电压VCC，第二输入引线340可以用于加载驱动数据Data。在一个信号通道内，与第一级控制区域201的第三焊盘组P30连接的地址引线360，可以加载选通信号。如此，在各个驱动引线300的控制下，各个第三芯片030和功能器件107可以正常工作。
可选地，在该第三阵列基板的第一控制区域2011中，第一参考过孔HR1、第二输入过孔HI2、第四输入过孔HI4可以不与任何第二金属布线层104交叠，且被绝缘保护层105 填充。
本公开提供的布线基板，还可以用于制备具有第四芯片040的阵列基板，例如可以用于制备第四阵列基板。其中，第四阵列基板的衬底基板101、第一金属布线层102和绝缘材料层103的形成该实施方式中的布线基板。示例性地，图14示出了一种第四阵列基板在一个第一控制区域2011内的结构示意图；其中，图14仅仅示出了驱动引线300、绝缘材料层103所设置的各个过孔的位置、连接引线500(用粗线条表示)、用于绑定第四芯片040的第四焊盘组P40、各个器件区A内的功能器件107等。
参见图14，该第四阵列基板在一个第一控制区域2011内可以设置有一个用于绑定第四芯片040的第四焊盘组P40，第四焊盘组P40可以位于第一控制区域2011内的四个器件区A之间。换言之，在一个第一控制区域2011内，在沿第一方向C上，第四焊盘组P40位于第一器件区A(1,1)与第三器件区A(2,1)之间；在沿第二方向D上，第四焊盘组P40位于第一器件区A(1,1)与第二器件区A(1,2)之间。其中，该第四焊盘组P40的芯片电源子焊盘P43和驱动数据子焊盘P44沿第二方向D或者其相反方向排列，以使得第四焊盘组P40具有两列子焊盘，且每列子焊盘具有沿第一方向C排列的五个子焊盘。这可以简化第四阵列基板的连接引线500的设计，减小连接引线500的长度进而减小连接引线500与第一金属布线层102的驱动引线300之间发生短路的几率。参见图14，在第二方向D或者其相反方向上，相较于第四焊盘组P40的选通信号子焊盘P45，第四焊盘组P40的参考电压子焊盘P41位于靠近第一参考过孔HR1的一侧。如此，可以保证与第四焊盘组P40的参考电压子焊盘P41连接的连接引线500能够延伸至与第一参考过孔HR1或者第二参考过孔HR2交叠。
示例性地，参见图14，相较于第二电源电压引线350，第一参考过孔HR1靠近第一电源电压引线310。如此，第四焊盘组P40包括两列子焊盘，靠近第一电源电压引线310的五个子焊盘沿第一方向C依次为第四输出子焊盘P424、参考电压子焊盘P41、驱动数据子焊盘P44、参考电压子焊盘P41和第二输出子焊盘P422，靠近第二电源电压引线350的五个子焊盘沿第一方向C依次为第三输出子焊盘P423、选通信号子焊盘P45、芯片电源子焊盘P43、中继信号子焊盘P46、第一输出子焊盘P421。
可选地，参见图14，在该第四阵列基板的第一控制区域2011中，第四焊盘组P40的靠近第一参考过孔HR1的参考电压子焊盘P41与参考电压引线330之间，通过与第一参考过孔HR1交叠的连接引线500连接；该连接引线500可以与参考电压引线330完全交叠。在该第四阵列基板的第一控制区域2011中，第四焊盘组P40的远离第一参考过孔HR1的参考电压子焊盘P41与参考电压引线330之间，通过与第二参考过孔HR2交叠的连接引线500连接。
在本公开的一种实施方式中，两个参考电压子焊盘P41中，可以仅一个参考电压子焊盘与参考电压引线330电连接，另一个参考电压子焊盘P41可以不与参考电压引线330电连接。如此，第四芯片040可以通过一个参考电压子焊盘P41获得参考电压，可以满足第四芯片040的工作需求。在该实施方式中，在两个参考电压子焊盘P41中，可以使得靠近第一参考过孔HR1的参考电压子焊盘P41与参考电压引线330电连接。
可选地，参见图14，在该第四阵列基板的第一控制区域2011中，第四焊盘组P40的芯片电源子焊盘P43和驱动数据子焊盘P44中靠近第一输入引线320的子焊盘与第一输入引线320之间，通过与第一输入过孔HI1交叠的连接引线500连接；远离第一输入引线320的子焊盘与第二输入引线340之间，通过与第三输入过孔HI3交叠的连接引线500连接。如此，可以尽量减小这些连接引线500的长度，减少这些连接引线500与参考电压引线330短路的风险。
示例性地，在本公开的一种实施方式中，参见图14，在该第四阵列基板的第一控制区域2011中，驱动数据子焊盘P44与第一输入引线320之间，通过与第一输入过孔HI1 交叠的连接引线500连接；芯片电源子焊盘P43与第二输入引线340之间，通过与第四输入过孔HI4交叠的连接引线500连接。
在该第四阵列基板的第一控制区域2011中，四个器件区A的器件控制电路的第一端与电源电压引线之间，通过与电源过孔交叠的连接引线500连接。四个器件区A的器件控制电路的第二端一一对应的通过连接引线500连接至第四焊盘组P40的四个输出子焊盘。其中，器件控制电路的第二端连接至距离其最近的输出子焊盘。
在本公开的一种实施方式中，参见图14，在该第四阵列基板的第一控制区域2011中，第一器件区A(1,1)中的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV1交叠的连接引线500连接；第一器件区A(1,1)中的器件控制电路的第二端通过连接引线500与第四焊盘组P40的第四输出子焊盘P424连接。第三器件区A(2,1)中的器件控制电路的第一端与第一电源电压引线310之间，通过与第二电源过孔HV2和第三电源过孔HV3中的一个交叠的连接引线500连接；第三器件区A(2,1)中的器件控制电路的第二端通过连接引线500与第四焊盘组P40的第二输出子焊盘P422连接。第二器件区A(1,2)中的器件控制电路的第一端与第二电源电压引线350之间，通过与第四电源过孔HV4交叠的连接引线500连接；第二器件区A(1,2)中的器件控制电路的第二端通过连接引线500与第四焊盘组P40的第三输出子焊盘P423连接。第四器件区A(2,2)中的器件控制电路的第一端与第二电源电压引线350之间，通过与第五电源过孔HV5和第六电源过孔HV6中的一个交叠的连接引线500连接；第四器件区A(2,2)中的器件控制电路的第二端通过连接引线500与第四焊盘组P40的第一输出子焊盘P421连接。其中，器件控制电路的第一端可以为位于电源电压引线上的一个器件焊盘组P50中的一个子焊盘，器件控制电路的第二端可以为在第一方向C上靠近第四焊盘组P40且在第二方向D上靠近参考电压引线330的轴线的一个器件焊盘组P50中的一个子焊盘。这可以尽量减少连接第四芯片040的输出引脚与器件控制电路的第二端之间的连接引线500的长度，减少这些连接引线500与参考电压引线330之间的交叠长度，进而降低这些连接引线500与参考电压引线330之间发生短路不良的风险。
可选地，在至少部分控制区域内，第一器件区A(1,1)内的器件控制电路存在连接各个功能器件的连接引线，第三器件区A(2,1)内的器件控制电路存在连接各个功能器件的连接引线，第一器件区A(1,1)的这些连接引线与第三器件区A(2,1)内的这些连接引线关于一对称轴对称，且该对称轴平行于第二方向。第二器件区A(1,2)内的器件控制电路存在连接各个功能器件的连接引线，第四器件区A(2,2)内的器件控制电路存在连接各个功能器件的连接引线，第二器件区A(1,2)的这些连接引线与第四器件区A(2,2)内的这些连接引线关于一对称轴对称，且该对称轴平行于第二方向。
示例性地，在本公开的一种实施方式中，在一个器件区A内设置有串联且呈2*2阵列分布的四个发光元件；其中，第一个发光元件与电源电压引线之间，通过与电源过孔交叠的连接引线500连接；第四个发光元件通过连接引线500连接至第四焊盘组P40的输出子焊盘。在第一器件区A(1,1)和第二器件区A(1,2)中，串联四个发光元件的三根连接引线500，在整体是呈开口朝向第一方向C的凵字型分布。在第三器件区A(2,1)和第四器件区A(2,2)中，串联四个发光元件的三根连接引线500，在整体是呈开口朝向第一方向C的相反方向的凵字型分布。在该实施方式中，在第一控制区域2011内，第一电源过孔HV1可以设置于第一器件区A(1,1)的第一方向C一侧，第四电源过孔HV4可以设置于第二器件区A(1,2)的第一方向C一侧。第一器件区A(1,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第一电源过孔HV1交叠的连接引线500连接。第三器件区A(2,1)内的器件控制电路的第一端与第一电源电压引线310之间，通过与第二电源过孔HV2交叠的连接引线500连接。第二器件区A(1,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第四电源过孔HV4交叠的连接引线500 连接。第四器件区A(2,2)内的器件控制电路的第一端与第二电源电压引线350之间，通过与第五电源过孔HV5交叠的连接引线500连接。
在该第四阵列基板的一个信号通道内，各个控制区域201可以依次编号，其中，其中编号为1的控制区域201可以位于该信号通道在其延伸方向上的一端，例如可以位于靠近绑定区B的一端或者位于远离绑定区B的一端。当一个信号通道内仅具有一个控制区域列220时，各个控制区域201可以沿第一方向C或者第一方向C的相反方向依次编号。当一个信号通道内具有多个控制区域列220时，在该信号通道内，各个控制区域201可以按照Z形逐行逐列依次编号，或者按照S形逐行逐列依次编号，或者按照N形逐列逐行依次编号，或者按照U形或者倒U形逐列逐行依次编号。在一个信号通道内，各个控制区域201中的第四焊盘组P40可以按照控制区域201的编号顺序依次级联，其中，第一级控制区域201中的第四焊盘组P40的选通信号子焊盘P45与地址引线360之间，通过与地址过孔交叠的连接引线500连接；第(n-1)级控制区域201中的第四焊盘组P40的中继信号子焊盘P46与第n级控制区域201中的第四焊盘组P40的选通信号子焊盘P45通过连接引线500连接。如此，该第四阵列基板在一个信号通道内，可以实现各个第四芯片040的相互级联，进而实现对该信号通道内的各个器件控制电路的控制。
在该第四阵列基板中，第一电源电压引线310和第二电源电压引线350可以用于加载驱动器件控制电路的电源电压VLED，例如加载驱动器件控制电路中的各个发光元件发光的电源电压VLED。参考电压引线330可以用于加载参考电压GND。第一输入引线320和第二输入引线340中，与芯片电源子焊盘P43连接的一个可以用于加载芯片工作电压VCC，另一个可以用于加载驱动数据Data。在一个信号通道内，与第一级控制区域201的第四焊盘组P40电连接的地址引线360，可以加载选通信号。如此，在各个驱动引线300的控制下，各个第四芯片040和功能器件107可以正常工作。
可选地，在该第四阵列基板的第一控制区域2011中，第二输入过孔HI2、第四输入过孔HI4可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
可选地，参见图10、图16、图22和图28，在本公开提供的布线基板中，在一个控制区域列220中，第一电源过孔HV1与第四电源过孔HV4关于第一对称轴对称，第二电源过孔HV2与第五电源过孔HV5关于第二对称轴对称，第三电源过孔HV3与第六电源过孔HV6关于第三对称轴对称。第一对称轴、第二对称轴和第三对称轴沿第一方向C延伸且相互重合。如此，可以便于布线基板的设计和制备，降低布线基板的成本，并进一步降低基于布线基板的各个阵列基板的成本。
可选地，参见图10、图16、图22和图28，在一个控制区域列220中，第一输入过孔HI1与第三输入过孔HI3关于第四对称轴对称，第二输入过孔HI2与第四输入过孔HI4关于第五对称轴对称。第四对称轴和第五对称轴沿第一方向C延伸且相互重合。如此，可以便于布线基板的设计和制备，降低布线基板的成本，并进一步降低基于布线基板的各个阵列基板的成本。
可选地，参见图10、图16、图22和图28，在一个第一控制区域2011中，沿第一方向C，第一电源过孔HV1和第四电源过孔HV4位于第一器件区A(1,1)与第一参考过孔HR1之间，第二电源过孔HV2和第五电源过孔HV5位于第三器件区A(2,1)与第一参考过孔HR1之间；第三电源过孔HV3和第六电源过孔HV6位于第三器件区A(2,1)与第二参考过孔HR2之间。如此，在一个第一控制区域2011中，在第一方向C上，第一电源过孔HV1与第一参考过孔HR1之间存在用于阵列基板布线的布线空间，第二电源过孔HV2与第一参考过孔HR1之间存在用于阵列基板布线的布线空间，第四电源过孔HV4与第一参考过孔HR1之间存在用于阵列基板布线的布线空间，第五电源过孔HV5与第一参考过孔HR1之间存在用于阵列基板布线的布线空间。阵列基板可以在这些布线空间内布设沿第二方向D延伸的连接引线500，使得这些连接引线500尽量减少与不同的驱动引线 300之间的交叠长度。
在本公开的一种实施方式中，参见图15和图16，在本公开的布线基板中，在一个第一控制区域2011中，绝缘材料层103还可以设置有暴露参考电压引线330的部分区域的第三参考过孔HR3和第四参考过孔HR4。第三参考过孔HR3和第一参考过孔HR1分别位于参考电压引线330的轴线的两侧，第四参考过孔HR4和第二参考过孔HR2分别位于参考电压引线330的轴线的两侧。在该实施方式中，布线基板在第一控制区域2011中，每个器件区A可以均具有对应的参考过孔。其中，第一器件区A(1,1)可以与第一参考过孔HR1对应设置，第二器件区A(1,2)可以与第三参考过孔HR3对应设置，第三器件区A(2,1)可以与第二参考过孔HR2对应设置，第四器件区A(2,2)可以与第四参考过孔HR4对应设置。
进一步地，第三参考过孔HR3与第一参考过孔HR1关于第六对称轴对称，第四参考过孔HR4与第二参考过孔HR2关于第七对称轴对称；第六对称轴和第七对称轴沿第一方向C延伸且相互重合。如此，可以便于布线基板的设计和制备，降低布线基板的成本，并进一步降低基于布线基板的各个阵列基板的成本。
基于该实施方式的布线基板，除了可以制备上述的第一阵列基板至第四阵列基板之外，还可以制备采用第一芯片010至第四芯片040中任意一个的其他阵列基板。
示例性地，该实施方式中的布线基板可以用于制备设置有第一芯片010的第五阵列基板。第五阵列基板在第二金属布线层104的结构可以与第一阵列基板基本相同，也可以在此基础上局部进行调整。在使用该实施方式的布线基板时，第五阵列基板中器件区A对应的第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间的连接方式更为灵活，例如可以通过该器件区A对应的参考过孔与参考电压引线330连接。
举例而言，参见图17，第五阵列基板中，第一器件区A(1,1)对应的第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间，通过与第一参考过孔HR1交叠的连接引线500连接。第二器件区A(1,2)对应的第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间，通过与第三参考过孔HR3交叠的连接引线500连接。第三器件区A(2,1)对应的第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间，通过与第二参考过孔HR2交叠的连接引线500连接。第四器件区A(2,2)对应的第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间，通过与第四参考过孔HR4交叠的连接引线500连接。这样，各个第一焊盘组P10的参考电压子焊盘P11与参考电压引线330之间的连接引线500的长度基本一致，可以提高各个第一芯片010工作环境的均一性，进而提高第五阵列基板的工作稳定性，并利于第五阵列基板的调试。
再示例性地，该实施方式中的布线基板可以用于制备设置有第二芯片020的第六阵列基板。其中，参见图18，第六阵列基板在第二金属布线层104的结构可以与第二阵列基板基本相同，也可以在此基础上局部进行调整。在使用该实施方式的布线基板时，第五阵列基板的第一控制区域2011中第二焊盘组P20的参考电压子焊盘P21与参考电压引线330之间的连接方式更为灵活。在该第六阵列基板中，在第一控制区域2011内，与第二焊盘组P20的参考电压子焊盘P21和参考电压引线330连接的连接引线500，可以与第二参考过孔HR2交叠，或者可以与第四参考过孔HR4交叠，或者可以同时与第二参考过孔HR2和第四参考过孔HR4交叠。在第一控制区域2011中，连接参考电压子焊盘P21和参考电压引线330的连接引线500，可以与参考电压引线330完全交叠。
可选地，在该第六阵列基板的第一控制区域2011中，第一参考过孔HR1、第三参考过孔HR3、第二输入过孔HI2、第四输入过孔HI4可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。第二参考过孔HR2和第四参考过孔HR4中的一个用于与连接引线500交叠，以使得参考电压子焊盘P11通过连接引线500与参考电压引线330连接；另一个可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第三芯片030的第七阵列基板。其中，参见图19，第七阵列基板在第二金属布线层104的结构可以与第三阵列基板基本相同，也可以在此基础上局部进行调整。在使用该实施方式的布线基板时，第七阵列基板在第一控制区域2011中第三焊盘组P30的参考电压子焊盘P31与参考电压引线330之间的连接方式更为灵活。在该第七阵列基板中，在第一控制区域2011内，与第三焊盘组P30的参考电压子焊盘P31和参考电压引线330连接的连接引线500，可以与第二参考过孔HR2交叠，或者可以与第四参考过孔HR4交叠。在第一控制区域2011中，连接参考电压子焊盘P31和参考电压引线330的连接引线500，可以与参考电压引线330完全交叠。
可选地，在该第七阵列基板的第一控制区域2011中，第一参考过孔HR1、第三参考过孔HR3、第二输入过孔HI2、第四输入过孔HI4可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。第二参考过孔HR2和第四参考过孔HR4中的一个用于与连接引线500交叠，以使得参考电压子焊盘P31通过连接引线500与参考电压引线330连接；另一个可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第四芯片040的第八阵列基板。参见图20，第八阵列基板在第二金属布线层104的结构可以与第四阵列基板基本相同，也可以在此基础上局部进行调整。在使用该实施方式的布线基板时，第八阵列基板在第一控制区域2011中的第四焊盘组P40的设置方式更为灵活。
在该第八阵列基板中，第四焊盘组P40依然包括两列子焊盘且每列子焊盘的数量为5个子焊盘。其中，无论参考电压子焊盘P41处于靠近第一参考过孔HR1的一侧还是靠近第三参考过孔HR3的一侧，两个参考电压子焊盘P41均可以与参考过孔连接。
在本公开的一种实施方式中，两个参考电压子焊盘P41中，可以仅一个参考电压子焊盘P41通过连接引线500与参考电压引线330电连接，另一个参考电压子焊盘P41可以不与参考电压引线330电连接。如此，第四芯片040可以通过一个参考电压子焊盘P41获得参考电压GND，可以满足第四芯片040的工作需求。在该实施方式中，在两个参考电压子焊盘P41中，可以使得靠近第一参考过孔HR1或第三参考过孔HR3的参考电压子焊盘P41通过连接引线500与参考电压引线330电连接。
可选地，在该第八阵列基板的第一控制区域2011中，第二输入过孔HI2、第四输入过孔HI4可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。第一参考过孔HR1至第四参考过孔HR4中的至少一个，用于与连接引线500交叠，且其余的参考过孔可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
可选地，在本公开提供的布线基板中，参见图16，在一个第一控制区域2011中，第三参考过孔HR3和第四参考过孔HR4位于第一参考过孔HR1和第二参考过孔HR2远离第一电源电压引线310的一侧。
在一个第一控制区域2011中，第一电源过孔HV1、第一输入过孔HI1、第一参考过孔HR1、第四电源过孔HV4、第三输入过孔HI3和第三参考过孔HR3组成第一过孔组；第二电源过孔HV2和第三电源过孔HV3中的一个、第二输入过孔HI2、第二参考过孔HR2、第五电源过孔HV5和第六电源过孔HV6中的一个、第四输入过孔HI4和第四参考过孔HR4组成第二过孔组。第一过孔组中各个过孔之间的相对位置，与第二过孔组中各个过孔之间的相对位置相同。这可以简化布线基板的设计和制备，降低各种阵列基板的成本。不仅如此，这还可以简化阵列基板的设计和制备，并利于阵列基板的调试。
在本公开的一种实施方式中，在本公开提供的布线基板中，参见图21和图22，在一个第一控制区域2011中，绝缘材料层103还设置有暴露参考电压引线330的部分区域的第五参考过孔HR5，第五参考过孔HR5位于四个器件区A之间。如此，布线基板在用于制备不同的阵列基板时，还可以进一步简化一些阵列基板的连接引线500。
示例性地，该实施方式中的布线基板可以用于制备设置有第一芯片010的第九阵列基 板。参见图23，第九阵列基板在第二金属布线层104的结构可以与第一阵列基板或者第五阵列基板相同，也可以在此基础上局部进行调整。可选地，在该第九阵列基板的第一控制区域2011中，第五参考过孔HR5可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第二芯片020的第十阵列基板。第十阵列基板在第二金属布线层104的结构可以与第二阵列基板或者第六阵列基板相同，也可以在此基础上局部进行调整。
在第十阵列基板的一种实施方式中，参见图24，相对于第二阵列基板或者第六阵列基板，第十阵列基板的参考电压子焊盘P21与参考电压引线330之间，通过与第五参考过孔HR5交叠的连接引线500连接。
在第十阵列基板的一种实施方式中，相对于第二阵列基板或者第六阵列基板，第十阵列基板的参考电压子焊盘P21也可以位于地址子焊盘P25的第一方向C的相反方向一侧；此时，可以使得参考电压子焊盘P21与参考电压引线330之间通过与第五参考过孔HR5交叠的连接引线500连接。
可选地，在该第十阵列基板的第一控制区域2011中，第十阵列基板的参考电压子焊盘P21与参考电压引线330之间，通过与第五参考过孔HR5交叠的连接引线500连接。第一参考过孔HR1至第四参考过孔HR4可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第三芯片030的第十一阵列基板。其中，第十一阵列基板在第二金属布线层104的结构可以与第三阵列基板或者第七阵列基板相同，也可以在此基础上局部进行调整。
在第十一阵列基板的一种实施方式中，参见图25，相对于第七阵列基板，第十一阵列基板的参考电压子焊盘P31与参考电压引线330之间，通过与第五参考过孔HR5交叠的连接引线500连接。
可选地，在该第十一阵列基板的第一控制区域2011中，第十一阵列基板的参考电压子焊盘P31与参考电压引线330之间，通过与第五参考过孔HR5交叠的连接引线500连接；第一参考过孔HR1至第四参考过孔HR4可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第四芯片040的第十二阵列基板。其中，第十二阵列基板在第二金属布线层104的结构可以与第四阵列基板或者第八阵列基板相同，也可以在此基础上局部进行调整。
在第十二阵列基板的一种实施方式中，参见图26，相对于第四阵列基板或者第八阵列基板，第十二阵列基板的远离第一参考过孔HR1或者远离第三参考过孔HR3的参考电压子焊盘P41与参考电压引线330之间，通过与第五参考过孔HR5交叠的连接引线500连接。
举例而言，在该第十二阵列基板的第一控制区域2011中，沿第二方向D或者其相反方向，第四焊盘组P40的两个子焊盘列中，设置有参考电压子焊盘P41的子焊盘列位于靠近第五参考过孔HR5的一侧。换言之，在第二方向D上，参考电压子焊盘P41位于选通信号子焊盘P45与第一参考过孔HR1之间；第四焊盘组P40位于第五参考过孔HR5的第二方向D一侧。如此，可以方便参考电压子焊盘P41通过第五参考过孔HR5与参考电压引线330电连接。
可选地，在该第十二阵列基板的第一控制区域2011中，第十二阵列基板的一个参考电压子焊盘P41与参考电压引线330之间，通过与第一参考过孔HR1和第三参考过孔HR3中的一个交叠的连接引线500连接。另一个参考电压子焊盘P41与参考电压引线330之间，通过与第五参考过孔HR5交叠的连接引线500连接。其余参考过孔可以不与任何第二金 属布线层104层叠且被绝缘保护层105填充。
可选地，在本公开的布线基板的一些实施方式中，参见图27和图28，在一个第一控制区域2011中，绝缘材料层103还设置有暴露第一输入引线320的部分区域的第五输入过孔HI5；沿第一方向C，第五输入过孔HI5位于第一参考过孔HR1与第三器件区A(2,1)之间；绝缘材料层103还可以设置有暴露第二输入引线340的部分区域的第六输入过孔HI6；第六输入过孔HI6与第五输入过孔HI5关于参考电压引线330的轴线对称。如此，本公开提供的布线基板同样可以适用于不同的微芯片，进而制备出不同的阵列基板。
示例性地，该实施方式中的布线基板可以用于制备设置有第一芯片010的第十三阵列基板。参见图29，第十三阵列基板在第二金属布线层104的结构可以与第一阵列基板、第五阵列基板或者第九阵列基板基本相同，也可以在此基础上局部进行调整。
可选地，在该第十三阵列基板的一种实施方式中，在第一控制区域2011中，第五输入过孔HI5和第六输入过孔HI6可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
可选地，在该第十三阵列基板的另一种实施方式中，在第一控制区域2011中，第一器件区A(1,1)对应的第一焊盘组P10的第一输入子焊盘P13与第一电源电压引线310之间，通过与第五输入过孔HI5交叠的连接引线500连接。第一输入过孔HI1可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
可选地，在该第十三阵列基板的另一种实施方式中，在第一控制区域2011中，第二器件区A(1,2)对应的第一焊盘组P10的第一输入子焊盘P13与第二电源电压引线350连接之间，通过与第六输入过孔HI6交叠的连接引线500连接。第三输入过孔HI3可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第二芯片020的第十四阵列基板。其中，第十四阵列基板在第二金属布线层104的结构可以与第一阵列基板、第五阵列基板或者第十阵列基板基本相同，也可以在此基础上局部进行调整。
在第十四阵列基板的一种实施方式中，在第一控制区域2011中，第十四阵列基板的参考电压子焊盘P21与参考电压引线330之间，通过与第一参考过孔HR1、第二参考过孔HR2和第五参考过孔HR5中的任意一个交叠的连接引线500连接。芯片电源子焊盘P23和驱动数据子焊盘P24中的一个与第一输入引线320之间，通过与第五输入过孔HI5交叠的连接引线500连接；另一个与第二输入引线340之间，通过与第六输入过孔HI6交叠的连接引线500连接。可选地，与第五输入过孔HI5交叠的连接引线500和与第六输入过孔HI6交叠的连接引线500可以沿第二方向D直线延伸，以减小与参考电压引线330之间的交叠长度。
在本公开的一种实施方式中，参见图30，相对于第十阵列基板，在第一控制区域2011中，第十四阵列基板的芯片电源子焊盘P23与第一输入引线320之间，通过与第五输入过孔HI5交叠的连接引线500连接；可选地，该连接引线500沿第二方向直线延伸，以便减小与参考电压引线330之间的交叠长度。驱动数据子焊盘P24与第二输入引线340之间，通过与第六输入过孔HI6交叠的连接引线500连接；可选地，该连接引线500沿第二方向直线延伸。第一输入过孔HI1和第三输入过孔HI3可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第三芯片030的第十五阵列基板。其中，第十五阵列基板在第二金属布线层104的结构可以与第三阵列基板、第七阵列基板或者第十阵列基板相同，也可以在此基础上局部进行调整。
在第十五阵列基板的一种实施方式中，参见图31，相对于第十一阵列基板，在第一控制区域2011中，第十五阵列基板的芯片电源子焊盘P33与第一输入引线320之间，通过与第五输入过孔HI5交叠的连接引线500连接；可选地，该连接引线500沿第二方向D 直线延伸。驱动数据子焊盘P34与第二输入引线340之间，通过与第六输入过孔HI6交叠的连接引线500连接；可选地，该连接引线500沿第二方向D直线延伸。第一输入过孔HI1和第三输入过孔HI3可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式中的布线基板可以用于制备设置有第四芯片040的第十六阵列基板。其中，第十六阵列基板在第二金属布线层104的结构可以与第四阵列基板、第八阵列基板或者第十二阵列基板相同，也可以在此基础上局部进行调整。
在第十六阵列基板的一种实施方式中，参见图32，相对于第十二阵列基板，在第一控制区域2011中，第十六阵列基板的芯片电源子焊盘P43与第一输入引线320之间，通过与第五输入过孔HI5交叠的连接引线500连接；可选地，该连接引线500沿第二方向D直线延伸。第十六阵列基板的驱动数据子焊盘P44与第二输入引线340之间，通过与第六输入过孔HI6交叠的连接引线500连接；可选地，该连接引线500沿第二方向D直线延伸。第一输入过孔HI1和第三输入过孔HI3可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
可选地，在一些实施方式中，参见图33，在本公开的布线基板以及所制备的各个阵列基板中，控制区域201还可以包括第二控制区域2012。在任意一个控制区域列220中，第二控制区域2012位于各个第一控制区域2011的第一方向C的一侧。换言之，在一个控制区域列220中，沿第一方向C上的最后一个控制区域201可以为第二控制区域2012，且其余控制区域201可以为第一控制区域2011。可选地，在任意一个控制区域列220中，第二控制区域2012的数量为一个。
可选地，参见图34，该实施方式中，布线基板包括扇出区，第一金属布线层102在扇出区设置有与各个驱动引线300连接的扇出引线400；其中，驱动引线300与对应的扇出引线400在第二控制区域2012连接。换言之，扇出引线400和驱动引线300的连接位置，位于各个第二控制区域2012范围内；扇出区和第二控制区域2012至少部分交叠。
可选地，参见图34，在第二控制区域2012中，第一器件区A(1,1)和第二器件区A(1,2)均与驱动引线300部分交叠且均不与扇出引线400交叠；第三器件区A(2,1)和第四器件区A(2,2)可以部分与扇出引线400交叠。
参见图34，在该实施方式的布线基板及各个阵列基板在一个第二控制区域2012内，绝缘材料层103设置有第七至第十电源过孔、第七至第十输入过孔、第六至第十参考过孔。
其中，第七电源过孔HV7和第八电源过孔HV8均暴露第一电源电压引线310的至少部分区域。第八电源过孔HV8位于第七电源过孔HV7的第一方向一侧，且位于第一器件区A(1,1)和第三器件区A(2,1)之间。换言之，第七电源过孔HV7可以位于第一器件区A(1,1)和第三器件区A(2,1)之间，也可以位于第一器件区A(1,1)远离第三器件区A(2,1)的一侧。在本公开的一种实施方式中，在第二控制区域2012中第七电源过孔HV7与第一器件区A(1,1)的相对位置关系，与第一控制区域2011中第一电源过孔HV1与第一器件区A(1,1)的相对位置关系相同。
其中，第九电源过孔HV9和第十电源过孔HV10均暴露第二电源电压引线350的至少部分区域。第十电源过孔HV10位于第九电源过孔HV9的第一方向一侧，且位于第二器件区A(1,2)和第四器件区A(2,2)之间。换言之，第七电源过孔HV7可以位于第二器件区A(1,2)和第四器件区A(2,2)之间，也可以位于第二器件区A(1,2)远离第四器件区A(2,2)的一侧。在本公开的一种实施方式中，在第二控制区域2012中第九电源过孔HV9与第二器件区A(1,2)的相对位置关系，与第一控制区域2011中第四电源过孔HV4与第二器件区A(1,2)的相对位置关系相同。
第七输入过孔HI7和第八输入过孔HI8均暴露第一输入引线320的部分区域；第七输入过孔HI7位于第一器件区A(1,1)远离第三器件区A(2,1)的一侧；第八输入过孔HI8 位于第一器件区A(1,1)和第三器件区A(2,1)之间。
第九输入过孔HI9和第十输入过孔HI10均暴露第二输入引线340的部分区域；第九输入过孔HI9位于第二器件区A(1,2)远离第四器件区A(2,2)的一侧；第十输入过孔HI10位于第二器件区A(1,2)和第四器件区A(2,2)之间。
第六至第十参考过孔均暴露参考电压引线330部分区域；其中，第六参考过孔HR6和第七参考过孔HR7沿第二方向D排列且位于第一器件区A(1,1)和第三器件区A(2,1)之间；第八参考过孔HR8位于第一器件区A(1,1)和第三器件区A(2,1)之间，第九参考过孔HR9位于第二器件区A(1,2)和第四器件区A(2,2)之间，第十参考过孔HR10位于第二控制区域2012的四个器件区A之间。
参见图34，在该第二控制区域2012，一根驱动引线300及其所连接的扇出引线400在整体上可以为一根弯折的金属引线；在该金属引线中，位于驱动引线300的延伸方向上的部分，均为驱动引线300。换言之，在第二控制区域2012中，在靠近驱动引线300和连接引线500的结合处附近，驱动引线300在第二方向D上的尺寸可以已经呈现逐渐缩小的趋势。在该实施方式的布线基板中，第七至第十电源过孔、第七至第十输入过孔、第六至第十参考过孔可以均暴露部分驱动引线300，使得阵列基板的连接引线500可以连接至驱动引线300而非扇出引线400。如此，尽管不同第二控制区域2012所交叠的扇出引线400不同，但是不同第二控制区域2012所交叠的驱动引线300的布图基本一致。这样，本公开的布线基板在各个第二控制区域2012中分布相对固定的驱动引线300上方设置各个过孔，可以规避扇出引线400不同进而简化布线基板的设计和制备，并利于阵列基板的设计、制备和调试。
本实施方式所提供的具有第二控制区域2012的布线基板，依然可以适用于不同的微芯片，并用于制备不同的阵列基板。
示例性地，该实施方式的布线基板可以用于制备具有第一芯片010的第十七阵列基板。该第十七阵列基板的第一控制区域2011的结构可以与第一阵列基板、第五阵列基板、第九阵列基板、第十三阵列基板中的任意一个相同。
参见图35，在第二控制区域2012，第十七阵列基板的第二金属布线层104可以包括与四个器件区A一一对应的四个第一焊盘组P10；各个焊盘组的图案可以与第一控制区域2011中的第一焊盘组P10的图案相同。
其中，第一器件区A(1,1)对应的第一焊盘组P10和第二器件区A(1,2)对应的第一焊盘组P10位于第一器件区A(1,1)和第二器件区A(1,2)之间；且第一器件区A(1,1)对应的第一焊盘组P10靠近第一器件区A(1,1)设置，第二器件区A(1,2)对应的第一焊盘组P10靠近第二器件区A(1,2)设置。在第一方向C上，第三器件区A(2,1)对应的第一焊盘组P10在第一器件区A(1,1)和第三器件区A(2,1)之间，第四器件区A(2,2)对应的第一焊盘组P10在第二器件区A(1,2)和第四器件区A(2,2)之间。可选地，第三器件区A(2,1)对应的第一焊盘组P10和第四器件区A(2,2)对应的第一焊盘组P10且均与参考电压引线330至少部分交叠。可选地，第一器件区A(1,1)对应的第一焊盘组P10和第二器件区A(1,2)对应的第一焊盘组P10沿第二方向D排列，第三器件区A(2,1)对应的第一焊盘组P10和第四器件区A(2,2)对应的第一焊盘组P10沿第二方向D排列。
参见图35，在第二控制区域2012中，各个第一焊盘组P10与器件控制电路的连接方式以及相互之间的级联方式，可以与第一控制区与相同。换言之，在一个信号通道内的各个器件区A对应的第一焊盘组P10可以依次级联，使得第(n-1)级器件区A对应的第一焊盘组P10的输出子焊盘P12与第n级器件区A对应的第一焊盘组P10的第一输入子焊盘P13通过连接引线500连接。器件区A的器件控制电路的第二端，通过连接引线500与对应的第二焊盘组P20的输出子焊盘P12连接。
第二控制区域2012中的第一器件区A(1,1)对应的第一焊盘组P10中，参考电压子 焊盘P11与参考电压引线330之间，通过与第六参考过孔HR6交叠的连接引线500连接；第一输入子焊盘P13与第一输入引线320之间，通过与第七输入过孔HI7交叠的连接引线500连接。第二控制区域2012中的第二器件区A(1,2)对应的第一焊盘组P10中，参考电压子焊盘P11与参考电压引线330之间，通过与第七参考过孔HR7交叠的连接引线500连接；第一输入子焊盘P13与第二输入引线340之间，通过与第九输入过孔HI9交叠的连接引线500连接。第二控制区域2012中的第三器件区A(2,1)对应的第一焊盘组P10中，参考电压子焊盘P11与参考电压引线330之间，通过与第八参考过孔HR8交叠的连接引线500连接；第一输入子焊盘P13与第一输入引线320之间，通过与第八输入过孔HI8交叠的连接引线500连接。第二控制区域2012中的第四器件区A(2,2)对应的第一焊盘组P10中，参考电压子焊盘P11与参考电压引线330之间，通过与第九参考过孔HR9交叠的连接引线500连接；第一输入子焊盘P13与第第二输入引线340之间，通过与第十输入过孔HI10交叠的连接引线500连接。
参见图35，在第二控制区域2012中，第一器件区A(1,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第七电源过孔HV7交叠的连接引线500连接；第二器件区A(1,2)的器件控制电路的第一端与第二电源电压引线350之间，通过与第九电源过孔HV9交叠的连接引线500连接；第三器件区A(2,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第八电源过孔HV8交叠的连接引线500连接；第四器件区A(2,2)的器件控制电路的第一端与第二电源电压引线350之间，通过与第十电源过孔HV10交叠的连接引线500连接。
可选地，在第十七阵列基板的一种实施方式中，第十参考过孔HR10可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
在该第十七阵列基板中，通过调整第二控制区域2012中四个第一焊盘组P10的位置，可以使得四个第一焊盘组P10分散设置，避免了相邻两个第一焊盘组P10紧邻设置，进而避免了相邻两个第一芯片紧邻设置而对光线产生较大的遮挡，进而避免了第一芯片的遮光而产生的光斑(mura)不良。
再示例性地，该实施方式的布线基板可以用于制备具有第二芯片020的第十八阵列基板。该第十八阵列基板的第一控制区域2011的结构可以与第二阵列基板、第六阵列基板、第十阵列基板、第十四阵列基板中的任意一个相同。
参见图36，在第二控制区域2012，该第十八阵列基板的第二金属布线层104可以包括第二焊盘组P20。可选地，第一控制区域2011和第二控制区域2012中第二焊盘组P20的图案可以相同。
参见图36，第十八阵列基板的第二控制区域2012中，第二焊盘组P20可以位于四个器件区A之间。换言之，在一个第二控制区域2012内，在沿第一方向C上，第二焊盘组P20位于第一器件区A(1,1)与第三器件区A(2,1)之间；在沿第二方向D上，第二焊盘组P20位于第一器件区A(1,1)与第二器件区A(1,2)之间。
在该第十八阵列基板中，在第二控制区域2012，第二焊盘组P20的参考电压子焊盘P21与参考电压引线330之间，通过与第六参考过孔HR6、第七参考过孔HR7和第十参考过孔HR10中的至少一个交叠的连接引线500连接。驱动数据子焊盘P24和芯片电源子焊盘P23中的一个与第一输入引线320之间，通过与第八输入过孔HI8交叠的连接引线500连接；另一个与第二输入引线340之间，通过与第十输入过孔HI10交叠的连接引线500连接。四个输出子焊盘P12分别与四个器件区A的器件控制电路的第二端连接。
举例而言，在该第十八阵列基板的一种实施方式中，在第二控制区域2012，第二焊盘组P20的参考电压子焊盘P21位于第二焊盘组P20的地址子焊盘P25的第一方向C一侧，以保证第二焊盘组P20的参考电压子焊盘P21所连接的连接引线500能够延伸至与第十参考过孔HR10交叠，且该连接引线500与参考电压引线330完全交叠。这样，在该连 接引线500与参考电压引线330短路时，第十八阵列基板可以避免呈现不良。
在第二控制区域2012，芯片电源子焊盘P23与第一输入引线320之间，通过与第八输入过孔HI8交叠的连接引线500连接；驱动数据子焊盘P24与第二输入引线340之间，通过与第十输入过孔HI10交叠的连接引线500连接；地址子焊盘P25与地址引线360之间，通过与地址过孔交叠的连接引线500连接。第一输出子焊盘P221可以通过连接引线500与第一器件区A(1,1)的器件控制电路的第二端连接；第二输出子焊盘P222可以通过连接引线500与第二器件区A(1,2)的器件控制电路的第二端连接；第三输出子焊盘P223可以通过连接引线500与第三器件区A(2,1)的器件控制电路的第二端连接；第四输出子焊盘P224可以通过连接引线500与第四器件区A(2,2)的器件控制电路的第二端连接。第一器件区A(1,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第七电源过孔HV7交叠的连接引线500连接；第二器件区A(1,2)的器件控制电路的第一端与第二电源电压引线350之间，通过与第九电源过孔HV9交叠的连接引线500连接；第三器件区A(2,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第八电源过孔HV8交叠的连接引线500连接；第四器件区A(2,2)的器件控制电路的第一端与第二电源电压引线350之间，通过与第十电源过孔HV10交叠的连接引线500连接。
可选地，在第十八阵列基板的一种实施方式中，第二控制区域2012中的第七输入过孔HI7、第九输入过孔HI9、第六参考过孔HR6、第七参考过孔HR7、第八参考过孔HR8、第九参考过孔HR9可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式的布线基板可以用于制备具有第三芯片030的第十九阵列基板。该第十九阵列基板的第一控制区域2011的结构可以与第三阵列基板、第七阵列基板、第十一阵列基板、第十五阵列基板中的任意一个相同。
参见图37，在第二控制区域2012，该第十九阵列基板的第二金属布线层104可以包括第三焊盘组P30。可选地，第一控制区域2011和第二控制区域2012中第三焊盘组P30的图案可以相同。
参见图37，第十九阵列基板的第二控制区域2012中，第三焊盘组P30可以位于四个器件区A之间。换言之，在一个第二控制区域2012内，在沿第一方向C上，第三焊盘组P30位于第一器件区A(1,1)与第三器件区A(2,1)之间；在沿第二方向D上，第三焊盘组P30位于第一器件区A(1,1)与第二器件区A(1,2)之间。
在该第十九阵列基板中，在第二控制区域2012，第三焊盘组P30的参考电压子焊盘P31与参考电压引线330之间，通过与第六参考过孔HR6、第七参考过孔HR7和第十参考过孔HR10中的至少一个交叠的连接引线500连接。驱动数据子焊盘P34和芯片电源子焊盘P33中的一个与第一输入引线320之间，通过与第八输入过孔HI8交叠的连接引线500连接；另一个与第二输入引线340之间，通过与第十输入过孔HI10交叠的连接引线500连接。四个输出子焊盘分别与四个器件区A的器件控制电路的第二端连接。在一个信号通道内，各个第三焊盘组P30依次级联，其中，第一级的第三焊盘组P30的选通信号子焊盘P35与地址引线360之间通过与地址过孔交叠的连接引线500连接；第(n-1)级的第三焊盘组P30的中继信号子焊盘P36与第n级的第三焊盘组P30的选通信号子焊盘P35之间，通过连接引线500连接。
举例而言，在该第十九阵列基板的一种实施方式中，参见图37，在第二控制区域2012，第三焊盘组P30的参考电压子焊盘P31位于第三焊盘组P30的中继信号子焊盘P36的第一方向C一侧。这样，第三焊盘组P30的参考电压子焊盘P31所连接的连接引线500可以延伸至与第十参考过孔HR10交叠，且该连接引线500与参考电压引线330完全交叠。在该连接引线500与参考电压引线330短路时，第十九阵列基板可以避免呈现不良。在第二控制区域2012，芯片电源子焊盘P33与第一输入引线320之间，通过与第八输入过孔HI8交叠的连接引线500连接；驱动数据子焊盘P34与第二输入引线340之间，通过与第十输 入过孔HI10交叠的连接引线500连接；第一输出子焊盘P321可以通过连接引线500与第一器件区A(1,1)的器件控制电路的第二端连接；第二输出子焊盘P222可以通过连接引线500与第二器件区A(1,2)的器件控制电路的第二端连接；第三输出子焊盘P223可以通过连接引线500与第三器件区A(2,1)的器件控制电路的第二端连接；第四输出子焊盘P224可以通过连接引线500与第四器件区A(2,2)的器件控制电路的第二端连接。在第二控制区域2012，第一器件区A(1,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第七电源过孔HV7交叠的连接引线500连接；第二器件区A(1,2)的器件控制电路的第一端与第二电源电压引线350之间，通过与第九电源过孔HV9交叠的连接引线500连接；第三器件区A(2,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第八电源过孔HV8交叠的连接引线500连接；第一器件区A(1,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第十电源过孔HV10交叠的连接引线500连接。
可选地，在第十九阵列基板的一种实施方式中，第二控制区域2012中的第七输入过孔HI7、第九输入过孔HI9、第六参考过孔HR6、第七参考过孔HR7、第八参考过孔HR8、第九参考过孔HR9可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
再示例性地，该实施方式的布线基板可以用于制备具有第四芯片040的第二十阵列基板。该第二十阵列基板的第一控制区域2011的结构可以与第四阵列基板、第八阵列基板、第十二阵列基板、第十六阵列基板中的任意一个相同。
在第二控制区域2012，该第二十阵列基板的第二金属布线层104可以包括第四焊盘组P40，其中，第一控制区域2011和第二控制区域2012中第四焊盘组P40的图案可以相同。
参见图38，第二十阵列基板的第二控制区域2012中，第四焊盘组P40可以位于四个器件区A之间。换言之，在一个第二控制区域2012内，在沿第一方向C上，第四焊盘组P40位于第一器件区A(1,1)与第三器件区A(2,1)之间；在沿第二方向D上，第四焊盘组P40位于第一器件区A(1,1)与第二器件区A(1,2)之间。
在该第二十阵列基板中，在第二控制区域2012，第四焊盘组P40具有两个子焊盘列，每个子焊盘列包括沿第一方向C排列的五个子焊盘。其中，沿第二方向D，在两个子焊盘列中，设置有参考电压子焊盘P41的子焊盘列可以位于靠近第十参考过孔HR10的一侧。这样，其中一个参考电压子焊盘41所连接的连接引线500可以延伸至与第十参考过孔HR10交叠；另一个参考电压子焊盘41所连接的连接引线500可以延伸至与第八参考过孔HR8或者第九参考过孔HR9交叠。第二控制区域2012中，第四焊盘组P40的驱动数据子焊盘P44和芯片电源子焊盘P43中的一个与第一输入引线320之间，通过与第八输入过孔HI8交叠的连接引线500连接；另一个与第二输入引线340之间，通过与第十输入过孔HI10交叠的连接引线500连接；四个输出子焊盘分别与四个器件区A的器件控制电路的第二端连接。在一个信号通道内，各个第四焊盘组P40依次级联，其中，第一级的第四焊盘组P40的选通信号子焊盘P45与地址引线360之间，通过与地址过孔交叠的连接引线500连接；第(n-1)级的第四焊盘组P40的中继信号子焊盘P46与第n级的第四焊盘组P40的选通信号子焊盘P45之间通过连接引线500连接。
举例而言，在该第二十阵列基板的一种实施方式中，参见图38，在第二控制区域2012，沿第二方向D，第四焊盘组P40的中继信号子焊盘P46位于参考电压子焊盘P41的第二方向D一侧，参考电压子焊盘P41位于第十参考过孔HR10的第二方向D一侧。第四焊盘组P40的一个参考电压子焊盘P41所连接的连接引线500延伸至与第十参考过孔HR10交叠，另一个参考电压子焊盘P41所连接的连接引线500延伸至与第八参考过孔HR8交叠。驱动数据子焊盘P44与第一输入引线320之间，通过与第八输入过孔HI8交叠的连接引线500连接；芯片电源子焊盘P43与第二输入引线340之间，通过与第十输入过孔HI10交 叠的连接引线500连接。第一输出子焊盘P421可以通过连接引线500与第四器件区A(2,2)的器件控制电路的第二端连接；第二输出子焊盘P422可以通过连接引线500与第三器件区A(2,1)的器件控制电路的第二端连接；第三输出子焊盘P423可以通过连接引线500与第二器件区A(1,2)的器件控制电路的第二端连接；第四输出子焊盘P424可以通过连接引线500与第一器件区A(1,1)的器件控制电路的第二端连接。第一器件区A(1,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第七电源过孔HV7交叠的连接引线500连接；第三器件区A(2,1)的器件控制电路的第一端与第一电源电压引线310之间，通过与第八电源过孔HV8交叠的连接引线500连接；第二器件区A(1,2)的器件控制电路的第一端与第二电源电压引线350之间，通过与第九电源过孔HV9交叠的连接引线500连接；第四器件区A(2,2)的器件控制电路的第一端与第二电源电压引线350之间，通过与第十电源过孔HV10交叠的连接引线500连接。
可选地，在第二十阵列基板的一种实施方式中，第二控制区域2012中的第七输入过孔HI7、第九输入过孔HI9、第六参考过孔HR6、第七参考过孔HR7、第九参考过孔HR9可以不与任何第二金属布线层104交叠，且被绝缘保护层105填充。
在本公开提供的布线基板中，在一个信号通道内可以设置有至少一个地址引线360。其中，绝缘材料层103可以设置有暴露地址引线360的部分区域的地址过孔。如此，在本公开的阵列基板中，第二金属布线层104可以设置有与地址过孔交叠的连接引线500，该连接引线500可以与微芯片对应的芯片焊盘组连接，以便向微芯片提供所需的信号。
可选地，参见图40，在一个控制区域列220内可以设置有两个地址引线360。示例性地，参见图10、图16、图22、图28和图34，在一个控制区域列220内，地址引线360包括第一地址引线361和第二地址引线362，其中，第一地址引线361设置于第一电源电压引线310和第一输入引线320之间，第二地址引线361设置于第二电源电压引线350和第二输入引线340之间。
可选地，在一个控制区域列220内的两个地址引线360中，其中一个地址引线360可以延伸至控制区域列220远离绑定区B的一端，另一个地址引线360可以仅设置于最靠近绑定区B的控制区域201中。示例性地，参见图50，一个控制区域列220内设置有第一地址引线361和第二地址引线362；其中，第一地址引线361可以向远离绑定区B的方向延伸并与该控制区域列220内的各个控制区域201交叠，第二地址引线362仅与第二控制区域2012交叠，即可以仅位于靠近绑定区B的控制区域201内。
可选地，布线基板上设置的地址引线360的数量不小于控制区域行210的数量，且在一个信号通道内至少设置一个地址引线360。地址过孔至少包括第一地址过孔HD1和第二地址过孔HD2。在本公开的一种实施方式中，布线基板上设置的地址引线360的数量等于控制区域行210的数量。
参见图40，第一地址过孔HD1可以靠近地址引线360的其中一端设置，且在任意一个信号通道内设置至少一个第一地址过孔HD1。参见图41，当微芯片为第一芯片010、第三芯片030或者第四芯片040时，微芯片与地址引线360可以通过与第一地址过孔HD1交叠的连接引线500连接，进而收到地址引线360上所加载的选通信号的控制。进一步地，在一个信号通道内，用于使得第一级微芯片和地址引线360连接的第一地址过孔HD1，可以与该第一级微芯片位于同一个控制区域201内。
可选地，参见图40，在本公开的布线基板及阵列基板的一种实施方式中，各个第一地址过孔HD1可以沿第二方向D直线排布。
可选地，在本公开的布线基板及阵列基板的一种实施方式中，第一地址过孔HD1可以位于布线基板远离绑定区B的一端。当然地，在本公开的布线基板及阵列基板的另一种实施方式中，第一地址过孔HD1可以位于布线基板靠近绑定区B的一端。
可选地，在本公开的布线基板及阵列基板的一种实施方式中，参见图41，一个信号 通道内可以仅设置一个第一地址过孔HD1。
可选地，在本公开的布线基板及阵列基板的另一种实施方式中，参见图43，第一地址过孔HD1与各个地址引线360一一对应设置，其中，任意一个第一地址过孔HD1可以暴露对应的地址引线360的部分区域。参见图44，第一地址过孔HD1的数量可以超过所需数量；在设置第二金属布线层104时，可以在任意一个信号通道内选择其中一个第一地址过孔HD1作为该信号通道对应的第一地址过孔HD1，且该对应的第一地址过孔HD1用于使得地址引线360与级联的第一级微芯片电连接，其余第一地址过孔HD1可以被绝缘保护层105填充。如此，阵列基板可以根据第二金属布线层104的布线需求更加灵活地选择与连接引线500交叠的第一地址过孔HD1，且使得其他第一地址过孔HD1不与任何连接引线500交叠，且被绝缘保护层105填充。
可选地，参见图40，任意一个控制区域行210内至少设置有一个第二地址过孔HD2，且可以从该控制区域行210内选择一个第二地址过孔HD2作为该控制区域行210对应的第二地址过孔HD2。其中，在本公开的布线基板中，各个控制区域行210所各自对应的第二地址过孔HD2，分别暴露不同的地址引线360。换言之，在任意一个控制区域行210内设置有与控制区域行210对应的第二地址过孔HD2，各个控制区域行210对应的第二地址过孔HD2分别暴露不同地址引线的部分区域。可以理解的是，在一些实施方式中，部分第一地址过孔HD1可以复用为第二地址过孔HD2。
在本公开的阵列基板中，当微芯片为第二芯片或者其他需要逐行扫通的微芯片时，参见图42，第二金属布线层104可以设置有与各个控制区域行210一一对应的且作为扫描引线的多个连接引线500。其中，扫描引线与对应的控制区域行210的各个控制区域201交叠，且与该控制区域行210对应的第二地址过孔HD2交叠。在控制区域行210内的各个地址子焊盘P25可以通过连接引线500与该扫描引线连接。如此，与该扫描引线连接的地址引线360，可以用于向该扫描引线加载选通信号，进而使得该控制区域行210中的各个第二芯片020选通。
在一些实施方式中，扫描引线可以沿第二方向D延伸，其两端可以分别位于控制区域行210两端的两个控制区域201内，且该扫描引线穿过该控制区域行210中的其他控制区域201。
参见图42，在一些实施方式中，扫描引线可以沿第二方向D直线延伸，并与其中一个第二地址过孔HD2交叠。在本公开的另一种实施方式中，扫描引线可以包括延伸段和连接段，其中延伸段可以沿第二方向D延伸且不与任何第二地址过孔HD2交叠；连接段与延伸段连接并与其中一个第二地址过孔HD2交叠。
在一些实施方式中，参见图40，布线基板上的第二地址过孔HD2的数量与控制区域行210的数量相同，且分别暴露不同的地址引线360；其中，各个第二地址过孔HD2与各个控制区域行210一一对应设置，且任意一个第二地址过孔HD2位于对应的控制区域行210内。如此，第二地址过孔HD2的数量较少，可以降低开设第二地址过孔HD2对地址引线360可能造成的影响。
在另一些实施方式中，参见图43，在本公开的阵列基板和布线基板中，在任意一个控制区域行210内，第二地址过孔HD2的数量与地址引线360的数量相同且一一对应设置，任意一个第二地址过孔HD2暴露对应的地址引线360。换言之，在每一个地址引线360和控制区域行210交叠范围内，均设置有至少一个第二地址过孔HD2。如此，参见图45，在本公开的阵列基板中，可以在一个控制区域行210中选择一个第二地址过孔HD2作为该控制区域行210对应的第二地址过孔HD2；该控制区域行210对应的第二地址过孔HD2与连接引线500交叠以便驱动该控制区域行210内的各个微芯片。如此，可以增加阵列基板布线的灵活性，也便于布线基板和阵列基板的设计、制备和调试。
可选地，地址过孔还可以包括第三地址过孔HD3。参见图40和图43，第三地址过孔 HD3可以靠近地址引线360的其中一端设置；其中，沿第一方向C，第一地址过孔HD1和第三地址过孔HD3可以分别分布于本公开的布线基板的两端。在一个信号通道内，可以设置有至少一个第三地址过孔HD3，地址引线的数量至少为两个；至少一个第一地址过孔HD1和至少一个第三地址过孔HD3分别暴露不同的地址引线。当该阵列基板的微芯片为第一芯片010时，最后一级第一芯片010的输出引脚012与地址引线360之间可以通过与第三地址过孔HD3层叠的连接引线500连接，进而使得级联的第一芯片010形成回路。当该阵列基板的微芯片为第三芯片030或者第四芯片040时，最后一级第三芯片030或者第四芯片040的输出引脚与地址引线360之间可以通过与第三地址过孔HD3层叠的连接引线500连接，进而使得级联的第三芯片030或者第四芯片040形成回路。可以理解的是，第一地址过孔HD1和第三地址过孔HD3为根据阵列基板中微芯片与地址引线360的连接关系而定义的两个相对概念；一个地址过孔在一种阵列基板中可以为第一地址过孔HD1，而在另一种阵列基板中可以为第三地址过孔HD3。还可以理解的是，在一些实施方式我中，第三地址过孔HD3中的至少部分可以复用为第二地址过孔HD2。
在一些实施方式中，参见图40，在本公开的阵列基板和布线基板中，在一根地址引线360上，不同时设置第一地址过孔HD1和第三地址过孔HD3。示例性地，在一个控制区域列中可以设置两根地址引线，以及设置一个第一地址过孔HD1和一个第三地址过孔HD3。第一地址过孔HD1暴露其中一个地址引线，第三地址过孔HD3暴露另一个地址引线。在本公开的另一种实施方式中，参见图43，在本公开的阵列基板和布线基板中，在任意一根地址引线360上，可以同时设置第一地址过孔HD1和第三地址过孔HD3。换言之，任意一个地址引线360的两端，分别被第一地址过孔HD1和第三地址过孔HD3暴露。在阵列基板的任意一个信号通道内，对于依次级联的多个微芯片，第一级的微芯片和最后一级的微芯片分别与不同的地址引线360连接。如此，可以提高阵列基板的布线的灵活性。
可选地，在本公开的阵列基板中，部分地址过孔可以与连接引线500层叠，以使得地址引线360能够通过与该地址过孔层叠的连接引线500向微芯片加载信号。其余地址过孔可以不与任何第二金属布线层104层叠，且可以被绝缘保护层105填充。
可选地，参见图46，在本公开的布线基板中，第一金属布线层102还可以具有沿第二方向D延伸的第一电压分布线371，各个驱动引线300可以位于第一电压分布线371的第一方向C一侧。其中，电源电压引线和参考电压引线330中的一种，可以沿第一方向C的相反方向延伸至与第一电压分布线371连接。换言之，第一电源电压引线和第二电源电压引线可以沿第一方向的相反方向延伸至与第一电压分布线连接，或者参考电压引线可以沿第一方向的相反方向延伸至与第一电压分布线连接。这使得各个电源电压引线或者各个参考电压引线330相互电连接，进而提高用于布线基板的阵列基板的抗信号扰动能力和电压稳定性。
进一步地，在本公开的布线基板中，参见图46，第一金属布线层102还可以具有沿第二方向D延伸的第二电压分布线372。其中，第一电压分布线371可以位于第二电压分布线372与各个驱动引线300之间。电源电压引线和参考电压引线330中的一种，可以沿第一方向C的相反方向延伸至与第一电压分布线371连接；另一种驱动引线300至多部分沿第一方向C的相反方向延伸以与第二电压分布线372连接，且该驱动引线300与第一电压分布引线不连接。在基于布线基板的阵列基板中，第二金属布线层104可以设置跨接引线373，该跨接引线373跨过第一电压分布线371，并通过过孔使得第二电压分布线372与上述的另一种驱动引线300连接。
示例性地，参见图46，在本公开的一种实施方式中，在第一金属布线层102内，各个参考电压引线330可以沿第一方向C的相反方向延伸至与第一电压分布线371连接。在第一金属布线层102内，第一电压分布线371位于第二电压分布线372与至少部分电源电压引线之间，使得至少部分电源电压引线与第二电压分布线372不能通过第二电压分布线 372电连接。在基于该阵列基板的阵列基板中，参见图46，第二金属布线层104可以设置有多个跨接引线373，在第一金属布线层102上与第二电压分布线372断路的各个电源电压引线与各个跨接引线373一一对应设置。其中，跨接引线373跨过第一电压分布线371，且一端通过过孔与第二电压分布线372连接，另一端可以通过过孔与对应的电源电压引线连接。如此，在该阵列基板中，各个电源电压引线之间相互电连接，能够实现不同电源电压引线之间的相互分流，提高电源电压引线的抗过载能力，并提高阵列基板的抗信号扰动性能和稳压性能。各个参考电压引线330之间相互电连接，这可以提高阵列基板的抗信号扰动能力，并提高参考电压引线330上的电压的稳定性。
进一步地，参见图46，在布线基板中，在第二方向D上，第一电压分布线371可以位于布线基板最两侧的两根电源电压引线之间。如此，在第一金属布线层102，最两侧的电源电压引线可以沿第一方向C的相反方向延伸至与第二电压分布线372连接。
再示例性地，在本公开的另一种实施方式中，在第一金属布线层102内，各个电源电压引线可以沿第一方向C的相反方向延伸至与第一电压分布线371连接。在第一金属布线层102内，第一电压分布线371位于第二电压分布线372与参考电压引线330之间，使得参考电压引线330与第二电压分布线372不能通过第一金属布线层102电连接。在基于该阵列基板的阵列基板中，第二金属布线层104可以设置有与各个参考电压引线330一一对应设置的跨接引线373。其中，跨接引线373跨过第一电压分布线371，且一端通过过孔与第二电压分布线372连接，另一端可以通过过孔与对应的参考电压引线330连接。如此，在该阵列基板中，各个电源电压引线之间相互电连接，能够实现不同电源电压引线之间的相互分流，提高电源电压引线的抗过载能力，并提高阵列基板的抗信号扰动性能和稳压性能。各个参考电压引线330之间相互电连接，这可以提高阵列基板的抗信号扰动能力，并提高参考电压引线330上的电压的稳定性。
可选地，在本公开的阵列基板中，参见图46，跨接引线373可以与器件区A部分交叠；此时，可以调整器件控制电路中连接引线500的方向，使得连接引线500避让跨接走线373。如此，器件区A内的功能器件107的相对位置在不同的器件区A中均是相同的，这可以保证阵列基板上功能器件107均匀分布。
可选地，参见图47，阵列基板还包括多个导电连接部374，相邻的第一电源电压引线310和第二电源电压引线350之间通过多个导电连接部374连接。如此，相邻两个电源电压引线之间通过多个导电连接部374连接而成网格状，既可以使得两个电源电压引线之间进行充分有效地信号分流，又可以避免相邻两个电源电压引线完全合并为一条电源电压引线而导致第一金属布线层102的金属面积占比过于大。
可以理解的是，在另外的一些实施方式中，相邻两个电源电压引线也可以完全合并为一条电源电压引线，以降低电源电压引线的阻抗并提高其抗过载性能。进一步地，可以通过调整不同驱动引线300之间的间距、对部分驱动引线300进行镂空等方法，调整金属布线层的金属面积占比，满足阵列基板的制备工艺要求。
在本公开的一种实施方式中，导电连接部374可以位于第一金属布线层102，导电连接部374位于相邻的两个电源电压引线之间且与该两个电源电压引线连接，使得相邻两个电源电压引线和其之间的导电连接部374形成网格状。
当然的，在本公开的阵列基板的其他实施方式中，导电连接部374的部分或者全部，也可以位于第二金属布线层104。举例而言，导电连接部374位于第二金属布线层104，且导电连接部374通过过孔与相邻的两个电源电压引线连接。再举例而言，导电连接部374可以包括第一部分和第二部分，其中第一部分位于第一金属布线层102且与其中一个电源电压引线连接，第二部分位于第二金属布线层104且通过过孔与第一部分和另一个电源电压引线连接。
本公开实施方式还提供一种发光模组，该发光模组包括上述阵列基板实施方式所描述 的任意一种阵列基板。该发光模组可以为电脑显示器的发光模组、手机屏幕的发光模组、电视机的发光模组或者其他液晶显示器的发光模组，其既可以为透射式液晶显示器的直下式发光模组，也可以为反射式液晶显示器的直下式发光模组。由于该发光模组具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (36)

  1. 一种布线基板，包括阵列分布的多个控制区域，所述多个控制区域排列成多个控制区域行和多个控制区域列；任意一个所述控制区域列包括沿第一方向排列的至少两个所述控制区域，任意一个所述控制区域行包括沿第二方向排列的至少两个所述控制区域；所述第二方向平行于所述布线基板所在平面且与所述第一方向相交；
    任意一个所述控制区域包括阵列分布的四个器件区，所述器件区用于设置相互电连接的功能器件；任意一个所述控制区域内的所述四个器件区分别为第一器件区、第二器件区、第三器件区和第四器件区；其中，所述第一器件区为所述控制区域内在所述第一方向上位于第一行、在所述第二方向上位于第一列的所述器件区；第二器件区为所述控制区域内在所述第一方向上位于第一行、在所述第二方向上位于第二列的所述器件区；第三器件区为所述控制区域内在所述第一方向上位于第二行、在所述第二方向上位于第一列的所述器件区；第四器件区为所述控制区域内在所述第一方向上位于第二行、在所述第二方向上位于第二列的所述器件区；
    所述布线基板包括依次层叠设置的衬底基板、第一金属布线层和绝缘材料层；所述第一金属布线层设置有沿所述第一方向延伸的驱动引线；在任意一个所述控制区域列内，所述驱动引线至少包括沿所述第二方向依次排列的第一电源电压引线、第一输入引线、参考电压引线、第二输入引线和第二电源电压引线；所述布线基板还具有至少一个沿所述第一方向延伸的信号通道，且任意一个所述信号通道包括至少一个所述控制区域列；在任意一个所述信号通道中，所述驱动引线还包括至少一个地址引线；
    所述控制区域包括第一控制区域；在一个所述第一控制区域中，所述绝缘材料层设置有第一电源过孔至第六电源过孔、第一输入过孔至第四输入过孔、第一参考过孔和第二参考过孔；
    所述第一电源过孔至所述第三电源过孔沿所述第一方向依次排列且分别暴露所述第一电源电压引线的部分区域；所述第一电源过孔位于所述器件区A(1,1)远离所述器件区A(2,1)的一侧或者位于所述器件区A(1,1)与所述器件区A(2,1)之间；所述第二电源过孔位于所述器件区A(1,1)和所述器件区A(2,1)之间；所述第三电源过孔位于所述器件区A(2,1)远离所述器件区A(1,1)的一侧；
    所述第四电源过孔至所述第六电源过孔沿所述第一方向依次排列且分别暴露所述第二电源电压引线的部分区域；所述第四电源过孔位于所述第二器件区远离所述第四器件区的一侧或者位于所述第二器件区与所述第四器件区之间；所述第五电源过孔位于所述第二器件区和所述第四器件区之间；所述第六电源过孔位于所述第四器件区远离所述第二器件区的一侧；
    所述第一输入过孔和所述第二输入过孔分别暴露所述第一输入引线的部分区域；所述第一输入过孔位于所述第一器件区远离所述第三器件区的边缘与所述第三器件区靠近所述第一器件区的边缘之间；所述第二输入过孔位于所述第三器件区远离所述第一器件区的一侧；
    所述第三输入过孔和所述第四输入过孔分别暴露所述第二输入引线的部分区域；所述第三输入过孔位于所述第二器件区远离所述第四器件区的边缘与所述第四器件区靠近所述第二器件区的边缘之间；所述第四输入过孔位于所述第四器件区远离所述第二器件区的一侧；
    所述第一参考过孔和所述第二参考过孔均暴露所述参考电压引线的部分区域；沿所述第一方向，所述第一参考过孔位于所述第一器件区与所述第三器件区之间，所述第二参考过孔位于所述第三器件区远离所述与第一器件区的一侧；
    在任意一个所述信号通道，所述绝缘材料层还设置有暴露所述至少一个地址引线的部分区域的至少一个地址过孔。
  2. 根据权利要求1所述的布线基板，其中，在一个所述控制区域列中，所述第一电源过孔与所述第四电源过孔关于第一对称轴对称，所述第二电源过孔与所述第五电源过孔关于第二对称轴对称，所述第三电源过孔与所述第六电源过孔关于第三对称轴对称。
  3. 根据权利要求1所述的布线基板，其中，在一个所述控制区域列中，所述第一输入过孔与所述第三输入过孔关于第四对称轴对称，所述第二输入过孔与所述第四输入过孔关于第五对称轴对称。
  4. 根据权利要求1所述的布线基板，其中，在一个所述第一控制区域中，沿所述第一方向，所述第一电源过孔和所述第四电源过孔位于所述第一器件区与所述第一参考过孔之间，所述第二电源过孔和所述第五电源过孔位于所述第三器件区与所述第一参考过孔之间；所述第三电源过孔和所述第六电源过孔位于所述第三器件区与所述第二参考过孔之间。
  5. 根据权利要求1所述的布线基板，其中，在一个所述第一控制区域中，所述绝缘材料层还设置有暴露所述参考电压引线的部分区域的第三参考过孔和第四参考过孔；所述第三参考过孔与所述第一参考过孔关于第六对称轴对称，所述第四参考过孔与所述第二参考过孔关于所述第七对称轴对称。
  6. 根据权利要求5所述的布线基板，其中，在一个所述第一控制区域中，在所述第二方向上，所述第三参考过孔和所述第四参考过孔位于所述第一参考过孔和所述第二参考过孔远离所述第一电源电压引线的一侧；
    在一个所述第一控制区域中，所述第一电源过孔、所述第一输入过孔、所述第一参考过孔、所述第四电源过孔、所述第三输入过孔和所述第三参考过孔组成第一过孔组；所述第二电源过孔和所述第三电源过孔中的一个、所述第二输入过孔、所述第二参考过孔、所述第五电源过孔和所述第六电源过孔中的一个、所述第四输入过孔和所述第四参考过孔组成第二过孔组；
    所述第一过孔组中各个过孔之间的相对位置，与所述第二过孔组中各个过孔之间的相对位置相同。
  7. 根据权利要求1所述的布线基板，其中，在一个所述第一控制区域中，所述绝缘材料层还设置有暴露所述参考电压引线的部分区域的第五参考过孔，所述第五参考过孔位于四个所述器件区之间。
  8. 根据权利要求1所述的布线基板，其中，在一个所述第一控制区域中，所述绝缘材料层还设置有暴露所述第一输入引线的部分区域的第五输入过孔；沿所述第一方向，所述第五输入过孔位于所述第一参考过孔与所述第三器件区之间；所述绝缘材料层还可以设置有暴露所述第二输入引线的部分区域的第六输入过孔；所述第六输入过孔与所述第五输入过孔关于第八对称轴对称，所述第八对称轴沿所述第一方向延伸。
  9. 根据权利要求1所述的布线基板，其中，所述控制区域还包括第二控制区域；在任意一个所述控制区域列中，所述第二控制区域位于各个所述第一控制区域的所述第一方向的一侧；
    在一个所述第二控制区域中，所述绝缘材料层设置有第七电源过孔至第十电源过孔、第七输入过孔至第十输入过孔、第六参考过孔至第十参考过孔；
    所述第七电源过孔和所述第八电源过孔均暴露所述第一电源电压引线的至少部分区域，所述第九电源过孔和所述第十电源过孔均暴露所述第二电源电压引线的至少部分区域；所述第八电源过孔位于所述第七电源过孔的所述第一方向一侧，且位于所述第一器件区和所述第三器件区之间；所述第十电源过孔位于所述第九电源过孔的所述第一方向一侧，且位于所述第二器件区和所述第四器件区之间；
    所述第七输入过孔和所述第八输入过孔均暴露所述第一输入引线的部分区域；所 述第七输入过孔位于所述第一器件区远离所述第三器件区的一侧；所述第八输入过孔位于所述第一器件区和所述第三器件区之间；所述第九输入过孔和所述第十输入过孔均暴露所述第二输入引线的部分区域；所述第九输入过孔位于所述第二器件区远离所述第四器件区的一侧；所述第十输入过孔位于所述第二器件区和所述第四器件区之间；
    所述第六参考过孔至所述第十参考过孔均暴露所述参考电压引线部分区域；其中，所述第六参考过孔和所述第七参考过孔沿所述第二方向排列且位于所述第一器件区和所述第三器件区之间；所述第八参考过孔位于所述第一器件区和所述第三器件区之间，所述第九参考过孔位于所述第二器件区和所述第四器件区之间，所述第十参考过孔位于所述第二控制区域的所述四个器件区之间。
  10. 根据权利要求9所述的布线基板，其中，所述布线基板包括扇出区，所述第一金属布线层在所述扇出区设置有与各个所述驱动引线连接的扇出引线；其中，所述驱动引线与对应的所述扇出引线在所述第二控制区域连接。
  11. 根据权利要求1所述的布线基板，其中，所述地址引线的数量不小于所述控制区域行的数量；
    所述地址过孔包括第一地址过孔和第二地址过孔；所述第一地址过孔靠近所述地址引线的其中一端设置，且在任意一个所述信号通道内设置至少一个所述第一地址过孔；在任意一个所述控制区域行内设置有与所述控制区域行对应的所述第二地址过孔，各个所述控制区域行对应的所述第二地址过孔分别暴露不同所述地址引线的部分区域。
  12. 根据权利要求11所述的布线基板，其中，所述地址过孔还包括第三地址过孔；沿所述第一方向，所述第一地址过孔和所述第三地址过孔分别分布于所述布线基板的两端；在一个所述信号通道内，所述地址引线的数量至少为两个，所述第三地址过孔的数量至少为1，至少一个所述第一地址过孔和至少一个所述第三地址过孔分别暴露不同的所述地址引线。
  13. 根据权利要求12所述的布线基板，其中，在一个所述控制区域列中设置两个所述地址引线，以及设置有一个所述第一地址过孔和一个所述第三地址过孔；所述第一地址过孔暴露其中一个所述地址引线，所述第三地址过孔暴露另一个所述地址引线。
  14. 根据权利要求12所述的布线基板，其中，任意一个所述地址引线的两端，分别被所述第一地址过孔和所述第三地址过孔暴露。
  15. 根据权利要求11所述的布线基板，其中，所述第二地址过孔的数量与所述控制区域行的数量相同，各个所述第二地址过孔与各个所述控制区域行一一对应设置；各个所述第二地址过孔分别暴露不同的所述地址引线，且任意一个所述第二地址过孔位于对应的所述控制区域行内。
  16. 根据权利要求11所述的布线基板，其中，在任意一个所述控制区域行内，所述第二地址过孔的数量与所述地址引线的数量相同且一一对应设置，任意一个所述第二地址过孔暴露对应的所述地址引线。
  17. 根据权利要求1所述的布线基板，其中，所述第一金属布线层还具有沿所述第二方向延伸的第一电压分布线，各个所述驱动引线位于所述第一电压分布线的所述第一方向一侧；所述第一电源电压引线和所述第二电源电压引线沿所述第一方向的相反方向延伸至与所述第一电压分布线连接，或者所述参考电压引线沿所述第一方向的相反方向延伸至与所述第一电压分布线连接。
  18. 根据权利要求17所述的布线基板，其中，所述第一金属布线层还包括沿所述第二方向延伸的第二电压分布线；其中，所述第一电压分布线位于所述第二电压分布线与各个所述驱动引线之间。
  19. 一种阵列基板，包括权利要求1～18任意一项所述的布线基板。
  20. 根据权利要求19所述的阵列基板，其中，所述阵列基板还包括依次层叠于所 述布线基板的绝缘材料层远离所述衬底基板一侧的第二金属布线层和绝缘保护层，以及包括多个功能器件和多个微芯片；
    其中，所述第二金属布线层包括多个连接引线、多个器件焊盘组和多个芯片焊盘组，所述功能器件与所述器件焊盘组绑定连接，所述微芯片与所述芯片焊盘组绑定连接；所述器件焊盘组和所述芯片焊盘组与所述连接引线连接；至少部分所述连接引线通过设于所述绝缘材料层上的至少部分过孔与所述第一金属布线层连接。
  21. 根据权利要求20所述的阵列基板，其中，在任意一个所述器件区内设置有器件控制电路，所述器件控制电路包括一个所述功能器件或者多个电连接的所述功能器件；
    在所述第一控制区域，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第一电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第二电源过孔或者第三电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第四电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第五电源过孔或者第六电源过孔交叠的所述连接引线连接。
  22. 根据权利要求21所述的阵列基板，其中，在一个所述控制区域内，所述阵列基板设置有与四个所述器件区一一对应的四个所述芯片焊盘组；任意一个所述芯片焊盘组包括参考电压子焊盘、输出子焊盘、第一输入子焊盘和第二输入子焊盘；任意一个所述器件区内的所述器件控制电路的第二端，与所述器件区对应的所述芯片焊盘组的所述输出子焊盘之间通过所述连接引线连接；
    在一个所述信号通道内，各个所述器件区依次编号，且编号为1的所述器件区位于所述信号通道在所述第一方向上的一端；各个所述器件区对应的所述芯片焊盘组按照所述器件区的编号顺序依次级联；编号为1的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘与其中一个所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述器件区对应的所述芯片焊盘组的所述输出子焊盘与编号为n的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述器件区的数量；
    在任意一个所述第一控制区域中，所述第一器件区对应的所述芯片焊盘组的所述参考电压子焊盘和所述第二器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第一参考过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述参考电压子焊盘和所述第四器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第二参考过孔交叠的所述连接引线连接；所述第一器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第一输入过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第二输入过孔交叠的所述连接引线连接；所述第二器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第三输入过孔交叠的所述连接引线连接；所述第四器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第四输入过孔交叠的所述连接引线连接。
  23. 根据权利要求22所述的阵列基板，其中，在一个所述控制区域内，所述阵列基板设置有与四个所述器件区一一对应的四个所述芯片焊盘组；任意一个所述芯片焊盘组包括参考电压子焊盘、输出子焊盘、第一输入子焊盘和第二输入子焊盘；任意一个所述器件区内的所述器件控制电路的第二端，与所述器件区对应的所述芯片焊盘组的所述输出子焊盘之间通过所述连接引线连接；
    在一个所述信号通道内，各个所述器件区依次编号，且编号为1的所述器件区位于所述信号通道在所述第一方向上的一端；各个所述器件区对应的所述芯片焊盘组按照所述器件区的编号顺序依次级联；编号为1的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘与其中一个所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述器件区对应的所述芯片焊盘组的所述输出子焊盘与编号为n的所述器件区对应的所述芯片焊盘组的所述第二输入子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述器件区的数量；
    在任意一个所述第一控制区域中，所述第一器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第一输入过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第一输入引线之间，通过与所述第二输入过孔交叠的所述连接引线连接；所述第二器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第三输入过孔交叠的所述连接引线连接；所述第四器件区对应的所述芯片焊盘组的所述第一输入子焊盘与所述第二输入引线之间，通过与所述第四输入过孔交叠的所述连接引线连接；
    当所述布线基板设置有所述第三参考过孔和所述第四参考过孔时，在任意一个所述第一控制区域中，所述第一器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第一参考过孔交叠的所述连接引线连接；所述第三器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第二参考过孔交叠的所述连接引线连接；所述第二器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第三参考过孔交叠的所述连接引线连接；所述第四器件区对应的所述芯片焊盘组的所述参考电压子焊盘与所述参考电压引线之间，通过与所述第四参考过孔交叠的所述连接引线连接。
  24. 根据权利要求22或者23所述的阵列基板，其中，当所述布线基板包括所述第二控制区域时，在任意一个所述第二控制区域内，所述第一器件区对应的所述芯片焊盘组和所述第二器件区对应的所述芯片焊盘组位于第一器件区和第二器件区之间；且所述第一器件区对应的所述芯片焊盘组靠近第一器件区设置，所述第二器件区对应的所述芯片焊盘组靠近所述第二器件区设置；在所述第一方向上，所述第三器件区对应的所述芯片焊盘组在所述第一器件区和所述第三器件区之间，所述第四器件区对应的所述芯片焊盘组在所述第二器件区和所述第四器件区之间；
    在任意一个所述第二控制区域内所述第一器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第六参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第一输入引线之间通过与所述第七输入过孔交叠的所述连接引线连接；
    在任意一个所述第二控制区域内所述第二器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第七参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第二输入引线之间通过与所述第九输入过孔交叠的所述连接引线连接；
    在任意一个所述第二控制区域内所述第三器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第八参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接；
    在任意一个所述第二控制区域内所述第四器件区对应的所述芯片焊盘组中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第九参考过孔交叠的所述连接引线连接，所述第一输入子焊盘与所述第二输入引线之间通过与所述第十输入过孔交叠 的所述连接引线连接；
    在任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接。
  25. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、地址子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；所述参考电压子焊盘位于所述地址子焊盘的第一方向一侧；
    在任意一个所述第一控制区域内，所述参考电压子焊盘位于所述地址子焊盘的第一方向一侧；所述参考电压子焊盘与所述参考电压引线之间通过与所述第二参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第三输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
  26. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、地址子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
    当所述布线基板设置有所述第五参考过孔时，在任意一个所述第一控制区域内，所述参考电压子焊盘与所述参考电压引线之间通过与所述第五参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第三输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
  27. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、地址子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
    当所述布线基板设置有所述第五输入过孔和所述第六输入过孔时，在任意一个所述第一控制区域内，所述参考电压子焊盘与所述参考电压引线之间通过所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第五输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第六输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
  28. 根据权利要求25～27任意一项所述的阵列基板，其中，当所述布线基板包括所述第二控制区域时，在任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的 所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接；四个所述器件区内的所述器件控制电路的第二端一一对应地与四个所述输出子焊盘通过连接引线连接；
    所述参考电压子焊盘与所述参考电压引线之间通过与所述第十参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第十输入过孔交叠的所述连接引线连接；所述地址子焊盘与所述地址引线之间通过与所述地址过孔交叠的所述连接引线连接。
  29. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
    在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述控制区域的数量；
    在任意一个所述第一控制区域中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第二参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
  30. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
    在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；
    当所述布线基板包括所述第五参考过孔时，在任意一个所述第一控制区域中，所述参考电压子焊盘与所述参考电压引线之间通过与所述第五参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线 之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
  31. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
    在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述控制区域的数量；
    当所述布线基板包括所述第五参考过孔和所述第六参考过孔时，在任意一个所述第一控制区域中，所述参考电压子焊盘与所述参考电压引线之间通过所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第五输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第六输入过孔交叠的所述连接引线连接。
  32. 根据权利要求29～31任意一项所述的阵列基板，其中，当所述布线基板包括所述第二控制区域时，在任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接；四个所述器件区内的所述器件控制电路的第二端一一对应地与四个所述输出子焊盘通过连接引线连接；
    所述参考电压子焊盘与所述参考电压引线之间通过与所述第十参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第十输入过孔交叠的所述连接引线连接。
  33. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括两个参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
    在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继 信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；n为大于1的正整数且不大于一个所述信号通道内的所述控制区域的数量；
    在任意一个所述第一控制区域中，在所述第二方向上，所述参考电压子焊盘位于所述选通信号子焊盘与所述第一参考过孔之间；其中一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第一参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
  34. 根据权利要求21所述的阵列基板，其中，在任意一个所述控制区域内，所述阵列基板设置有一个所述芯片焊盘组，且所述芯片焊盘组位于所述控制区域的四个所述器件区之间；所述芯片焊盘组包括两个参考电压子焊盘、芯片电源子焊盘、驱动数据子焊盘、选通信号子焊盘、中继信号子焊盘和四个输出子焊盘；四个所述器件区内的所述器件控制电路的第二端与四个所述输出子焊盘一一对应的通过所述连接引线电连接；
    在一个所述信号通道区域内，各个所述控制区域依次编号，其中，编号为1的所述控制区域位于所述信号通道区域在其延伸方向上的一端；各个所述控制区域中的所述芯片焊盘组按照所述控制区域的编号顺序依次级联；编号为1的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘与所述地址引线之间，通过与所述地址过孔交叠的所述连接引线连接；编号为(n-1)的所述控制区域中的所述芯片焊盘组的所述中继信号子焊盘与编号为n的所述控制区域中的所述芯片焊盘组的所述选通信号子焊盘通过所述连接引线连接；
    当所述布线基板包括所述第五参考过孔时，在任意一个所述第一控制区域中，在所述第二方向上，所述参考电压子焊盘位于所述选通信号子焊盘与所述第一参考过孔之间；所述芯片焊盘组位于所述第五参考过孔的第二方向一侧；其中一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第一参考过孔交叠的所述连接引线连接；另一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第五参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第一输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线之间通过与所述第三输入过孔交叠的所述连接引线连接。
  35. 根据权利要求33或者34所述的阵列基板，其中，当所述布线基板包括所述第二控制区域时，在任意一个所述第二控制区域内，所述第一器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第七电源过孔交叠的所述连接引线连接；所述第三器件区内的所述器件控制电路的第一端与所述第一电源电压引线之间，通过与所述第八电源过孔交叠的所述连接引线连接；所述第二器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第九电源过孔交叠的所述连接引线连接；所述第四器件区内的所述器件控制电路的第一端与所述第二电源电压引线之间，通过与所述第十电源过孔交叠的所述连接引线连接；四个所述器件区内的所述器件控制电路的第二端一一对应地与四个所述输出子焊盘通过连接引线连接；
    其中一个所述参考电压子焊盘与所述参考电压引线之间通过与所述第十参考过孔交叠的所述连接引线连接；所述芯片电源子焊盘和所述驱动数据子焊盘中的一个与所述第一输入引线之间通过与所述第八输入过孔交叠的所述连接引线连接，另一个与所述第二输入引线间通过与所述第十输入过孔交叠的所述连接引线连接。
  36. 一种发光模组，包括权利要求19～35任意一项所述的阵列基板。
PCT/CN2021/074260 2021-01-28 2021-01-28 布线基板、阵列基板和发光模组 WO2022160220A1 (zh)

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