WO2024083228A1 - 电路板和工作组件 - Google Patents

电路板和工作组件 Download PDF

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Publication number
WO2024083228A1
WO2024083228A1 PCT/CN2023/125699 CN2023125699W WO2024083228A1 WO 2024083228 A1 WO2024083228 A1 WO 2024083228A1 CN 2023125699 W CN2023125699 W CN 2023125699W WO 2024083228 A1 WO2024083228 A1 WO 2024083228A1
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WO
WIPO (PCT)
Prior art keywords
chips
chip
circuit board
board according
chip array
Prior art date
Application number
PCT/CN2023/125699
Other languages
English (en)
French (fr)
Inventor
张少华
杨欢
张楠赓
Original Assignee
北京嘉楠捷思信息技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京嘉楠捷思信息技术有限公司 filed Critical 北京嘉楠捷思信息技术有限公司
Publication of WO2024083228A1 publication Critical patent/WO2024083228A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/20009—Modifications to facilitate cooling, ventilating, or heating using a gaseous coolant in electronic enclosures
    • H05K7/20136—Forced ventilation, e.g. by fans
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/20009—Modifications to facilitate cooling, ventilating, or heating using a gaseous coolant in electronic enclosures
    • H05K7/20136—Forced ventilation, e.g. by fans
    • H05K7/20145—Means for directing air flow, e.g. ducts, deflectors, plenum or guides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2039—Modifications to facilitate cooling, ventilating, or heating characterised by the heat transfer by conduction from the heat generating element to a dissipating body
    • H05K7/20409—Outer radiating structures on heat dissipating housings, e.g. fins integrated with the housing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of heat dissipation technology, and in particular to a circuit board and a working component.
  • the embodiments of the present application provide a circuit board and an electronic device to solve or alleviate one or more technical problems in the prior art.
  • an embodiment of the present application provides a circuit board, on which a chip array is arranged, the chip array includes multiple power taking units, the power taking units include at least one chip, wherein the distances between at least some adjacent power taking units are not equal.
  • the embodiments of the present application provide a circuit board, which is provided with a chip array, and the chip array includes multiple chips and at least one vacant position.
  • the embodiments of the present application provide a circuit board, on which multiple chipsets are arranged, each chipset includes at least one row of chips and/or at least one column of chips, and the spacing between at least some adjacent chipsets is not equal to the spacing between adjacent chips in any chipset.
  • the embodiments of the present application provide a working component, including a circuit board, a radiator, the radiator including a heat dissipation body and heat dissipation fins, the heat dissipation body including a first surface and a second surface opposite to each other, and the first surface is connected to the heat dissipation fins.
  • FIG1A is a schematic diagram showing the structure of a circuit board according to an embodiment of the present application.
  • FIG1B is a schematic diagram showing the structure of a circuit board according to the first embodiment of the present application.
  • FIG. 2A shows a schematic diagram of the structure of a circuit board according to the second embodiment of the present application.
  • FIG. 2B shows a current diagram of the circuit board shown in FIG. 2A .
  • FIG. 2C shows a signal diagram of the circuit board shown in FIG. 2A .
  • FIG3 shows a schematic diagram of the structure of a circuit board according to a third embodiment of the present application.
  • FIG4 shows a schematic diagram of the structure of a circuit board according to a fourth embodiment of the present application.
  • FIG5 is a schematic diagram showing the structure of a circuit board according to a fifth embodiment of the present application.
  • FIG6A shows a schematic diagram of the structure of a circuit board according to a sixth embodiment of the present application.
  • FIG6B shows another schematic structural diagram of a circuit board according to the sixth embodiment of the present application.
  • FIG. 7 shows a schematic diagram of the structure of a circuit board according to Embodiment 7 of the present application.
  • FIG8 shows a schematic diagram of the structure of a circuit board according to an eighth embodiment of the present application.
  • FIG9 shows a schematic structural diagram of a circuit board according to a ninth embodiment of the present application.
  • FIG10 is a schematic diagram showing the structure of a circuit board according to the tenth embodiment of the present application.
  • FIG. 11 shows a schematic diagram of the structure of a circuit board according to the eleventh embodiment of the present application.
  • FIG. 12 is a schematic diagram showing the structure of a circuit board according to the twelfth embodiment of the present application.
  • FIG13 shows a schematic diagram of the structure of a circuit board according to the thirteenth embodiment of the present application.
  • FIG. 14 shows a schematic diagram of the structure of a circuit board according to a fourteenth embodiment of the present application.
  • FIG15 is a schematic diagram showing the structure of a circuit board according to the fifteenth embodiment of the present application.
  • FIG16 shows a schematic diagram of the structure of a circuit board according to a sixteenth embodiment of the present application.
  • FIG17 shows a schematic diagram of the structure of a circuit board according to Embodiment 17 of the present application.
  • FIG. 18 shows a schematic diagram of the structure of a circuit board according to the eighteenth embodiment of the present application.
  • FIG19A shows a schematic diagram of the structure of a circuit board according to the nineteenth embodiment of the present application.
  • FIG. 19B shows a current diagram of the circuit board shown in FIG. 19A .
  • Figure 20 shows a schematic diagram of the structure of a circuit board according to embodiment 20 of the present application.
  • Figure 21A shows a schematic diagram of the structure of a circuit board according to embodiment 21 of the present application.
  • FIG21B shows a current diagram of the circuit board shown in FIG21A
  • FIG. 22 shows a schematic diagram of the structure of an electronic device according to an embodiment of the present application.
  • FIG. 23 is a schematic diagram showing the structure of a working component according to an embodiment of the present application.
  • the arrangement of chips on a circuit board is a single chip arrangement or a plurality of chips arranged unevenly or irregularly, and the heat dissipation uniformity is poor.
  • FIG1A is a schematic diagram of the structure of the circuit board 110 involved in the present application. As shown in FIG1A , multiple chips on the circuit board 110 are arranged in an array, and the row spacing of multiple chips 111 is the same, and the column spacing of multiple chips 111 is the same. The total number of chips in the chip array is large, which can improve the computing power of the circuit board 110, thereby improving the overall performance of the circuit board 110, and the array arrangement method can improve the heat dissipation uniformity of multiple chips 111.
  • the embodiment of the present application provides a circuit board 110, on which a chip array is arranged, the chip array includes a plurality of power taking units 114, the power taking unit 114 includes at least one chip 111, wherein the distances between at least some adjacent power taking units 114 are not equal.
  • "plurality" means two or more.
  • the power taking units 114 can be connected in series, and the chips 111 in the power taking units 114 can be connected in parallel.
  • the chip array includes 40 power taking units 114 connected in series, and the 40 power taking units 114 are connected in series.
  • Each power taking unit 114 includes 3 chips 111 connected in parallel, so there are 21 power taking units 114 on the left and 19 power taking units 114 on the right. Among them, the distance between the 9th and 10th power taking units 114 on the right from top to bottom is not equal to the distance between other adjacent power taking units 114.
  • FIG. 1B the distances between at least some adjacent power extraction units 114 are not equal, and a similar situation also exists in the circuit boards 110 of FIGS. 2A to 17 and 19A to 21B .
  • a heat dissipation channel is formed between adjacent power taking units 114 with unequal distances, which is beneficial to the heat dissipation of the circuit board 110 .
  • the chips in the chip array have the same size, and the total number of chips in the chip array is greater than or equal to 20 or 50.
  • each chip is rectangular, and the total number of chips in the chip array is 120. Therefore, in FIG. 1B , the chips in the chip array have the same size, and the total number of chips in the chip array is greater than or equal to 20 or 50.
  • a similar situation also exists in the circuit board 110 of FIGS. 2A to 21B .
  • the versatility of the chips 111 can be improved and processing can be facilitated; by making the total number of chips 111 in the chip array greater than or equal to 20 or 50, the total number of chips in the chip array is large, which can improve the computing power of the circuit board 110, thereby improving the overall performance of the circuit board 110.
  • the distance between at least some adjacent power taking units 114 is greater than the distance between other adjacent power taking units 114.
  • the 21 power taking units 114 in the left 3 columns, i.e., the first distribution area are evenly spaced, and the distance between the 9th and 10th power taking units 114 in the right 3 columns, i.e., the second distribution area, from top to bottom, is greater than the distance between other adjacent power taking units 114.
  • the 19 power taking units 114 in the second distribution area can be divided according to the spacing between adjacent power taking units 114, and the 19 power taking units 114 can be divided into two sub-areas.
  • the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between the two sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 at both ends of the series connection direction in each sub-area and the chip 111 at the center position is smaller, thereby effectively reducing the temperature of the chip 111 at the center position in each sub-area, and thereby reducing the temperature difference between multiple chips 111 in the sub-area.
  • the length of the electrical connection line between at least some adjacent power taking units 114 is longer than the length of the electrical connection line between other adjacent power taking units 114, wherein the length direction is perpendicular to the parallel connection direction of the power taking units 114.
  • the electrical connection line may include a power line 115 and/or a signal line 116.
  • the distance between the 7th power taking unit 114 and the 8th power taking unit 114 on the right side, as well as the distance between the 12th power taking unit 114 and the 13th power taking unit 114 can be greater than the distance between other adjacent power taking units 114, so in the up-down direction, the length of the electrical connection line between the 7th power taking unit 114 and the 8th power taking unit 114 on the right side, as well as the length of the electrical connection line between the 12th power taking unit 114 and the 13th power taking unit 114 are longer than the length of the electrical connection line between other adjacent power taking units 114; that is, there is a large gap between adjacent power taking units 114 to form a heat dissipation channel, and the formation of a heat dissipation channel is beneficial to the heat dissipation of the circuit board 110. Similar situations also exist in Figures 1B, 3 to 17, and FIG. 19A to the circuit board 110 of Figures 21A to 21
  • the other adjacent power taking units 114 are adjacent power taking units 114 in the same row or column.
  • the other adjacent power taking units 114 may be non-edge power taking units 114 in the chip array in a parallel direction perpendicular to the power taking units 114.
  • the adjacent power taking units 114 in the 1st to 7th power taking units 114 arranged in the same column on the right the adjacent power taking units 114 in the 8th to 12th power taking units 114 arranged in the same column on the right, and the adjacent power taking units 114 in the 13th to 19th power taking units 114 arranged in the same column on the right. Similar situations also exist in the circuit board 110 of FIG. 1B, FIG. 3 to FIG. 17, and FIG. 19A to FIG. 21B.
  • the circuit board 110 can be applied to an electronic device 3100 such as a computing device.
  • a heat dissipation duct is defined in the electronic device 3100, and the circuit board 110 can work in the heat dissipation duct.
  • the heat dissipation direction of the circuit board 110 is the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the heat dissipation source of the circuit board 110 can be an air-cooled heat source (such as a fan) or a liquid-cooled heat source.
  • the heat dissipation direction is from left to right.
  • the distance between the power taking units 114 on the left and right sides can be greater than the distance between two adjacent columns of chips in each power taking unit 114.
  • the distance between the left and right power taking units 114 can be equal to the distance between two adjacent columns of chips in each power taking unit 114; or, along the left-right direction, the distance between the left and right power taking units 114 can be smaller than the distance between two adjacent columns of chips in each power taking unit 114; or, along the left-right direction, the distance between multiple columns of chips can gradually increase or decrease.
  • the rectangular area of the circuit board 110 occupied by the chip array is divided into a plurality of distribution areas, and the number of power extraction units 114 in at least two distribution areas is unequal.
  • the rectangular area of the circuit board 110 occupied by the chip array is divided into two distribution areas, that is, the value Y with the largest number of row chips divides the chip array into two distribution areas, the two distribution areas are the first distribution area (for example, the left three columns of chips in FIG. 1B ) and the second distribution area (for example, the right three columns of chips in FIG. 1B ), and the number of power extraction units 114 in the first distribution area and the second distribution area is not equal.
  • the first distribution area includes 63 chips 111 arranged in 21 rows and 3 columns, and the 3 chips 111 in each row of the first distribution area are connected in parallel to form 1 power extraction unit 114, so the first distribution area includes 21 power extraction units 114.
  • the second distribution area includes 57 chips 111 arranged in 19 rows and 3 columns, and the 3 chips 111 in each row of the second distribution area are connected in parallel to form 1 power extraction unit 114, so the second distribution area includes 19 power extraction units 114.
  • the value Y with the largest number of row chips can also divide the chip array into more than two distribution areas. This application does not limit the number of distribution areas.
  • the chip row direction is the heat dissipation direction
  • the number of chip columns in each distribution area is the same
  • the chip column direction is the heat dissipation direction
  • the number of chip rows in each distribution area is the same.
  • the chip row direction is In the heat dissipation direction
  • the number of columns of the first distribution area and the second distribution area are both 3. Similar situations also exist in FIG. 1B and FIG. 3 to FIG. 17 .
  • the number of power taking units 114 in multiple distribution areas decreases.
  • the number of power taking units 114 in the first distribution area is 21, and the number of power taking units 114 in the second distribution area is 19.
  • the present application is not limited to this.
  • the number of power taking units 114 in a distribution area is greater than 2
  • the number of power taking units 114 in adjacent distribution areas is not reduced one by one, and the number of power taking units 114 in several adjacent distribution areas is allowed to increase along the heat dissipation direction, as long as the spacing between adjacent distribution areas is generally increasing in the left-right direction.
  • the number of distribution areas is 6 for illustration.
  • the number of power taking units 114 in multiple distribution areas can be 15, 14, 13, 12, 11, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 12, 12, 11, 11, 10, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 11, 10, 10, 10, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 16, 15, 13, 14, 12, 10 respectively.
  • the total number of chips in the front half near the air inlet is greater than the total number of chips in the back half near the air outlet, which can reduce the maximum temperature difference between the chip 111 near the air outlet and the chip 111 near the air inlet, thereby improving the temperature uniformity of the chip 111.
  • the rectangular area of the circuit board 110 occupied by the chip array is divided into a plurality of sub-areas.
  • the chip array is divided into a plurality of sub-regions due to the existence of the chip vacant positions 113, so that the spacing between at least some adjacent sub-regions is greater than or equal to the spacing required to accommodate one chip.
  • chip vacancy 113 between the 9th and 10th rows of the three right columns of chips in the chip array, thereby dividing the three left columns of chips into one sub-region, dividing the 1st to 9th rows of the three right columns of chips into one sub-region, and dividing the 10th to 19th rows of the three right columns of chips into one sub-region, that is, the chip vacancy 113 divides the chip array into three sub-regions.
  • chip vacancies 113 between rows 7 and 8 and between rows 12 and 13 of the three right columns of chips in the chip array, thereby dividing the three left columns of chips into one sub-region, dividing rows 1 to 7 of the three right columns of chips into one sub-region, dividing rows 8 to 12 of the three right columns of chips into one sub-region, and dividing rows 13 to 19 of the three right columns of chips into one sub-region, that is, the chip vacancies 113 divide the chip array into four sub-regions.
  • FIG6A there is a chip vacancy 113 between the 10th and 11th rows of the three left columns of chips in the chip array, and there is a chip vacancy 113 between the 7th and 8th rows and between the 12th and 13th rows of the three right columns of chips in the chip array, so that the 1st to 10th rows of the three left columns of chips are divided into a sub-region, the 11th to 20th rows of the three left columns of chips are divided into a sub-region, the 1st to 7th rows of the three right columns of chips are divided into a sub-region, the 8th to 12th rows of the three right columns of chips are divided into a sub-region, and the 13th to 19th rows of the three right columns of chips are divided into a sub-region.
  • a row is divided into a sub-region, that is, the chip vacant position 113 divides the chip array into five sub-regions.
  • the sub-region is composed of at least one power extraction unit 114, and the distance between two adjacent sub-regions is greater than the distance between adjacent power extraction units 114 in the sub-region.
  • the power extraction unit 114 includes at least one chip 111.
  • the chips 111 in the power extraction unit 114 are in the same row or column and connected in parallel.
  • the chips in each sub-region are connected in parallel in the same direction, and the spacing of at least some adjacent sub-regions along the direction perpendicular to the parallel connection direction of the chips is not equal to the spacing of adjacent power extraction units 114 in any sub-region.
  • the sub-region includes multiple power extraction units 114, and the multiple power extraction units 114 are connected in series.
  • the chips in each sub-region are connected in series in the same direction, and the spacing of at least some adjacent sub-regions along the chip series connection direction is not equal to the spacing of adjacent power extraction units 114 in any sub-region.
  • the chips 111 between the sub-regions can be arranged with equal spacing or unequal spacing or increasing spacing or decreasing spacing along the row and column directions, but the spacing between at least some adjacent sub-regions will be different from the spacing of adjacent chips contained in the sub-region due to the existence of chip vacancies 113.
  • the electrical connection method of the chips 111 in the above embodiment is not limited to series connection and parallel connection.
  • the chips can also be connected in other electrical connection methods such as a combination of series connection and parallel connection.
  • the number of power taking units 114 in at least two sub-areas may be equal or unequal.
  • the maximum value of the number of column chips in the chip array is X, and the circuit board area occupied by the chip array can be divided into multiple sub-areas based on X. In the example of FIG1B , X is 21.
  • the 1st to 9th power taking units 114 in the second distribution area can be divided into a sub-area, which includes 27 chips arranged in 9 rows and 3 columns; the 10th to 19th power taking units 114 are divided into another sub-area, which includes 30 chips arranged in 10 rows and 3 columns.
  • the 19 power taking units 114 in the second distribution area are divided into two sub-areas, and the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between the two sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 located at both ends of the series direction in each sub-area and the chip 111 at the center position is smaller, which effectively reduces the temperature of the chip located at the center position in each sub-area, and thereby reduces the temperature difference between multiple chips 111 in the sub-area.
  • the height of the circuit board area occupied by the chip array in the vertical heat dissipation direction is H.
  • the circuit board area occupied by the chip array can also be divided into multiple sub-areas based on H.
  • the multiple sub-regions include two end regions and one middle region, and the heights of the two end regions and one middle region are both H/3.
  • the number of rows in each end region and the middle region can be equal.
  • the above-mentioned region height is not limited to H/3.
  • the end region can also be set to H/4, and the middle region height is H/2. This application does not make specific limitations here.
  • the power taking unit 114 can be divided into different sub-regions according to design requirements, and it is sufficient to ensure that the distances between at least some adjacent power taking units 114 are not equal, so as to form a heat dissipation channel, which is beneficial to the heat dissipation of the circuit board 110.
  • the plurality of sub-regions include two end regions and a middle region.
  • the number of power taking units 114 in the end region is greater than the number of power taking units 114 in the middle region.
  • the 1st to 7th power taking units 114 in the second distribution area can be divided into the first sub-region, which includes 21 chips 111 arranged in 7 rows and 3 columns; the 8th to 12th power taking units 114 are divided into the second sub-region, which includes 15 chips 111 arranged in 5 rows and 3 columns; the 13th to 19th power taking units 114 are divided into the third sub-region, which also includes 21 chips 111 arranged in 7 rows and 3 columns.
  • the number of power taking units 114 in the end region is 7, and the number of power taking units 114 in the middle region is 5.
  • the number of power taking units 114 increases from the middle area to the end area.
  • the number of power taking units 114 in the end area is 7, and the number of power taking units 114 in the middle area is 5.
  • the number of chips in the end areas is 21, and the number of chips in the middle area is 15. Therefore, when the circuit board 110 is applied to the electronic device 3100, the chips in the two end areas are closer to the external environment and the heat dissipation is better.
  • the chip temperature in the middle area can be effectively reduced, thereby reducing the temperature difference between the chips 111 in the middle area and the chips 111 in the end area, improving the heat dissipation effect of the circuit board 110, and ensuring the overall performance of the circuit board 110.
  • the plurality of sub-regions include two end regions and one middle region, and the number of chips corresponding to the end regions is greater than or equal to the total number of chips in the middle region.
  • the chips in the end regions are the chips 111 in the first sub-region and the chips 111 in the third sub-region
  • the chips 111 in the middle region are the chips 111 in the second sub-region.
  • the first sub-region and the third sub-region include 21 chips 111 respectively
  • the second sub-region includes 15 chips 111
  • the number of chips corresponding to the end regions is greater than the total number of chips in the middle region.
  • the chip temperature in the middle region can be further reduced, thereby reducing the temperature difference between the chips 111 in the middle region and the chips 111 in the end regions, improving the heat dissipation effect of the circuit board 110, and ensuring the overall performance of the circuit board 110.
  • the average chip spacing in the end regions is smaller than the average chip spacing in the middle region.
  • the two end regions include a first end region and a second end region, and the number of power taking units 114 in the first end region is less than the number of power taking units 114 in the second end region, wherein, in the vertically placed state of the circuit board 110, the first end region is close to the top of the circuit board 110, and the second end region is close to the bottom of the circuit board 110. In this way, due to the end region disposed close to the top The region can better exchange heat with the external environment.
  • the total heat generated by the chip 111 in the second end region can be reduced, thereby effectively reducing the chip temperature in the second end region, thereby reducing the temperature difference between the chip 111 in the first end region and the chip 111 in the second end region, and improving the heat dissipation effect of the circuit board 110.
  • metal parts are provided between adjacent power taking units 114, and along the series direction, the length of the metal parts between at least some adjacent power taking units 114 is longer than that of other adjacent power taking units 114, wherein the length direction is perpendicular to the parallel direction of the power taking units 114.
  • the length direction is the up-down direction.
  • the spacing between the 7th power taking unit 114 and the 8th power taking unit 114 on the right side and the spacing between the 12th power taking unit 114 and the 13th power taking unit 114 can be greater than the spacing between other adjacent power taking units 114, so that in the up-down direction, the length of the metal parts between the 7th power taking unit 114 and the 8th power taking unit 114 on the right side and the length of the metal parts between the 12th power taking unit 114 and the 13th power taking unit 114 are longer than the length of the metal parts between other adjacent power taking units 114.
  • Similar situations also exist in the circuit board 110 of FIG. 1B, FIG. 3 to FIG. 17, and FIG. 19A to FIG. 21B.
  • the other adjacent power taking units 114 are adjacent power taking units 114 in the same row or column; in the direction perpendicular to the parallel direction, the other adjacent power taking units 114 are non-edge power taking units 114 in the chip array.
  • the spacing between the two power supply groups can be greater than the spacing between adjacent power supply units 114 in each power supply group, thereby making the distance between the chips at both ends of the series connection direction in each power supply group and the chip at the center position smaller, effectively reducing the temperature of the chip at the center position in each power supply group, thereby reducing the temperature difference between multiple chips in the power supply group.
  • the metal piece can be a copper sheet or an aluminum sheet, which is welded on the circuit board 110 to dissipate heat for the two adjacent working chips connected thereto and reduce the voltage drop between the two adjacent working chips connected thereto.
  • the thickness of the metal piece is less than or equal to the thickness of the chip.
  • the thickness direction of the metal piece and the thickness direction of the chip are perpendicular to the direction of the circuit board 110.
  • the chip row direction may be the parallel connection direction of the plurality of chips 111 (e.g., the left-right direction in FIG1B ).
  • the chip row direction may also be perpendicular to the parallel connection direction of the chips 111 (e.g., the left-right direction in FIG19A ).
  • the chip row direction is the heat dissipation direction (eg, the left-right direction in FIG. 1B ), and the chip column direction is perpendicular to the heat dissipation direction.
  • the circuit board 110 of FIG. 2A to FIG. 17 A similar situation also exists in the circuit board 110 of FIG. 2A to FIG. 17 .
  • the parallel connection direction of the chip array is a heat dissipation direction (eg, the left-right direction in FIG. 1B ).
  • a similar situation also exists in the circuit board 110 of FIGS. 2A to 17 .
  • the operating temperature difference range between the chips 111 of the chip array is 0-10°C (including the endpoint value).
  • the temperature difference between the chips 111 can be 8-10°C (including the endpoint value).
  • the above operating temperature difference range is not limited to 0-10°C.
  • the temperature difference between the highest temperature and the lowest temperature of the chip on the circuit board is 5-12°C (including the endpoint values).
  • the temperature difference of the chips in the arrangement in FIG. 1A is 20-40°C (including the endpoint values)
  • the temperature difference of the chips in the arrangement of the power extraction unit 114 in FIG. 1B to FIG. 21B of the present application is 10-20°C (including the endpoint values).
  • the centers of each row or column of chips are on the same straight line.
  • the 120 chips in the chip array are arranged in 21 rows and 6 columns, the centers of each row of chips are on a straight line, and the centers of each column of chips are on a straight line.
  • the row spacing of the first 3 columns of chips is the same, and the 10th and 11th rows of the last 3 columns of chips are missing.
  • the number of chips in the first 3 columns is 63, and the number of chips in the last 3 columns is 57.
  • the row direction of the chip array can be the heat dissipation direction.
  • the total number of chips in the front half near the air inlet is greater than the total number of chips in the back half near the air outlet.
  • the number of chips 111 at the air inlet is large, which can increase the heat generation of the chip 111 at the air inlet.
  • the number of chips 111 at the air outlet is small, which can reduce the heat generation of the chip 111 at the air outlet, thereby further reducing the maximum temperature difference between the chip 111 near the air outlet and the chip 111 near the air inlet, thereby improving the temperature uniformity of the chip 111. Similar situations also exist in the circuit board 110 of FIGS. 2A to 21B.
  • the total number of chips in the chip array and the number of vacancies 113 is X*Y.
  • X is 21 and Y is 6.
  • the total number of chips in the chip array and the number of vacancies 113 is 126. Among them, the number of chips in the chip array is 120 and the number of vacancies 113 is 6.
  • the maximum value Y of the number of row chips divides the chip array into at least two distribution areas.
  • the total number of chips A in the first Y/2 columns of the chip array is greater than the total number of chips B in the last Y/2 columns of the chip array.
  • Y is an even number 6
  • the total number of chips in the first 3 columns of the chip array is 63
  • the total number of chips in the last 3 columns of the chip array is 57.
  • the total number of chips C in the first (Y-1)/2 columns of the chip array is greater than the total number of chips D in the last (Y-1)/2 columns of the chip array.
  • Y is 7.
  • the total number of chips C in the first 3 columns of the chip array is greater than the total number of chips D in the last 3 columns of the chip array.
  • the total number of chips in the first half near the air inlet is greater than the total number of chips in the second half near the air outlet, which can reduce the maximum temperature difference between the chip 111 near the air outlet and the chip 111 near the air inlet, thereby improving the temperature uniformity of the chip 111.
  • the total number of chips A in the first Y/2 columns of the chip array and the corresponding columns can be less than the number of chips
  • the total number of chips in the Y/2 columns and the corresponding columns after the array is B.
  • Y is an even number 6
  • the total number of chips in the first 3 columns of the chip array is 57
  • the total number of chips in the last 3 columns of the chip array is 63.
  • the total number of chips C in the first (Y-1)/2 columns of the chip array and the corresponding columns can also be less than the total number of chips D in the last (Y-1)/2 columns of the chip array and the corresponding columns.
  • the total number of chips C in the first 3 columns of the chip array can be less than the total number of chips D in the last 3 columns of the chip array.
  • the present application is not limited thereto, and if Y is an even number, the total number of chips A in the first Y/2 columns and the corresponding columns of the chip array may also be equal to the total number of chips B in the last Y/2 columns and the corresponding columns of the chip array.
  • Y is an even number 6
  • the total number of chips in the first 3 columns of the chip array is 57
  • the total number of chips in the last 3 columns of the chip array is 57.
  • the total number of chips C in the first (Y-1)/2 columns and the corresponding columns of the chip array is equal to the total number of chips D in the last (Y-1)/2 columns and the corresponding columns of the chip array.
  • Y take Y as 7 as an example.
  • the total number of chips C in the first 3 columns of the chip array can be equal to the total number of chips D in the last 3 columns of the chip array.
  • the present application also provides a working assembly 2100, including a circuit board 110 and a heat sink 2110.
  • the circuit board 110 is the circuit board 110 in any of the above embodiments
  • the heat sink 2110 includes a heat sink body and heat sink fins
  • the heat sink body includes a first surface and a second surface opposite to each other, and the first surface is connected to the heat sink fins.
  • the heat sink 2110 may be an air-cooled heat sink 2110 or a liquid-cooled heat sink 2110.
  • the heat sink 2110 may be located on the side of the circuit board 110 where the working chip is provided, and is used to dissipate heat for the circuit board 110.
  • the heat sink 2110 may also be located on the side of the circuit board 110 where no chip is provided. Alternatively, chips are provided on both sides of the circuit board 110, and heat sinks 2110 are provided on both sides of the circuit board 110, respectively.
  • the second surface is provided with a plurality of bosses, each boss being provided corresponding to each row or column of the power taking unit 114. In this way, the heat generated by the chip in the power taking unit 114 during operation can be effectively transferred to the heat sink 2110 through the bosses, thereby improving the heat dissipation effect.
  • a plurality of bosses are provided on the second surface, and at least some of the bosses may also be provided at corresponding positions between at least some of the adjacent power taking units 114.
  • the 117 chips on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the number of chips in the 6th row, the 11th row and the 16th row are 3 respectively, and the number of chips in the other rows is 6, so the number of chips in the 6th row, the 11th row and the 16th row is less than the number of chips in the other rows.
  • the bosses may be provided at corresponding positions between the 5th power taking unit 114 and the 6th power taking unit 114, the corresponding positions between the 9th power taking unit 114 and the 10th power taking unit 114, and the corresponding positions between the 13th power taking unit 114 and the 14th power taking unit 114 in the second distribution area.
  • the present application embodiment provides a circuit board 110, on which a chip array is arranged.
  • the chip array includes A plurality of chips 111 and at least one vacant position 113.
  • "plurality" means two or more.
  • the chip array may include two types of chip 111 connection modes, namely, serial connection and parallel connection.
  • the chip array includes 120 chips 111 and 6 vacancies 113.
  • the three left columns of the chip array include 63 chips 111, and no vacancies 113 are set in the three left columns.
  • the three right columns of the chip array include 57 chips 111, and two rows of 6 vacancies 113 are set between the 9th row of chips 111 and the 10th row of chips 111 on the right side of the three right columns from top to bottom.
  • the chip array includes multiple chips 111 and at least one vacant position 113 , and a similar situation also exists in the circuit board 110 of FIG2A to FIG21B .
  • a heat dissipation channel is formed at the vacant position 113 of the chip array, which is beneficial to the heat dissipation of the circuit board 110 .
  • the chips 111 in the chip array have the same size, and the total number of chips 111 in the chip array is greater than or equal to 20 or 50.
  • each chip 111 is rectangular, and the total number of chips 111 in the chip array is 120. Therefore, in FIG. 1B , the chips 111 in the chip array have the same size, and the total number of chips 111 in the chip array is greater than or equal to 20 or 50.
  • a similar situation also exists in the circuit board 110 of FIGS. 2A to 21B .
  • the versatility of the chips 111 can be improved and processing can be facilitated; by making the total number of chips 111 in the chip array greater than or equal to 20 or 50, the total number of chips 111 in the chip array is relatively large, which can improve the computing power of the circuit board 110, thereby improving the overall performance of the circuit board 110.
  • the size of the vacant position 113 is greater than or equal to the size of a single chip 111 in the chip array, and the space corresponding to the vacant position 113 can accommodate at least one chip 111.
  • the "size of the vacant position 113" includes the length and/or width of the vacant position 113. With this arrangement, the heat dissipation channel at the vacant position 113 of the chip array has a larger size, which can reduce wind resistance and improve heat dissipation effect.
  • the spacings between at least some adjacent chips 111 in the chip array are unequal.
  • At least one vacant position 113 is arranged in the row direction of the chip array, so that there are unequal spacings between adjacent chips 111 in at least one row of chips 111 in the chip array.
  • the row direction is the left-right direction.
  • the chip array includes 76 chips 111 and 4 vacant positions 113.
  • the 4 vacant positions 113 are respectively located in the 3rd row and the 3rd column, the 4th row and the 3rd column, the 5th row and the 3rd column, and the 6th row and the 3rd column.
  • the distance between the 2nd chip 111 and the 3rd chip 111 from right to left in the 3rd row is greater than the distance between the remaining adjacent chips 111; the distance between the 2nd chip 111 and the 3rd chip 111 from right to left in the 4th row is greater than the distance between the remaining adjacent chips 111; the distance between the 2nd chip 111 and the 3rd chip 111 from right to left in the 5th row is greater than the distance between the remaining adjacent chips 111; The distance between them is greater than the distance between the other adjacent chips 111 ; the distance between the second chip 111 and the third chip 111 from right to left in the 6th row is greater than the distance between the other adjacent chips 111 .
  • At least one vacant position 113 is located in the column direction of the chip array, so that there are unequal spacings between adjacent chips 111 in at least one column of chips 111 in the chip array.
  • the row direction is the left-right direction.
  • the chip array includes 123 chips 111 and 3 vacant positions 113. Among them, the 3 vacant positions 113 are respectively located in the 6th column and the 10th to 12th rows from left to right. Thus, the distance between the 9th chip 111 and the 10th chip 111 from top to bottom in the 6th row is greater than the distance between the remaining adjacent chips 111.
  • the chip array includes a plurality of power taking units 114, and the chips 111 in the power taking units 114 are connected in parallel.
  • the chip array includes 40 power taking units 114, and the 40 power taking units 114 are connected in series.
  • Each power taking unit 114 includes 3 chips 111 connected in parallel, so that there are 21 power taking units 114 on the left and 19 power taking units 114 on the right. Among them, the distance between the 9th and 10th power taking units 114 on the right from top to bottom is not equal to the distance between other adjacent power taking units 114.
  • the chip array includes 10 power taking units 114, and the 10 power taking units 114 are connected in series.
  • Each power taking unit 114 includes 10 chips 111 connected in parallel, so that there are 5 power taking units 114 on the upper side and 5 power taking units 114 on the lower side.
  • the distance between the fifth and sixth power taking units 114 from top to bottom is not equal to the distance between other adjacent power taking units 114 .
  • the total number of vacant positions 113 is an integer multiple of the number of chips 111 included in a power extraction unit 114.
  • the total number of chips 111 in the chip array may be an integer multiple of the power extraction unit 114.
  • the chip array includes 120 chips 111 and 6 vacant positions 113, the number of chips 111 included in a power extraction unit 114 is 3, and the total number of vacant positions 113 is 2 times the number of chips 111 included in a power extraction unit 114.
  • the chip array includes 100 chips 111 and 10 vacant positions 113, the number of chips 111 included in a power extraction unit 114 is 10, and the total number of vacant positions 113 is 1 times the number of chips 111 included in a power extraction unit 114.
  • the length of the electrical connection line between the two power taking units 114 adjacent to the front and rear of the vacant position 113 is longer than the length of the electrical connection line between other adjacent power taking units 114, wherein the length direction is perpendicular to the parallel direction of the chips 111 of the chip array.
  • the parallel direction of the chips 111 is the left-right direction
  • the parallel direction of the chips 111 of the vertical chip array is the up-down direction.
  • the electrical connection line may include a power line 115 and/or a signal line 116.
  • the spacing between the 7th power taking unit 114 and the 8th power taking unit 114 on the right and the spacing between the 12th power taking unit 114 and the 13th power taking unit 114 may be greater than the spacing between other adjacent power taking units 114, and thus in the up-down direction, the length of the electrical connection line between the 7th power taking unit 114 and the 8th power taking unit 114 on the right is greater than the spacing between the other adjacent power taking units 114.
  • the length of the electrical connection line between the 12th power taking unit 114 and the 13th power taking unit 114 is longer than the length of the electrical connection line between other adjacent power taking units 114. Similar situations also exist in the circuit board 110 of Figures 1B, 3 to 17, and 19A to 21B.
  • the other adjacent power taking units 114 have the same row or the same column.
  • the other adjacent power taking units 114 may be non-edge power taking units 114 in the chip array in a parallel direction perpendicular to the power taking units 114.
  • the adjacent power taking units 114 in the 1st to 7th power taking units 114 arranged in the same column on the right side the adjacent power taking units 114 in the 8th to 12th power taking units 114 arranged in the same column on the right side, and the adjacent power taking units 114 in the 13th to 19th power taking units 114 arranged in the same column on the right side. Similar situations also exist in the circuit board 110 of FIG. 1B, FIG. 3 to FIG. 17, and FIG. 19A to FIG. 21B.
  • the chip array is set to X*Y, and the maximum number of column chips in the column direction of the chip array is X, and the maximum number of row chips in the row direction of the chip array is Y.
  • the total number of chips 111 and the number of vacancies 113 in the chip array is X*Y.
  • X is 21, and Y is 6.
  • the total number of chips 111 and the number of vacancies 113 in the chip array is 126.
  • the number of chips 111 in the chip array is 120, and the number of vacancies 113 is 6.
  • the maximum value Y of the number of row chips divides the chip array into at least two parts, and the total number of chips 111 in each part is not completely equal.
  • the maximum value 6 of the number of row chips divides the chip array into two equal parts, the two parts being the first part (for example, the left three columns of chips 111 in FIG. 1B ) and the second part (for example, the right three columns of chips 111 in FIG. 1B ), and the number of power extraction units 114 in the first part and the second part are not equal.
  • the first part includes 63 chips 111 arranged in 21 rows and 3 columns, and the 3 chips 111 in each row of the first part are connected in parallel to form 1 power extraction unit 114, so the first part includes 21 power extraction units 114.
  • the second part includes 57 chips 111 arranged in 19 rows and 3 columns, and the 3 chips 111 in each row of the second part are connected in parallel to form 1 power extraction unit 114, so the second part includes 19 power extraction units 114.
  • the maximum value Y of the row chip 111 can also divide the chip array into more than two parts. The present application does not limit the number of parts.
  • the value Y with the largest number of row chips divides the chip array into at least two parts, and along the heat dissipation direction, the total number of chips 111 in each part decreases.
  • the circuit board 110 can be applied to an electronic device 3100 such as a computing device.
  • a heat dissipation duct is defined in the electronic device 3100, and the circuit board 110 can work in the heat dissipation duct.
  • the heat dissipation direction of the circuit board 110 is the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the heat dissipation source of the circuit board 110 can be an air-cooled heat source (such as a fan) or a liquid-cooled heat source.
  • the heat dissipation direction is from left to right.
  • the total number of chips 111 in the first part is 63
  • the total number of chips 111 in the second part is 57, that is, the total number of chips 111 in each part is reduced.
  • the present application is not limited to this.
  • the total number of chips 111 in adjacent parts is not limited to decreasing one by one.
  • the total number of chips 111 in several adjacent parts is allowed to increase along the heat dissipation direction, as long as the total number of chips 111 in the parts is decreasing along the left-right direction as a whole.
  • the number of parts is 6 for illustration.
  • the total number of chips 111 in multiple parts can be 25, 24, 23, 22, 21, 20 respectively; or, the total number of chips 111 in multiple parts can be 22, 22, 21, 21, 20, 20 respectively; or, the number of power taking units 114 in multiple parts can be 21, 20, 20, 20, 20 respectively; or, the number of power taking units 114 in multiple parts can be 26, 25, 23, 24, 22, 20 respectively.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the back half near the air outlet, which can reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the maximum value Y of the number of row chips divides the chip array into at least two parts, the number of rows or columns of each part is not completely equal and/or the layout of each part chip 111 is asymmetric.
  • the maximum value Y of the number of row chips is 6, and the maximum value Y of the number of row chips divides the chip array into a first part and a second part.
  • the first part includes 63 chips 111 arranged in 21 rows and 3 columns
  • the second part includes 57 chips 111 arranged in 19 rows and 3 columns.
  • the number of rows in the first part and the second part is not equal, and the layout of each part chip 111 is asymmetric.
  • the value Y with the largest number of row chips divides the chip array into two equal parts, and along the heat dissipation direction, the average column spacing of the first half is smaller than the average column spacing of the second half.
  • the above “equal division” refers to the number of columns of chips 111 being equally divided; the circuit board 110 is not necessarily equally divided in size.
  • Y is an even number
  • Y is an even number 6
  • the number of columns of the chip 111 in the first half and the second half can be (Y-1)/2, respectively.
  • the number of columns of the chip 111 in the first half and the second half is 3, respectively.
  • the ambient temperature is relatively low
  • the back half of the heat dissipation direction is arranged close to the air outlet
  • the ambient temperature is relatively high.
  • the value Y with the largest number of row chips divides the chip array into two equal parts.
  • the number of rows of chips 111 and/or the number of chips 111 and/or the number of vacancies 113 in the first half and the second half are not equal.
  • the first half is the first part
  • the second half is the second part.
  • the first part includes 63 chips 111 arranged in 21 rows and 3 columns, and the number of vacancies 113 in the first part is zero.
  • the second part includes 57 chips 111 arranged in 19 rows and 3 columns, and the number of vacancies 113 in the first part is 6. Therefore, The number of rows of chips 111 in the first half and the number of chips 111 in the second half are different, and the number of vacant positions 113 are not equal.
  • the value Y with the largest number of row chips divides the chip array into two equal parts, and along the heat dissipation direction, the number of rows of chips 111 and/or the number of chips 111 in the first half is greater than that in the second half.
  • the first part includes 63 chips 111 arranged in 21 rows and 3 columns
  • the second part includes 57 chips 111 arranged in 19 rows and 3 columns. Therefore, the number of rows of chips 111 in the first half is greater than that in the second half, and the number of chips 111 in the first half is greater than that in the second half. In this way, the total heat generated by the chips 111 arranged near the air outlet can be further reduced, thereby reducing the temperature difference between the chips 111 in the first half and the chips 111 in the second half.
  • the value Y with the largest number of chips in a row divides the chip array into two equal parts, and along the heat dissipation direction, the first half is equal to the number of chips 111 rows and/or the number of chips 111 in the second half.
  • the first part includes 57 chips 111 arranged in 19 rows and 3 columns
  • the second part includes 57 chips 111 arranged in 19 rows and 3 columns. Therefore, the number of chips 111 rows in the first half is equal to that in the second half, and the number of chips 111 in the first half is equal to that in the second half.
  • the value Y with the largest number of chips in a row divides the chip array into two equal parts, and along the heat dissipation direction, the number of vacancies 113 in the first half is less than or equal to the number of vacancies 113 in the second half.
  • the first part includes 60 chips 111 and 3 vacancies 113
  • the second part includes 54 chips 111 and 9 vacancies 113. Therefore, the number of vacancies 113 in the first half is less than that in the second half.
  • the value Y with the largest number of row chips divides the chip array into two equal parts, and along the heat dissipation direction, at least some of the row vacancies 113 of the first half and the second half are on the same straight line.
  • the 11th row in the first part includes 3 vacancies 113.
  • the 6th row, the 11th row, and the 17th row in the second part each include 3 vacancies 113.
  • the vacancies 113 in the first part are on the same straight line with the vacancies 113 in the 11th row in the second part.
  • the 8th row and the 14th row in the first part each include 3 vacancies 113.
  • the 8th row and the 14th row in the second part each include 3 vacancies 113.
  • the vacancies 113 in the 8th row in the first part are on the same straight line with the vacancies 113 in the 8th row in the second part
  • the vacancies 113 in the 14th row in the first part are on the same straight line with the vacancies 113 in the 14th row in the second part.
  • the value Y with the largest number of row chips divides the chip array into two equal parts, and along the heat dissipation direction, the vacant positions 113 of at least some rows in the first half and the second half are not on the same straight line.
  • the 11th row in the first part includes 3 vacant positions 113.
  • the 6th row, the 11th row, and the 17th row in the second part each include 3 vacant positions 113.
  • the vacant positions 113 in the first part are on the same straight line with the 11th row in the second part, and the vacant positions 113 in the first part are not on the same straight line with the 6th row and the 17th row in the second part.
  • the 11th row in the first part includes 3 vacant positions 113.
  • the 8th row in the second part and the 14th row respectively include 3 vacancies 113.
  • the vacancies 113 in the first part and the vacancies 113 in the second part are not on the same straight line.
  • the vacant positions 113 are located at the upper edge and/or the lower edge of the chip array.
  • the value Y with the largest number of row chips divides the chip array into two equal parts, and along the heat dissipation direction, the vacant position 113 is located at the upper edge and/or lower edge of the front half.
  • the “upper edge of the front half” refers to the upper edge of the front half perpendicular to the heat dissipation direction; the “lower edge of the front half” refers to the lower edge of the front half perpendicular to the heat dissipation direction.
  • the front half includes a row of vacant positions 113, and the row of vacant positions 113 is located at the upper edge of the front half.
  • the front half includes two rows of vacant positions 113, and the two rows of vacant positions 113 are located at the upper edge and the lower edge of the front half, respectively.
  • the vacant positions 113 can form an air duct, which can utilize the heat dissipation of the chip 111 and further improve the heat dissipation effect.
  • the circuit board 110 area occupied by the chip array is divided into three areas: two ends and the middle.
  • the 1st to 7th power taking units 114 in the second part can be divided into the first sub-area, which includes 21 chips 111 arranged in 7 rows and 3 columns;
  • the 8th to 12th power taking units 114 are divided into the second sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns;
  • the 13th to 19th power taking units 114 are divided into the third sub-area, which also includes 21 chips 111 arranged in 7 rows and 3 columns.
  • the number of power taking units 114 in the end area is 7, and the number of power taking units 114 in the middle area is 5.
  • the total number of chips 111 corresponding to the two end regions is greater than or equal to the total number of chips 111 in the middle region.
  • the 1st to 7th power taking units 114 in the second part are divided into the first sub-region, which includes 21 chips 111 arranged in 7 rows and 3 columns; the 8th to 12th power taking units 114 are divided into the second sub-region, which includes 15 chips 111 arranged in 5 rows and 3 columns; the 13th to 19th power taking units 114 are divided into the third sub-region, which also includes 21 chips 111 arranged in 7 rows and 3 columns.
  • the first sub-region and the second sub-region are the two end regions, and the second sub-region is the middle region. Therefore, the total number of chips 111 corresponding to the two end regions is greater than the total number of chips 111 in the middle region.
  • the chips 111 in the two end areas are closer to the external environment and the heat dissipation is better.
  • the temperature of the chips 111 in the middle area can be effectively reduced, thereby reducing the temperature difference between the chips 111 in the middle area and the chips 111 in the end areas, improving the heat dissipation effect of the circuit board 110, and ensuring the overall performance of the circuit board 110.
  • the average row spacing of the chips 111 in the two end regions is smaller than the average row spacing of the chips 111 in the middle region.
  • the chips 111 in the two end regions are closer to the external environment, and the heat dissipation is better.
  • the temperature of the chips 111 in the middle region can also be effectively reduced, thereby reducing the temperature difference between the chips 111 in the middle region and the chips 111 in the end regions, improving the heat dissipation effect of the circuit board 110, and ensuring the overall performance of the circuit board 110.
  • the circuit board 110 area occupied by the chip array is divided into two ends and three middle areas, including: the maximum value of the number of chips in the chip array column is X, and the circuit board 110 area occupied by the chip array is divided into three ends and three middle areas based on X.
  • X i.e., 21
  • the division method is average division
  • the circuit board 110 is divided into three parts from top to bottom, and the 7 chips 111 in a column are correspondingly divided into a part, then the total number of chips 111 in the first part is 42, the total number of chips 111 in the second part is 36, and the total number of chips 111 in the third part is 42.
  • the total number of chips 111 (42) in the first part (42) or the third part near the two ends of the circuit board 110 is greater than the number of chips 111 (36) in the middle second part; or, in combination with FIG. 1B, the division method is to make the number of chips 111 in the two end areas greater than the number of chips 111 in the middle area.
  • the circuit board 110 can be divided into three parts from top to bottom, and 8 chips 111 from top to bottom in a column are one part, 5 chips 111 are one part, and 8 chips 111 are one part. Then the total number of chips 111 in the first part is 48, the total number of chips 111 in the second part is 24, and the total number of chips 111 in the third part is 18.
  • the circuit board 110 area occupied by the chip array is divided into two end areas and a middle area, including: the height of the circuit board 110 area occupied by the chip array in the vertical heat dissipation direction is H; based on H, the circuit board 110 area occupied by the chip array is divided into two end areas and a middle area.
  • the division method is average division, the heights of the two end areas and one middle area are both H/3.
  • circuit board 110 area occupied by the chip array can be divided into multiple areas, which can be divided according to actual conditions and are not limited to the three areas mentioned above.
  • the division method is not limited to the above description.
  • the division method can be flexibly selected.
  • the overall area formed by the edges of the chips 111 arranged on the circuit board 110 can also be used as a reference to divide and divide it. It can be divided evenly, and of course it can be divided according to other proportions so that the total number of chips 111 in each part meets the preset distribution requirements.
  • the arrangement of the chips 111 can be set in combination with the heat dissipation conditions at various locations in the air duct. For example, if the ambient temperature at the air inlet is low and the overall heat dissipation efficiency is high, more chips 111 can be arranged; if the ambient temperature at the air outlet is high and the overall heat dissipation efficiency is low, fewer chips 111 can be arranged, and the total number of chips 111 near the air outlet is less than the total number of chips 111 at the air inlet.
  • the upper and lower ends of the circuit board 110 are perpendicular to the direction of the wind.
  • the temperature of the circuit board 110 is lower than the temperature of the center of the circuit board 110, more chips 111 can be arranged at the two ends, and fewer chips 111 can be arranged at the center, so that the total number of chips 111 at the two ends is greater than the total number of chips 111 in the center.
  • the total number of chips 111 in the lower part is greater than the total number of chips 111 in the upper part. This is a completely different design idea from the usual change of the thermal resistance of the heat sink 2110 to achieve temperature uniformity.
  • the two end regions include a first end region and a second end region, the number of chips 111 in the first end region is less than the number of chips 111 in the second end region, wherein, when the circuit board 110 is placed vertically, the first end region is close to the top of the circuit board 110, and the second end region is close to the bottom of the circuit board 110.
  • the end region disposed close to the top can better exchange heat with the external environment, the total heat generated by the chips 111 in the second end region can be reduced through the above arrangement, thereby effectively reducing the temperature of the chips 111 in the second end region, thereby reducing the temperature difference between the chips 111 in the first end region and the chips 111 in the second end region, and improving the heat dissipation effect of the circuit board 110.
  • the circuit board 110 area occupied by the chip array is divided into three areas at both ends and in the middle.
  • the 1st to 7th power taking units 114 in the second part can be divided into the first sub-area, which includes 21 chips 111 arranged in 7 rows and 3 columns;
  • the 8th to 12th power taking units 114 are divided into the second sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns;
  • the 13th to 19th power taking units 114 are divided into the third sub-area, which also includes 21 chips 111 arranged in 7 rows and 3 columns.
  • the number of power taking units 114 in the end area is 7, and the number of power taking units 114 in the middle area is 5.
  • the number of rows or columns of the corresponding chips 111 in each region is the same.
  • the row direction of the chips 111 is the heat dissipation direction
  • the number of columns of the chips 111 in each part is the same;
  • the column direction of the chips 111 is the heat dissipation direction
  • the number of rows of the chips 111 in each part is the same.
  • the row direction of the chips 111 is the heat dissipation direction
  • the number of columns of the first part and the second part are both 3. Similar situations also exist in FIG. 1B and FIG. 3 to FIG. 17 .
  • the number of power taking units 114 corresponding to at least two regions is not equal.
  • the 1st to 7th power taking units 114 in the second part are divided into the first sub-region, which includes 21 chips 111 arranged in 7 rows and 3 columns;
  • the 8th to 12th power taking units 114 are divided into the second sub-region, which includes 15 chips 111 arranged in 5 rows and 3 columns;
  • the 13th to 19th power taking units 114 are divided into the third sub-region, which also includes 21 chips 111 arranged in 7 rows and 3 columns.
  • the number of power taking units 114 in the end region is 7, and the number of power taking units 114 in the middle region is 5.
  • the number of power taking units 114 in each region increases from the middle to the two end regions.
  • the number of power taking units 114 in the end regions is 7, and the number of power taking units 114 in the middle region is 5. Therefore, when the circuit board 110 is applied to the electronic device 3100, the chips 111 in the two end regions are closer to the external environment, and the heat dissipation is better.
  • the temperature of the chips 111 in the middle region can be effectively reduced, thereby reducing the temperature difference between the chips 111 in the middle region and the chips 111 in the end regions, improving the heat dissipation effect of the circuit board 110, and ensuring the overall performance of the circuit board 110.
  • each vacant position 113 corresponds to a welding pad 117.
  • a conductive metal piece may be disposed corresponding to the vacant position 113, and the welding pad 117 is used to weld the conductive metal piece.
  • the conductive metal piece may be a copper sheet or an aluminum sheet, which is welded on the welding pad 117 to dissipate heat for the two adjacent working chips 111 connected thereto and reduce the voltage drop between the two adjacent working chips 111 connected thereto.
  • the working stability and reliability of the working chip 111 are improved.
  • the thickness of the conductive metal piece is less than or equal to the thickness of the chip 111.
  • the thickness direction of the conductive metal piece and the thickness direction of the chip 111 are perpendicular to the direction of the circuit board 110.
  • a plurality of continuous vacancies 113 cannot share the same conductive metal piece.
  • each vacancies 113 may correspond to a metal piece.
  • the length of the metal piece between the two chips 111 adjacent to the front and rear of the vacant position 113 is longer than the length of the metal piece set between the adjacent chips 111 without the vacant position 113, wherein the long direction is perpendicular to the parallel direction.
  • the adjacent chips 111 without the vacant position 113 may be in the same row or column, and the adjacent chips 111 without the vacant position 113 are non-edge chips 111 in the chip array in the parallel direction of the chips 111 perpendicular to the chip array.
  • the length direction is the up and down direction, and the adjacent chips 111 without the vacant position 113 are in the same column.
  • the spacing between the 7th power taking unit 114 and the 8th power taking unit 114 on the right side and the spacing between the 12th power taking unit 114 and the 13th power taking unit 114 can be greater than the spacing between other adjacent power taking units 114, so in the up and down direction, the length of the metal piece between the 7th power taking unit 114 and the 8th power taking unit 114 on the right side and the length of the metal piece between the 12th power taking unit 114 and the 13th power taking unit 114 are longer than the length of the metal piece between other adjacent power taking units 114.
  • Similar situations also exist in the circuit board 110 of Figures 1B, 3 to 17, and 19A to 21B.
  • the length of the signal line 116 between two chips 111 adjacent to the vacant position 113 is longer than the length of the signal line 116 between adjacent chips 111 without a vacant position 113, wherein the long direction is perpendicular to the parallel direction; and or the length of the power line 115 between two chips 111 adjacent to the vacant position 113 is longer than the length of the power line 115 between two chips 111 without a vacant position 113.
  • the length of the power line 115 between adjacent chips 111 with a missing position 113 wherein the long direction is perpendicular to the parallel direction.
  • adjacent chips 111 not separated by vacancies 113 may be in the same row or column.
  • Adjacent chips 111 not separated by vacancies 113 are non-edge chips 111 in the chip array in the parallel direction of the chips 111 perpendicular to the chip array.
  • Figure 2A is a schematic diagram of the structure of the circuit board 110;
  • Figure 2B shows a current diagram of the circuit board 110 shown in Figure 2A;
  • Figure 2C shows a signal diagram of the circuit board 110 shown in Figure 2A.
  • the parallel connection direction of the chips 111 is the left-right direction, and the parallel connection direction of the chips 111 of the vertical chip array is the up-down direction.
  • the distance between the 7th power unit 114 and the 8th power unit 114 on the right side and the distance between the 12th power unit 114 and the 13th power unit 114 can be greater than the distance between other adjacent power units 114, so in the up and down directions, the length of the power line 115 between the 7th power unit 114 and the 8th power unit 114 on the right side and the length of the power line 115 between the 12th power unit 114 and the 13th power unit 114 are longer than the length of the power line 115 between other adjacent power units 114, and the length of the signal line 116 between the 7th power unit 114 and the 8th power unit 114 on the right side and the length of the signal line 116 between the 12th power unit 114 and the 13th power unit 114 are longer than the length of the signal line 116 between other adjacent power units 114.
  • a similar situation also exists in the circuit board 110 of FIGS. 1B , 3 to 17 , and 19A to 21B
  • the operating temperature difference between the chips 111 of the chip array is in the range of 0 to 10° C. (including the endpoint value).
  • the temperature difference between the chips 111 can be 8 to 10° C. (including the endpoint value). In this way, the operating temperature difference between the chips 111 is small, thereby improving the working performance of the circuit board 110.
  • the spacings between adjacent vacant positions 113 along the heat dissipation direction are not equal.
  • the spacings between adjacent columns in the chip array may not be equal.
  • the spacing between adjacent vacant positions 113 can be increased along the heat dissipation direction.
  • the spacing between adjacent columns in the chip array can be gradually increased, so that the chips 111 arranged near the air outlet are relatively sparse, thereby reducing the operating temperature of the chips 111 arranged near the air outlet and reducing the temperature difference of the chips 111 at the air inlet and the air outlet.
  • the vacant position 113 is a non-edge chip 111 in the chip array.
  • the spacing between adjacent chips 111 in other non-vacant positions 113 other than the chips 111 adjacent to the front and rear of the vacant position 113 is equal.
  • the 10th and 11th rows on the right are vacant positions 113. Among them, the spacing between adjacent chips 111 in rows 1 to 9 on the right is equal, and the spacing between adjacent chips 111 in rows 12 to 21 is equal.
  • the distance between the adjacent chips 111 in front and behind the vacant position 113 after the chip 111 is filled is greater than or equal to the distance between the adjacent chips 111 in other non-vacant positions 113.
  • the distance between the chip 111 in the vacant position 113 and the adjacent chip 111 is greater than or equal to the distance between the remaining adjacent chips 111.
  • the chips 111 in the chip array are arranged in rows and columns, and the centers of the chips 111 in each row or column are on the same straight line.
  • the 120 chips 111 in the chip array are arranged in 21 rows and 6 columns, and the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the row spacing of the chips 111 in the first 3 columns is the same, and the 10th and 11th rows of the chips 111 in the last 3 columns are missing.
  • the number of chips 111 in the first 3 columns is 63, and the number of chips 111 in the last 3 columns is 57.
  • the row direction of the chip array can be the heat dissipation direction, and the column direction of the chip array is perpendicular to the heat dissipation direction of the chips 111.
  • the total number of the chips 111 in the front half near the air inlet is greater than the total number of the chips 111 in the back half near the air outlet.
  • the number of chips 111 at the air inlet is larger, which can increase the heat generation of the chips 111 at the air inlet.
  • the number of chips 111 at the air outlet is smaller, which can reduce the heat generation of the chips 111 at the air outlet, thereby further reducing the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111. Similar situations also exist in the circuit board 110 of Figures 2A to 21B.
  • the chips 111 in the chip array are arranged in rows and columns, and the center of each vacant position 113 is in the same straight line as the row or column.
  • each vacant position 113 can be set at the intersection of the rows and columns of the chip array, that is, the center of the vacant position 113 is in a straight line with the center of other chips 111 in the corresponding row chip 111, and the center of the vacant position 113 is in a straight line with the center of other chips 111 in the corresponding column chip 111.
  • the number of vacant positions 113 increases in the area on the circuit board 110 that is far from the heat dissipation source.
  • the heat dissipation source is a fan
  • the fan is disposed at the air inlet of the heat dissipation air duct
  • the area on the circuit board 110 that is far from the heat dissipation source is the area on the circuit board 110 that is near the air outlet.
  • the total number of chips 111 in the front half near the air inlet can be made greater than the total number of chips 111 in the rear half near the air outlet, and the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet can be reduced, thereby improving the temperature uniformity of the chips 111.
  • the number of vacant positions 113 is increased in areas prone to high temperatures.
  • the heat source is a fan
  • the fan is disposed at the air inlet of the heat dissipation duct
  • the area on the circuit board 110 away from the heat source is the area on the circuit board 110 near the air outlet.
  • the ambient temperature is proportional to the number of vacant positions 113.
  • the environmental text includes air temperature, chip 111 temperature, temperature of other electronic components and temperature of the circuit board 110.
  • the number of vacant positions 113 is negatively correlated with the density of chips 111 in the area where the vacant positions 113 are located, that is, the more vacant positions 113, the smaller the density of chips 111, and the fewer vacant positions 113, the greater the density of chips 111. With such a setting, it can be ensured that the density of chips 111 is small when the ambient temperature is high, which is beneficial to the heat dissipation of chips 111 and reduces the maximum temperature difference of chips 111 in the chip array.
  • the value Y with the largest number of row chips divides the chip array into at least two parts.
  • the total number of chips A in the first Y/2 columns of the chip array is greater than the total number of chips B in the last Y/2 columns of the chip array.
  • Y is an even number 6
  • the total number of chips in the first 3 columns of the chip array is 63
  • the total number of chips in the last 3 columns of the chip array is 57.
  • the total number of chips C in the front (Y-1)/2 columns of the chip array is greater than the total number of chips D in the rear (Y-1)/2 columns of the chip array.
  • Y is 7.
  • the total number of chips C in the first 3 columns of the chip array is greater than the total number of chips D in the rear 3 columns of the chip array.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the rear half near the air outlet, which can reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the total number of chips A in the first Y/2 columns of the chip array and the corresponding columns may be smaller than the total number of chips B in the last Y/2 columns of the chip array and the corresponding columns.
  • Y is an even number 6
  • the total number of chips in the first 3 columns of the chip array is 57
  • the total number of chips in the last 3 columns of the chip array is 63.
  • the total number of chips C in the first (Y-1)/2 columns of the chip array and the corresponding columns can also be less than the total number of chips D in the last (Y-1)/2 columns of the chip array and the corresponding columns.
  • the total number of chips C in the first 3 columns of the chip array can be less than the total number of chips D in the last 3 columns of the chip array.
  • the present application is not limited thereto, and if Y is an even number, the total number of chips A in the first Y/2 columns and the corresponding columns of the chip array may also be equal to the total number of chips B in the last Y/2 columns and the corresponding columns of the chip array.
  • Y is an even number 6
  • the total number of chips in the first 3 columns of the chip array is 57
  • the total number of chips in the last 3 columns of the chip array is 57.
  • the total number of chips C in the first (Y-1)/2 columns and the corresponding columns of the chip array is equal to the total number of chips D in the last (Y-1)/2 columns and the corresponding columns of the chip array.
  • Y take Y as 7 as an example.
  • the total number of chips C in the first 3 columns of the chip array can be equal to the total number of chips D in the last 3 columns of the chip array.
  • the present application also provides a working assembly 2100, including a circuit board 110 and a heat sink 2110.
  • the circuit board 110 is the circuit board 110 in any of the above embodiments
  • the heat sink 2110 includes a heat sink body and heat sink fins
  • the heat sink body includes a first surface and a second surface opposite to each other, and the first surface is connected to the heat sink fins.
  • the heat sink 2110 may be an air-cooled heat sink 2110 or a liquid-cooled heat sink 2110.
  • the heat sink 2110 may be located on the side of the circuit board 110 where the working chip 111 is provided, for dissipating heat for the circuit board 110.
  • the heat sink 2110 may also be located on the side of the circuit board 110 where the chip 111 is not provided.
  • the chip 111 is provided on both sides of the circuit board 110, and the heat sink 2110 is provided on both sides of the circuit board 110, respectively.
  • the second surface is provided with a plurality of bosses, each boss being provided corresponding to each row or column of the power taking unit 114. In this way, the heat generated by the chip 111 in the power taking unit 114 during operation can be effectively transferred to the heat sink 2110 through the bosses, thereby improving the heat dissipation effect.
  • a plurality of bosses are provided on the second surface, and at least some of the bosses can also be provided at corresponding positions between at least some adjacent power taking units 114.
  • 117 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the number of chips 111 in the 6th row, the 11th row and the 16th row is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 6th row, the 11th row and the 16th row is less than the number of chips 111 in other rows.
  • the bosses can be provided at corresponding positions of the 5th power taking unit 114 and the 6th power taking unit 114, corresponding positions of the 9th power taking unit 114 and the 10th power taking unit 114, and corresponding positions of the 13th power taking unit 114 and the 14th power taking unit 114 in the second part.
  • a plurality of chips 111 near the air outlet are divided into a plurality of heat generating component groups along the second direction, and a gap between two adjacent heat generating component groups is larger than a gap between two adjacent chips 111 in each heat generating component group.
  • the six columns of chips 111 are shown in the example of FIG2A.
  • the six columns of chips 111 arranged in sequence along the first direction are respectively referred to as the first heating column, the second heating column...the sixth heating column.
  • the number of chips 111 in the first to third heating columns is 21, and the number of chips 111 in the fourth to sixth heating columns is 19. Among them, the 21 chips 111 in the first to third heating columns are evenly spaced.
  • the 19 chips 111 in the fourth to sixth heating columns are divided into three groups of heating component groups, and the number of chips 111 in the heating component groups at the two ends of the second direction in the three groups of heating component groups is the same, and the number of chips 111 in the heating component group located in the middle of the second direction is less than the number of chips 111 in the heating component groups at the two ends.
  • the arrangement of the chip 111 can be in various forms. From the first column near the air inlet (such as the first heating column mentioned above) to the last column near the air outlet (such as the sixth heating column mentioned above), the number of chips in each column is not completely equal.
  • the number of chips in each column can be gradually decreased, for example, 21, 20, 19, 18, 17, 16; it can be partially decreased, for example, 21, 21, 21, 19, 19, 19; it can also be a jump in number, for example, 21, 21, 20, 19, 20, 21; or 21, 21, 20, 19, 18, 21; other numbers of chip arrays can also be set according to heat dissipation requirements, so that the total number of chips in the front half near the air inlet is greater than the total number of chips in the back half near the air outlet.
  • the front half and the back half here can be divided in half in terms of the number of chip columns, or in half in terms of the size of the circuit board 110. As shown in FIG. 2A , the total number of chips in the first three rows near the air inlet is set to be greater than the total number of chips in the last three rows near the air outlet.
  • the arrangement of each row of chips can also be combined in different forms, and the number of chips in each row can be different.
  • some rows of chips are arranged in a straight line with the center points of the chips, and the center points of some rows of chips do not form a straight line, such as a step arrangement (such as in accordance with the above-mentioned "the number of chips in each column gradually decreases, for example, 21, 20, 19, 18, 17, 16" and the row direction presents a step arrangement).
  • the number of chips in each row For example, in the second direction, the number of row chips near the two ends of the circuit board 110 is greater than the number of row chips near the center of the circuit board 110. In short, the total chip distribution and/or quantity is divided, and the total number of chips in each part of the division meets the preset distribution requirements.
  • the number of chips in the first heating column is used as the basis for division, and the circuit board 110 is divided from left to right into three parts, namely, the first part, the second part, and the third part.
  • the total number of chips in the first part or the third part close to both ends of the circuit board 110 is greater than the number of chips in the middle second part.
  • the number of chips in the first heating column is used as the basis for division in the second direction, and the circuit board 110 is divided from left to right into two parts, the number of chips in the first part is less than or equal to the number of chips in the second part.
  • the division method is average division.
  • the circuit board 110 is divided into three parts from left to right. There are 21 chips in the first heating column.
  • the circuit board 110 is divided into three parts from left to right. Each of the 7 chips in the first heating column is divided into a part.
  • the total number of chips in the first part is 42, the total number of chips in the second part is 36, and the total number of chips in the third part is 42.
  • the total number of chips in the first part (42) or the third part (42) near the two ends of the circuit board 110 is greater than the number of chips in the middle second part (36); if the circuit board 110 is divided into two parts from left to right based on the number of chips in the first heating column in the second direction, the central axis of the 11th chip in the middle of the first heating column can be used as the division point to divide the circuit board 110 from left to right into two parts, then the number of chips in the first part (57) is equal to the number of chips in the second part (57).
  • the division method is not limited to the above description. When the total number of chips in the first heating column is an odd number or an even number, The division method can be flexibly selected. Of course, the overall area formed by the edge of the circuit board where the chips are arranged can be used as a reference for division and partition. It can be divided evenly or according to other proportions so that the total number of chips in each part meets the preset distribution requirements.
  • the arrangement of the chips 111 can be set in combination with the heat dissipation conditions of various positions in the air duct. For example, if the ambient temperature of the air inlet is low and the overall heat dissipation efficiency is high, more chips can be arranged; if the ambient temperature of the air outlet is high and the overall heat dissipation efficiency is low, fewer chips can be arranged, and the total number of chips near the air outlet is less than the total number of chips at the air inlet.
  • the temperatures at both ends are lower than the temperature at the center of the circuit board 110, then more chips 111 can be arranged at both ends, and fewer chips 111 can be arranged at the center.
  • the total number of chips at both ends is greater than the total number of chips in the center, or after being divided into two parts, the total number of chips in the lower half is greater than the total number of chips in the upper half.
  • the present application also provides a circuit board 110, on which a plurality of chipsets 118 are disposed, each chipset 110 includes at least one row of chips and/or at least one column of chips, and the inter-group spacing between at least some adjacent chipsets is not equal to the spacing between adjacent chips in any chipset.
  • a plurality of chipsets 118 are arranged to form a chip array.
  • the spacing between at least some adjacent chipsets 118 is greater than or equal to the spacing required to accommodate a chip, that is, there are chip vacancies between some adjacent chipsets 118.
  • the three columns of chips on the left are a chipset group 118
  • the 1st to 9th rows of chips on the right are a chipset group 118
  • the 10th to 19th rows of chips on the right are a chipset group 118 .
  • Three chipsets 118 constitute a chip array, and there is a row of vacant chips between two chipsets 118 in the three columns of chips on the right.
  • the three columns of chips on the left are a chipset group 118
  • the 1st to 7th rows of the three columns of chips on the right are a chipset group 118
  • the 8th to 12th rows of the three columns of chips on the right are a chipset group 118
  • the 13th to 19th rows of the three columns of chips on the right are a chipset group 118.
  • Four chipsets 118 constitute a chip array, and there are two rows of vacant chips between the three chipsets 118 in the three columns of chips on the right.
  • the 1st to 10th rows of the three columns of chips on the left side form a chipset group 118
  • the 11th to 20th rows of the three columns of chips on the left side form a chipset group 118
  • the 1st to 7th rows of the three columns of chips on the right side form a chipset group 118
  • the 8th to 12th rows of the three columns of chips on the right side form a chipset group 118
  • the 13th to 19th rows of the three columns of chips on the right side form a chipset group 118.
  • Five chipsets 118 constitute a chip array, there is a row of vacant chips between the three chipsets 118 in the three columns of chips on the left side, and there are two rows of vacant chips between the three chipsets 118 in the three columns of chips on the right side.
  • the chipset 118 is composed of at least one power extraction unit 114, and the power extraction unit 114 includes at least one chip.
  • the chips in the power extraction unit 114 are in the same row or column and connected in parallel.
  • the chips of each chipset 118 are connected in parallel in the same direction. In the direction perpendicular to the direction of chip parallel connection, the spacing between at least some adjacent chipsets 118 is not equal to the spacing between adjacent power extraction units 114 in any chipset 118.
  • the chipset 118 includes a plurality of power extraction units 114, and the plurality of power extraction units 114 are connected in series. The chips of each chipset 118 are connected in series in the same direction.
  • the spacing between at least some adjacent chipsets 118 is not equal to the spacing between adjacent power extraction units 114 in any chipset 118.
  • the chips between the chipsets 118 can be arranged with equal spacing or unequal spacing or with increasing spacing or decreasing spacing in the row and column directions, but the spacing between at least some adjacent chipsets 118 will be different from the spacing between adjacent chips in the chipset 118 due to the existence of chip vacancies.
  • the electrical connection mode of the chips in the above embodiments is not limited to series connection and parallel connection, and the chips can also be connected in series and in parallel in other electrical connection modes.
  • the chips on the circuit board 110 are divided into groups, and the inter-group spacing between each chipset 110 is set to be greater than the chip spacing within each chipset 118, forming a heat dissipation channel between each chipset, so that the chips arranged on the circuit board are more convenient for heat dissipation.
  • the chips on the circuit board 110 shown in FIG1B are densely arranged with equal spacing, which is not conducive to the heat dissipation of chips near the center area.
  • all chips are divided into multiple groups 118, and the inter-group spacing is set to be greater than the chip spacing within the group, so that the chips near the center area of the circuit board can achieve heat dissipation through a wider component spacing, thereby improving the temperature uniformity of all chips on the entire circuit board.
  • the spacing between the chipset corresponds to one or more continuous vacancies 113 in FIG1B.
  • the spacing between two adjacent chip groups 118 is greater than or equal to the spacing required to accommodate one chip 111 .
  • the distance between the chipsets 118 is set to be greater than or equal to the distance required to accommodate one chip 111, it is ensured that the distance between the chipsets 118 is large enough, thereby ensuring the heat dissipation of the chips close to the central area.
  • each chipset 118 includes multiple rows of chips, and at least two chipsets 118 have different numbers of rows of chips.
  • each chipset 118 includes at least one row of chips, and the number of rows of chips included in each chipset 118 is not unique.
  • the circuit board 110 is divided into chipsets including only one row of chips, chipsets including two rows of chips, chipsets including three rows of chips, etc., and each chipset forms a chip array.
  • each chipset 118 includes multiple rows of chips, and the number of rows of chips in each chipset 118 is the same.
  • the circuit board 110 includes three chipsets 118, wherein the three rows of chips located in the left half of the circuit board 110 are one chipset 118, and the three rows of chips located in the right half of the circuit board are divided into two chipsets. There are two chip groups 118, and a large gap is provided between the two chip groups 118, which can accommodate at least two rows of chips.
  • the left side of the circuit board 110 is located upstream in the cooling direction, and the right side is located downstream in the cooling direction.
  • the gap between the groups is ensured, thereby improving the cooling performance of the downstream chips in the cooling direction, and improving the temperature uniformity between the chips on the entire circuit board.
  • multiple chipsets 118 are connected in series for power supply, and each row of chips in each chipset 118 is connected in series for power supply.
  • the circuit board 110 includes four chipsets 118, including a first chipset (three columns of chips) located in the left half of the circuit board 110, and a second chipset, a third chipset, and a fourth chipset located in the right half of the circuit board from top to bottom.
  • the circuit board also includes a first electrical connector and a second electrical connector, one of which is used to connect to the positive pole of the power supply and the other is used to connect to the negative pole of the power supply.
  • the first chipset, the second chipset, the third chipset, and the fourth chipset are sequentially connected in series between the first electrical connector 119 and the second electrical connector 119' to realize series power supply.
  • each chipset 118 includes the same number of chip columns, thereby ensuring that when the chipsets 118 are connected in series, it is convenient to arrange the space area occupied by the multiple chipsets in series on the circuit board, which is beneficial to the versatility of the circuit board design and the reasonable planning of the routing on the circuit board (for example, the power line 115 and signal line between chips and between chipsets).
  • the chips in each row of chips in each chipset 118 are connected in parallel.
  • the chips in each chipset 118 are also connected in series, and each row of chips in each chipset 118 is connected in parallel.
  • the voltage of each chip in each row can be made consistent, thereby ensuring that each chip obtains the same operating voltage and improving operating stability.
  • the voltage drop of each row of chips in parallel in the series direction is basically consistent and stable, which is beneficial to stabilize the operating voltage between each row of chips within a predetermined range, thereby improving the stability of chip operation.
  • the column direction is perpendicular to the parallel connection direction of the chips
  • the row direction is parallel to the parallel connection direction of the chips.
  • the chips on the circuit board 110 are at least partially arranged in rows and columns, wherein the row direction is perpendicular to the parallel connection direction of the parallel chips on the circuit board 110.
  • each chipset 118 is composed of at least one power taking unit 114, wherein the chips in the power taking unit 114 are connected in parallel and arranged in rows. The chips in each row are connected in parallel to form a power extraction unit, and the power extraction units 114 formed by the chips in the rows are connected in series.
  • multiple chips included in the power supply unit 114 are connected in parallel to ensure that the voltage obtained by each chip in the power supply unit 114 is consistent, which is beneficial to improving the consistency of the working performance of each chip in the power supply unit 114 (for example, consistency in computing power or consistency in working frequency, etc.).
  • the plurality of chipsets 118 are divided into at least one chipset set.
  • the heat dissipation direction mentioned in the embodiment of the present application may be, for example, the direction of wind.
  • a cooling fan is used to dissipate heat from the circuit board 110, and the wind takes away the heat generated by the chips on the circuit board 110, thereby achieving heat dissipation.
  • the circuit board 110 includes two upper and lower chipsets 118, and the spacing between the two chipsets 118 is greater than the spacing between the chips in each chip group.
  • the upper and lower chipsets 118 on the circuit board 110 are divided into a chipset set.
  • a heat dissipation duct is formed between the two chipsets 118, the direction of the heat dissipation duct is parallel to the heat dissipation direction, and runs through the middle area of the chip matrix on the entire circuit board 110, so as to facilitate the heat dissipation of the chips 111 in the middle and rear areas of the circuit board 110.
  • the plurality of chipsets 118 are divided into a first chipset set and a second chipset set.
  • the circuit board 110 includes 5 chipsets 118, which are divided into two chipset sets.
  • the first chipset set includes two chipsets 118 distributed in the upper and lower parts, and the second chipset set includes three chipsets 118 in the upper, middle and lower parts.
  • the gaps i.e., heat dissipation ducts formed between the chipsets 118 in each chipset set are misaligned with each other, so that when the wind flows from the heat dissipation duct in the first chipset set to the second chipset set, it flows directly to the area where the chips are densely arranged, which is conducive to forming turbulence and increasing heat dissipation efficiency.
  • the heat dissipation duct in FIGS. 13-16 there is also a misalignment of the heat dissipation duct in FIGS. 13-16 , which will not be described in detail here.
  • the serial current directions of the chips in the chipset set are the same.
  • each chip in the entire row of chips is connected in parallel, each row of chips is connected in series, and the connection to the external power supply is achieved through two electrical connectors.
  • the direction of the arrow on the connecting line in the figure is the direction of the series current. Overall, the current direction flows from one electrical connector into the first row of chips, then flows into the last row of chips through each row of chips in sequence, and then flows out through another electrical connector.
  • the number of chips in the first chipset set and the number of chips in the second chipset set are equal.
  • the first chipset set and the second chipset set include three chipsets respectively, and the first chipset set includes two first gaps, the second chipset set includes two second gaps, and the number of chips included in the two chipset sets is equal, both 57.
  • the chips on the circuit board 110 are grouped to form component gaps to achieve heat dissipation.
  • the number of chips in the first chipset set and the second chipset set is consistent, which facilitates the layout of the chips on the circuit board 110 .
  • the number of chip columns of the first chipset set and the second chipset set is the same, and the number of chips of the first chipset set is equal to the number of chips of the second chipset set.
  • Each chipset set contains the same number of chip columns, thereby ensuring that when the chipsets in each set are connected in series, the space area occupied by the multiple chipsets 118 arranged in series on the circuit board 110 is convenient, which is beneficial to the versatility of the design of the circuit board 110 and the reasonable planning of the routing on the circuit board 110 (for example, the power line 115 and the signal line 116 between chips and between chipsets).
  • the first chipset set has a smaller number of chips than the second chipset set.
  • all chips on the circuit board 110 are divided into two parts, the left and the right, corresponding to the first chipset set and the second chipset set, respectively.
  • the number of chips in the first chipset set is less than that in the second chipset set.
  • the second chipset set can be in a region with a higher heat dissipation efficiency
  • the first chipset set can be in a region with a lower heat dissipation efficiency, so as to facilitate the temperature uniformity of the chips on the entire circuit board 110.
  • first chipset set and the second chipset set have the same number of chip columns, and the number of chips in the first chipset set is less than the number of chips in the second chipset set.
  • Each chipset set contains the same number of chip columns, thereby ensuring that when the chipsets 118 in each set are connected in series, it is convenient to arrange the multiple chipsets 118 in series to occupy the space area on the circuit board 110, which is beneficial to the versatility of the design of the circuit board 110 and the reasonable planning of the routing on the circuit board 110 (for example, the power lines 115 and signal lines 116 between chips and between chipsets).
  • the first chipset set has a greater number of chips than the second chipset set.
  • all chips on the circuit board 110 are divided into two parts, which correspond to the first chipset set and the second chipset set, respectively.
  • the number of chips in the first chipset set is greater than the number of chips in the second chipset set.
  • the number of chips 111 in the first chipset set is greater than the number of chips 111 in the second chipset set, so that the chip density of the first chipset set as a whole is greater than the chip density of the second chipset set as a whole.
  • the first chipset set can be located in a region with a higher heat dissipation efficiency
  • the second chipset set can be located in a region with a lower heat dissipation efficiency, so as to facilitate the temperature uniformity of the chips 111 on the entire circuit board 110.
  • the circuit board 110 in this embodiment can be configured such that the first chipset set is close to a heat source, for example, the heat source is a fan, the fan is configured such that the wind direction is parallel to the parallel direction of the chips 111 on the circuit board 110, and the first chipset set is close to the fan.
  • the heat source is a fan
  • the fan is configured such that the wind direction is parallel to the parallel direction of the chips 111 on the circuit board 110, and the first chipset set is close to the fan.
  • first chipset set and the second chipset set have the same number of chip columns, and the number of chips in the first chipset set is greater than the number of chips in the second chipset set.
  • Each chipset set contains the same number of chip columns, thereby ensuring that when the chipsets in each set are connected in series, the space area occupied by the multiple chipsets 118 arranged in series on the circuit board 110 is convenient, which is beneficial to the versatility of the design of the circuit board 110 and the reasonable planning of the routing on the circuit board 110 (for example, the power line 115 and the signal line 116 between chips and between chipsets).
  • an average chip pitch of the first chipset set is smaller than an average chip pitch of the second chipset set.
  • the circuit board 110 includes a first chipset set consisting of the first three columns of chips and a second chipset set consisting of the last three columns of chips, wherein the first chipset set includes only one chipset, and the second chipset set includes three chipsets along the column direction.
  • the average value of the column spacing between the three columns of chips in the first chipset set is smaller than the average column spacing between the three columns of chips in the second chipset set.
  • the first chipset set and the second chipset set are distributed along the heat dissipation direction.
  • the heat dissipation direction is the blowing direction of the fan
  • the first new chipset set is located upstream of the heat dissipation direction
  • the second chipset set is located downstream of the heat dissipation direction (where upstream and downstream are only relative to the position of the circuit board 110 in the fan, the end of the circuit board 110 closer to the fan is upstream, and the other end is downstream).
  • upstream and downstream are only relative to the position of the circuit board 110 in the fan, the end of the circuit board 110 closer to the fan is upstream, and the other end is downstream.
  • the temperature of the wind gradually increases.
  • the first chipset set includes one chipset in the parallel direction perpendicular to the chips 111 ; along the vertical direction, the chip spacings between adjacent chips in the chipset in the first chipset set are equal.
  • the first chipset set located on the left side of the circuit board 110 includes a chipset, and the spacing between the chips 111 in the group in the parallel direction perpendicular to the chips 111 is equal. Since the rows of chips 111 are connected in series in the parallel direction perpendicular to the chips 111 in each chipset 118, arranging the chips 111 at equal intervals is beneficial to the hardware design of the circuit board 110.
  • the connectors or wirings between the chips 111 can be of a uniform size or length, which simplifies the design on the one hand and reduces costs on the other.
  • the connectors can be copper sheets or pads attached between the chips 111. It should be noted that the above is only an example, and the present application is not limited to this.
  • the first chipset set includes multiple chipsets 118 in the parallel direction perpendicular to the chips 111 ; the group spacing between adjacent chipsets 118 in the first chipset set is greater than the chip spacing between adjacent chips in each chipset 118 .
  • the chips 111 on the circuit board 110 include a first chip set, and the set is configured as each
  • the inter-group spacing between the chipsets 118 is greater than the chip spacing within each chipset 118 , forming a heat dissipation channel between each group of chips, thereby making it easier for the chips 111 arranged on the circuit board 110 to dissipate heat.
  • the second chipset set includes one chipset in the parallel direction perpendicular to the chips; along the vertical direction, the chip spacings between adjacent chips 111 in the chipset of the second chipset set are equal.
  • the second chipset set located on the right side of the circuit board 110 includes a chipset 118, and the spacing between the chips in the group in the parallel direction perpendicular to the chips is equal. Since the rows of chips 111 are connected in series in the parallel direction perpendicular to the chips in each chipset 118, the hardware design of the circuit board 110 is facilitated by arranging the chips at equal intervals.
  • the connectors or wiring between the chips can be of a uniform size or length, which simplifies the design on the one hand and reduces costs on the other. Among them, the connectors can be copper sheets or pads attached between the chips. It should be noted that the above is only an example, and the present application is not limited to this.
  • the second chipset set includes multiple chipsets 118 in the parallel direction perpendicular to the chips 111 ; the group spacing between adjacent chipsets 118 in the second chipset set is greater than the chip spacing between adjacent chips in each chipset 118 .
  • the chips on the circuit board 110 include a second chipset set, and the inter-group spacing between the chipsets 118 in the set is set to be greater than the chip spacing within each chipset 118, forming a heat dissipation channel between the chips, thereby making it easier for the chips arranged on the circuit board 110 to dissipate heat.
  • a plurality of first gaps are formed between a plurality of pairs of adjacent chipsets in the first chipset set; a plurality of second gaps are formed between a plurality of pairs of adjacent chipsets in the second chipset set.
  • the gap between each chip group 118 is greater than or equal to the spacing required to accommodate one chip 111.
  • the chips on the circuit board 110 include a first chip group set and a second chip group set, and gaps are formed between each chip group 118 in the set, and heat dissipation channels are formed between each group of chips, so that the chips 111 arranged on the circuit board 110 are more convenient for heat dissipation.
  • a plurality of first gaps and a plurality of second gaps correspond one to one, and at least some of the first gaps and second gaps that correspond to each other are collinear.
  • at least some of the first gaps and second gaps that correspond to each other are collinear.
  • there is one first gap, three second gaps, and only one pair of the first gap and the second gap are collinear; in the embodiment shown in Figure 12, there are two first gaps and two second gaps, and the two pairs of the first gaps and the second gaps are collinear.
  • the circuit board 110 includes five chipsets 118, which are divided into two chipset sets, the first chipset set includes two chipsets distributed up and down, and the second chipset set includes three chipsets in the upper, middle and lower parts.
  • the gaps i.e., heat dissipation ducts formed between the chipsets 118 in each chipset set are offset from each other, so that when the wind flows from the heat dissipation duct in the first chipset set to the second chipset set, it flows directly to the area where the chips are densely arranged, which is conducive to forming turbulence and increasing heat dissipation efficiency.
  • heat dissipation duct misalignment in Figures 13-16, which will not be repeated here.
  • the number of the plurality of first gaps is less than the number of the plurality of second gaps.
  • the circuit board 110 includes a first chip set and a second chip set distributed left and right, each including three columns of chips, wherein the number of first gaps in the first chip set is less than the number of gaps in the second chip set.
  • the first chip set includes one first gap
  • the second chip set includes two second gaps.
  • a smaller number of first gaps are set in the first chipset set, and a larger number of second gaps are set in the second chipset set.
  • the overall arrangement of the chips is dense in the front and sparse in the back, which is convenient for the uniform temperature of the chips 111 in each area on the circuit board 110.
  • the number of chips in at least one column of the first chipset set is greater than the number of chips in at least one column of the second chipset set.
  • the circuit board 110 includes a first chipset set and a second chipset set distributed on the left and right, each including three columns of chips 111, wherein the number of chips in at least one column of the first chipset set is greater than the number of chips in at least one column of the second chipset set.
  • the first chipset set includes one chipset
  • the second chipset set includes five chipsets
  • the number of chips in any column of the first chipset set is greater than the number of chips in any column of the second chipset set.
  • the number of chips in all chip columns in the first chipset set is greater than the number of chips in all chip columns in the second chipset set.
  • the number of chips 111 included in the chip columns in the first chipset set is set to be less than the number of chips 111 included in the chip columns in the second chipset set, so that the number of chips in the first chipset set is greater than the number of chips in the second chipset set as a whole.
  • the first chipset set and the second chipset set are distributed along the heat dissipation direction, so the setting of the number of chips in the above embodiment can improve the temperature uniformity of the chips 111 on the circuit board 110 .
  • a distance from a first chip to a last chip in at least one column of chips in the first chipset set is smaller than a distance from a first chip to a last chip in at least one column of chips in the second chipset set.
  • the circuit board 110 includes a first chipset set and a second chipset set distributed on the left and right, each including three columns of chips, wherein the first chipset set includes only one chipset, and the first row of three chips is missing in the chipset (as shown in Figures 10 and 16), or the first and last rows of chips are missing in the chipset 118 (as shown in Figure 11), while the chips at the upper and lower ends are not missing in the second chipset set, so that the distance from the first chip to the last chip in the chip column in the first chipset set is smaller than the distance from the first chip to the last chip in at least one column of chips in the second chipset set.
  • the first chipset set and the second chipset set are distributed along the heat dissipation direction.
  • the area where the chip row is missing in the first chipset set forms a heat dissipation channel extending to the second chipset set.
  • wind can enter the second chipset set through the heat dissipation channel for heat dissipation, increasing the amount of air entering the second chipset set.
  • the wind entering the second chipset set through the heat dissipation channel absorbs less heat and the temperature is relatively low, which is convenient for heat dissipation and cooling of the second chipset set, and improves the temperature uniformity of the chips on the entire circuit board 110.
  • the number of chipsets in the first chipset set is less than the number of chipsets in the second chipset set.
  • the circuit board 110 includes a first chipset set and a second chipset set distributed on the left and right, and the number of chipsets in the first chipset set is less than the number of chipsets in the second chipset set. On the whole, the number of first gaps between chipsets formed in the first chipset set is less than the number of second gaps between chipsets formed in the second chipset set. More second gaps enable the chips 111 in the second chipset set to have higher heat dissipation efficiency.
  • the second chipset set in the parallel connection direction of the vertical chips, includes two end chipsets and one middle chipset, wherein the number of chips in each end chipset is greater than the number of chips in the middle chipset.
  • the circuit board 110 includes a first chipset set and a second chipset set distributed on the left and right, wherein each chipset 118 in the second chipset set includes chips in the same column, and the chipsets at both ends include 7 rows of chips 111 respectively, and the middle chipset includes 5 rows of chips 111, and the number of chips included in the chipsets at both ends is greater than the number of chips 111 included in the middle chipset.
  • the first chipset set and the second chipset set are distributed along the heat dissipation direction. Taking air cooling as an example, Wind first enters the first chipset set to absorb heat and then enters the second chipset set.
  • the circuit board 110 of this embodiment is vertically arranged in the housing of the electronic device, and the upper and lower ends of the housing of the electronic device are conducive to the heat dissipation of the chips 111 at the upper and lower ends of the circuit board 110, so the number of chips at the two ends can be relatively larger than that in the middle, so as to achieve temperature uniformity between the chips 111.
  • the two end chip groups include a first end chip group and a second end chip group, the number of chips in the first end chip group is less than the number of chips in the second end chip group, wherein, when the circuit board 110 is placed vertically, the first end chip group is against the top of the circuit board 110, and the second end chip group is close to the bottom of the circuit board 110.
  • the first chipset set and the second chipset set are distributed along the heat dissipation direction.
  • the wind first enters the first chipset set to absorb heat and then enters the second chipset set.
  • the wind temperature gradually increases. Since the higher the temperature, the more the wind tends to rise, the higher temperature wind rises to the first end chipset, and the lower temperature wind enters the second end chipset.
  • the average spacing between the chips 111 in each end chip group is smaller than the average spacing between the chips 111 in the middle chip group.
  • the first chipset set and the second chipset set are distributed along the heat dissipation direction. Taking air cooling as an example, the wind first enters the first chipset set to absorb heat and then enters the second chipset set.
  • the circuit board 110 of this embodiment is vertically configured in the housing of the electronic device, and the upper and lower ends of the housing of the electronic device are conducive to the heat dissipation of the chips at the upper and lower ends of the circuit board 110, so the chip spacing at the two ends can be smaller than that in the middle, so as to achieve temperature uniformity between the chips 111.
  • an average chip pitch in the first chipset set is smaller than an average chip pitch in the second chipset set.
  • the first chipset set and the second chipset set are distributed along the heat dissipation direction.
  • the wind first enters the first chipset set to absorb heat and then enters the second chipset set, and the wind temperature entering the second chipset set is higher.
  • the chip array in the second chipset set is more sparse, which facilitates the realization of temperature uniformity between the chips 111 on the entire circuit board 110.
  • the length of the electrical connection line between adjacent chip groups is greater than the length of the electrical connection line between adjacent chips in the chip group.
  • the electrical connection line includes a power line 115 and/or a signal line 116.
  • the circuit board 110 includes a first chip set and a second chip set distributed on the left and right.
  • the second chipset set includes three chipsets, namely, upper, middle and lower chipsets. It can be seen that the length of the power line 115 between the chipsets 118 is longer than the length of the power line 115 of the chips in each chipset 118. The same situation exists in FIG. 19B and FIG. 21B, which will not be described again.
  • the circuit board 110 includes a first chipset set and a second chipset set distributed on the left and right, wherein the second chipset set includes three chipsets, upper, middle and lower. It can be seen that the length of the signal line 116 between each chipset 118 is longer than the length of the signal line 116 of the chip components within each chipset 118.
  • metal pieces are disposed between adjacent chip groups in the parallel connection direction of the vertical chips. By disposing metal pieces between adjacent chip groups, the voltage drop between adjacent chip groups can be reduced.
  • metal pieces are disposed between adjacent chips in each chip group 118, and the length of the metal pieces between adjacent chip groups is greater than the length of the metal pieces between adjacent chips 111.
  • the present application further provides a working component 2100, which includes:
  • the circuit board 110 is as described in any of the above embodiments.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other.
  • the first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses, each boss being provided corresponding to each row of chips or each column of chips.
  • the second surface is provided with a plurality of bosses, and at least some of the bosses are provided at corresponding positions between at least some adjacent chip groups 118 or between at least some adjacent power taking units or at least some vacant positions.
  • the bosses are disposed at corresponding positions between at least some of the adjacent chip groups 118, that is, the bosses are disposed corresponding to the gaps between the chip groups 118, and a heat dissipation channel is formed between the bosses and the gaps.
  • the air volume passing through the heat dissipation channel can be increased, which is beneficial to the uniform temperature of the chips on the entire circuit board.
  • circuit board 110 according to multiple embodiments of the present application is described below in conjunction with Figures 1B to 21B.
  • Fig. 1B shows a schematic diagram of the structure of the circuit board 110 according to the first embodiment of the present application.
  • the heat dissipation direction is the direction from left to right in Fig. 1B
  • the parallel direction and the row direction are the left-right direction in Fig. 1B
  • the direction perpendicular to the parallel direction, the direction perpendicular to the heat dissipation direction, and the column direction are all the up-down direction in Fig. 1B.
  • a chip array is arranged on the circuit board 110, and the number of chips 111 in the chip array is greater than 20 or 50.
  • the number of chips 111 in the chip array in FIG1B is 120.
  • the chip array is arranged as X*Y, In the column direction of the chip array, the maximum number of column chips is X, and in the row direction of the chip array, the maximum number of row chips is Y. In the first embodiment, X is 21 and Y is 6.
  • the rectangular area of the circuit board 110 occupied by the chip array is divided into two distribution areas, that is, the value Y with the largest number of row chips divides the chip array into two distribution areas, the two distribution areas are the first distribution area (for example, the left three columns of chips 111 in FIG. 1B ) and the second distribution area (for example, the right three columns of chips 111 in FIG. 1B ), and the number of power extraction units 114 in the first distribution area and the second distribution area is not equal.
  • the first distribution area includes 63 chips 111 arranged in 21 rows and 3 columns, and the 3 chips 111 in each row of the first distribution area are connected in parallel to form 1 power extraction unit 114, so the first distribution area includes 21 power extraction units 114.
  • the second distribution area includes 57 chips 111 arranged in 19 rows and 3 columns, and the 3 chips 111 in each row of the second distribution area are connected in parallel to form 1 power extraction unit 114, so the second distribution area includes 19 power extraction units 114.
  • the maximum value Y of the row chip 111 can also divide the chip array into more than two distribution areas.
  • the present application does not limit the number of distribution areas.
  • the row direction of the chips 111 is the heat dissipation direction, and the number of columns of the first distribution area and the second distribution area is the same (three columns).
  • the present application is not limited thereto, and when the column direction of the chips 111 is the heat dissipation direction, the number of rows of the chips 111 in each distribution area can be the same.
  • the number of power taking units 114 in the two distribution areas decreases. As shown in FIG1B , the number of power taking units 114 in the first distribution area is 21, and the number of power taking units 114 in the second distribution area is 19. Of course, the present application is not limited to this.
  • the number of power taking units 114 in a distribution area is greater than 2, the number of power taking units 114 in adjacent distribution areas is not reduced one by one, and the number of power taking units 114 in several adjacent distribution areas is allowed to increase along the heat dissipation direction, as long as the overall spacing between adjacent distribution areas increases along the left and right directions.
  • the number of distribution areas is 6 for illustration.
  • the number of power taking units 114 in multiple distribution areas can be 15, 14, 13, 12, 11, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 12, 12, 11, 11, 10, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 11, 10, 10, 10, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 16, 15, 13, 14, 12, 10 respectively.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the back half near the air outlet, which can reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the distances between the 21 power taking units 114 in the first distribution area can be equal.
  • the spacing between the 9th power taking unit 114 and the 10th power taking unit 114 in the second distribution area can be greater than the spacing between other adjacent power taking units 114.
  • the above-mentioned "other adjacent power taking units 114" are non-edge power taking units 114 in the chip array.
  • the spacing between other adjacent power taking units 114 can be the spacing between the 1st to 9th power taking units set in the same column.
  • spacing between other adjacent power taking units 114 can be equal to the spacing between adjacent power taking units 114 in the first distribution area, and at this time, the average column spacing of the first distribution area is less than the average column spacing of the second distribution area.
  • the distance between adjacent power extraction units 114 increases, and/or the distance between adjacent chips 111 increases.
  • the distance between the first distribution area and the second distribution area may be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the heat dissipation direction, the distance between the first distribution area and the second distribution area may be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the heat dissipation direction, the distance between multiple columns of chips 111 may gradually increase or decrease.
  • the rectangular area of the circuit board 110 occupied by the chip array is divided into multiple sub-areas, and the number of power taking units 114 in at least two sub-areas is not equal.
  • the 1st to 9th power taking units 114 in the second distribution area can be divided into a sub-area, which includes 27 chips 111 arranged in 9 rows and 3 columns; the 10th to 19th power taking units 114 are divided into another sub-area, which includes 30 chips 111 arranged in 10 rows and 3 columns.
  • the 19 power taking units 114 in the second distribution area can be divided according to the spacing between adjacent power taking units 114, and the 19 power taking units 114 can be divided into two sub-areas.
  • the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between the two sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 at both ends of the series connection direction in each sub-area and the chip 111 at the center position is smaller, thereby effectively reducing the temperature of the chip 111 at the center position in each sub-area, and thereby reducing the temperature difference between multiple chips 111 in the sub-area.
  • the 120 chips 111 in the chip array are arranged in 21 rows and 6 columns, and the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the row spacing of the chips 111 in the first 3 columns is the same, and the 10th and 11th rows of the chips 111 in the last 3 columns are missing.
  • the number of chips 111 in the first 3 columns is 63, and the number of chips 111 in the last 3 columns is 57.
  • the row direction of the chip array can be the heat dissipation direction.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the back half near the air outlet.
  • the number of chips 111 at the air inlet is larger, which can increase the heat generation of the chips 111 at the air inlet.
  • the number of chips 111 at the air outlet is smaller, which can reduce the heat generation of the chips 111 at the air outlet, thereby further reducing the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the row spacing of the chips 111 in each distribution area can be the same, and the centers of the multiple chips 111 in each row can be on a straight line.
  • the centers of the three chips 111 in the first distribution area are in a straight line.
  • the gap between the two sub-areas corresponds to the chips 111 in the 10th and 11th rows in the first distribution area in the first direction.
  • metal parts can be arranged between adjacent power taking units 114, and along the up and down direction, the length of the metal parts between at least some adjacent power taking units 114 is longer than that of other adjacent power taking units 114. Therefore, the metal parts arranged in this way can reduce the resistance of the current channel, reduce the voltage drop of the current channel, and thus reduce the energy loss on the current channel.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 can include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be provided corresponding to each row power taking unit 114 or each column power taking unit 114.
  • 120 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the number of chips 111 in the 10th and 11th rows is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 10th and 11th rows is less than the number of chips 111 in other rows.
  • at least part of the boss can be set at the corresponding position between the 9th power extraction unit 114 and the 10th power extraction unit 114.
  • the temperature of the chip array after working for a period of time is as follows. It can be seen that the chip temperature fluctuates within the range of 65° C. to 75° C., and the temperature difference is about 10° C.
  • a chip vacancy 113 is set.
  • the temperature of the chip array after working for a period of time is shown as follows. It can be seen that the chip temperature fluctuates in the range of 70°C to 75°C, and the temperature difference is about 5°C. It should be noted that the preset power remains unchanged but the number of chips is reduced, so the average power of each chip increases, resulting in an increase in the heat generation of each chip 111.
  • the maximum temperature is still about 75°C, the heat dissipation of the chip is improved, and the temperature uniformity of the chip is further improved. This shows that the present application is conducive to the heat dissipation and temperature uniformity of the circuit board 110.
  • the above embodiments do not represent the final actual use effect, but only illustrate the invention points of heat dissipation and temperature uniformity of the present application.
  • FIG2A shows a schematic diagram of the structure of a circuit board 110 according to the second embodiment of the present application.
  • the number of chips 111 in the chip array on the circuit board 110 is 120.
  • the chip array includes a plurality of power extraction units 114 composed of parallel chips 111, and the plurality of power extraction units 114 are connected in series. Among them, the distances between at least some adjacent power extraction units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet.
  • the first distribution area includes 63 chips 111 arranged in 21 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form a power extraction unit 114, so the first distribution area includes 21 power extraction units 114.
  • the distances between the 21 power extraction units 114 in the first distribution area can be equal.
  • the second distribution area includes 57 chips 111 arranged in 19 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form a power extraction unit 114, so the second distribution area includes 19 power extraction units 114.
  • the spacing between the 7th power extraction unit 114 and the 8th power extraction unit 114 and the spacing between the 12th power extraction unit 114 and the 13th power extraction unit 114 can be greater than the spacing between other adjacent power extraction units 114.
  • the above-mentioned "other adjacent power taking units 114" are non-edge power taking units 114 in the chip array.
  • the spacing between other adjacent power taking units 114 can be the spacing between the 1st to 7th power taking units 114, the spacing between the 8th to 12th power taking units 114, and the spacing between the 13th to 19th power taking units 114 arranged in the same column.
  • the parallel connection direction is the row direction.
  • the 1st to 7th power taking units 114 in the second distribution area can be divided into a first sub-area, which includes 21 chips 111 arranged in 7 rows and 3 columns; the 8th to 12th power taking units 114 are divided into a second sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns; the 13th to 19th power taking units 114 are divided into a third sub-area, which also includes 21 chips 111 arranged in 7 rows and 3 columns.
  • the 19 power taking units 114 in the second distribution area can be divided according to the spacing between adjacent power taking units 114, and the 19 power taking units 114 can be divided into three sub-areas.
  • the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between two adjacent sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 at both ends of the series direction in each sub-area and the chip 111 at the center position is smaller, thereby effectively reducing the temperature of the chip 111 at the center position in each sub-area, and thereby reducing the temperature difference between multiple chips 111 in the sub-area.
  • the number of power taking units 114 in each distribution area can be reduced.
  • the number of power taking units 114 in the first distribution area can be 21, and the number of power taking units 114 in the second distribution area can be 19.
  • the present application is not limited to this.
  • the number of power taking units 114 in the distribution area is greater than 2, the number of power taking units 114 in each distribution area can be gradually reduced in sequence, and can be partially gradually reduced or partially reduced.
  • the number of distribution areas is 6 for illustration.
  • the number of power taking units 114 in multiple distribution areas can be 15, 14, 13, 12, 11, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 12, 12, 11, 11, 10, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 11, 10, 10, 10, 10 respectively.
  • Metal parts may be arranged between adjacent power taking units 114. In the series direction, at least some of the metal parts between adjacent power taking units 114 are longer than other adjacent power taking units 114, wherein the long direction is perpendicular to the parallel direction.
  • the metal parts may be copper sheets.
  • the metal parts arranged in this way can reduce the resistance of the current channel, reduce the voltage drop of the current channel, and thus reduce the energy loss on the current channel.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are in a straight line.
  • the centers of the three chips 111 at the end of the first distribution area and the three chips 111 at the end of the corresponding sub-area are in a straight line.
  • the gap between two adjacent sub-areas corresponds to the chips 111 in the 8th and 14th rows of the first distribution area in the first direction.
  • the 120 chips 111 in the chip array are arranged in 21 rows and 6 columns, the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the row spacing of the chips 111 in the first 3 columns is the same, and the 8th and 14th rows of the chips 111 in the last 3 columns are missing.
  • the number of chips 111 in the first 3 columns is 63, and the number of chips 111 in the last 3 columns is 57.
  • the row direction of the chip array can be the heat dissipation direction.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the second half near the air outlet, which can also reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the second distribution area is distributed in two end areas and one middle area.
  • the number of chips 111 in each end area is greater than or equal to the number of chips 111 in the middle area.
  • the chips 111 in the end area are the chips 111 in the first sub-area and the chips 111 in the third sub-area
  • the chips 111 in the middle area are the chips 111 in the second sub-area.
  • the number of chips 111 in the end areas is 21, and the number of chips 111 in the middle area is 15. Therefore, when the circuit board 110 is applied to the electronic device 3100, the chips 111 in the two end areas are closer to the external environment and the heat dissipation is better.
  • the temperature of the chips 111 in the middle area can be effectively reduced, thereby reducing the temperature difference between the chips 111 in the middle area and the chips 111 in the end areas, improving the heat dissipation effect of the circuit board 110, and ensuring the overall performance of the circuit board 110.
  • the distance between the first distribution area and the second distribution area can be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area can be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 can include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be provided corresponding to each row power taking unit 114 or each column power taking unit 114.
  • 120 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the number of chips 111 in the 8th and 14th rows is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 8th and 14th rows is less than the number of chips 111 in other rows.
  • at least part of the bosses can be set at the corresponding positions of the 7th power extraction unit 114 and the 8th power extraction unit 114 and the corresponding positions of the 12th power extraction unit 114 and the 13th power extraction unit 114.
  • FIG2B shows a current diagram of the circuit board 110 shown in FIG2A
  • FIG2C shows a signal diagram of the circuit board 110 shown in FIG2A.
  • the length of the electrical connection line between adjacent distribution areas is greater than the length of the electrical connection line between adjacent power-taking units 114 in each distribution area.
  • the electrical connection line can be the length of the power line 115 and/or the signal line 116.
  • the upper edge of the circuit board 110 is provided with a first electrical connector 119 and a second electrical connector 119', and the first electrical connector 119 and the second electrical connector 119' may be L-shaped.
  • the above is only an example, and the positions and shapes of the first electrical connector 119 and the second electrical connector 119' are not limited.
  • the first electrical connector 119 and the second electrical connector 119' are not limited to being set at the upper edge as shown in FIG. 2A, but may also be set at other edge positions. That is, the position of the L-shaped power supply terminal shown in each figure is not limited to that in the figure, and may also be set at the top, bottom, left, right or any position of the circuit board.
  • the multiple chips 111 on the circuit board 110 adopt a series-parallel power supply connection mode, specifically: every three chips are connected in parallel to form a power supply unit 114, and the multiple power supply units 114 are connected in series between the first electrical connector 119 and the second electrical connector 119'.
  • the above power supply unit 114 is composed of three chips, which is only an example.
  • the power supply unit 114 can also be composed of 2, 4, 5 or even more chips connected in parallel, and this application does not limit this.
  • a chip vacancy position 113 is set.
  • the temperature of the chip array after working for a period of time is as follows. It can be seen that the chip temperature fluctuates in the range of 70°C to 75°C, and the temperature difference is about 5°C. It should be noted that the preset power remains unchanged but the number of chips 111 is reduced, so the average power increase of each chip 111 is The increase in the heat generated by each chip 111 also increases.
  • FIG. 1B due to the existence of the chip vacancy 113, the maximum temperature is still about 75°C, the chip heat dissipation is improved, and the chip temperature uniformity is further improved. This shows that the present application is conducive to the heat dissipation and temperature uniformity of the circuit board 111.
  • the above embodiments do not represent the final actual use effect, but only illustrate the invention points of heat dissipation and temperature uniformity of the present application.
  • FIG3 shows a schematic diagram of the structure of the circuit board 110 according to the third embodiment of the present application.
  • the number of chips 111 in the chip array on the circuit board 110 is 117.
  • the chip array includes a plurality of power taking units 114 composed of parallel chips 111, and the plurality of power taking units 114 are connected in series. Among them, the distances between at least some adjacent power taking units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet. Distribution area.
  • the first distribution area includes 63 chips 111 arranged in 21 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form one power taking unit 114, so the first distribution area includes 21 power taking units 114.
  • the spacing between the power taking units 114 in the first distribution area can be equal.
  • the second distribution area includes 54 chips 111 arranged in 18 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form one power taking unit 114, so the second distribution area includes 18 power taking units 114.
  • the spacing between the 5th power taking unit 114 and the 6th power taking unit 114, the spacing between the 9th power taking unit 114 and the 10th power taking unit 114, and the spacing between the 13th power taking unit 114 and the 14th power taking unit 114 can be greater than the spacing between other adjacent power taking units 114.
  • the above-mentioned "other adjacent power taking units 114" are non-edge power taking units 114 in the chip array.
  • the spacing of other adjacent power taking units 114 can be the spacing of the 1st to 5th power taking units 114 arranged in the same column, the spacing of the 6th to 9th power taking units 114, the spacing of the 10th to 13th power taking units 114, and the spacing of the 13th to 19th power taking units 114.
  • the parallel direction is the row direction.
  • the 1st to 5th power taking units 114 in the second distribution area can be divided into a first sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns; the 6th to 9th power taking units 114 are divided into a second sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns; the 10th to 13th power taking units 114 are divided into a third sub-area, which also includes 12 chips 111 arranged in 4 rows and 3 columns; the 14th to 18th power taking units 114 are divided into a fourth sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns.
  • the 18 power taking units 114 in the second distribution area can be divided according to the spacing between adjacent power taking units 114, and the 18 power taking units 114 can be divided into 4 sub-areas.
  • the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between two adjacent sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 at both ends of the series direction in each sub-area and the chip 111 at the center position is smaller, thereby effectively reducing the temperature of the chip 111 at the center position in each sub-area, and thereby reducing the temperature difference between multiple chips 111 in the sub-area.
  • the number of power taking units 114 in each distribution area can be reduced.
  • the number of power taking units 114 in the first distribution area can be 21, and the number of power taking units 114 in the second distribution area can be 18.
  • the present application is not limited to this.
  • the number of power taking units 114 in the distribution area is greater than 2, the number of power taking units 114 in each distribution area can be gradually reduced in sequence, and can be partially reduced or partially reduced.
  • the number of distribution areas is 6 for illustration.
  • the number of power taking units 114 in multiple distribution areas can be 15, 14, 13, 12, 11, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 12, 12, 11, 11, 10, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 11, 10, 10, 10, 10 respectively.
  • Metal parts may be arranged between adjacent power taking units 114. In the series direction, at least some of the metal parts between adjacent power taking units 114 are longer than other adjacent power taking units 114, wherein the long direction is perpendicular to the parallel direction.
  • the metal parts may be copper sheets.
  • the metal parts arranged in this way can reduce the resistance of the current channel, reduce the voltage drop of the current channel, and thus reduce the energy loss on the current channel.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are in a straight line.
  • the centers of the three chips 111 at the end of the first distribution area and the three chips 111 at the end of the corresponding sub-area are in a straight line.
  • the gap between two adjacent sub-areas corresponds to the chips 111 in the 6th row, the 11th row, and the 16th row of the first distribution area in the first direction.
  • the 117 chips 111 in the chip array are arranged in 21 rows and 6 columns, and the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the row spacing of the chips 111 in the first 3 columns is the same, and the 6th row, 11th row and 16th row of the chips 111 in the last 3 columns are missing.
  • the number of chips 111 in the first 3 columns is 63, and the number of chips 111 in the last 3 columns is 54.
  • the row direction of the chip array can be the heat dissipation direction.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the second half near the air outlet, which can also reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the distance between the first distribution area and the second distribution area can be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area can be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 can include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be provided corresponding to each row power taking unit 114 or each column power taking unit 114.
  • 117 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the number of chips 111 in the 6th row, the 11th row and the 16th row is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 6th row, the 11th row and the 16th row is less than the number of chips 111 in other rows.
  • At least part of the bosses can be set at the corresponding positions of the 5th power extraction unit 114 and the 6th power extraction unit 114, the corresponding positions of the 9th power extraction unit 114 and the 10th power extraction unit 114, and the corresponding positions of the 13th power extraction unit 114 and the 14th power extraction unit 114 in the second distribution area.
  • FIG4 is a schematic diagram showing the structure of a circuit board 110 according to a fourth embodiment of the present application.
  • the circuit board The number of chips 111 in the chip array 110 is 120.
  • the chip array includes a plurality of power extraction units 114 formed by parallel chips 111, and the plurality of power extraction units 114 are connected in series. The distances between at least some adjacent power extraction units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet.
  • the first distribution area includes 66 chips 111 arranged in 22 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form a power extraction unit 114, so the first distribution area includes 22 power extraction units 114.
  • the spacing between the power extraction units 114 in the first distribution area can be equal.
  • the second distribution area includes 54 chips 111 arranged in 18 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form a power extraction unit 114, so the second distribution area includes 18 power extraction units 114.
  • the spacing between the 4th power taking unit 114 and the 5th power taking unit 114 of the second distribution area, the spacing between the 7th power taking unit 114 and the 8th power taking unit 114, the spacing between the 11th power taking unit 114 and the 12th power taking unit 114, and the spacing between the 14th power taking unit 114 and the 15th power taking unit 114 can be greater than the spacing between other adjacent power taking units 114.
  • the above-mentioned "other adjacent power taking units 114" are non-edge power taking units 114 in the chip array.
  • the spacing of other adjacent power taking units 114 can be the spacing of the 1st to 4th power taking units 114 arranged in the same column, the spacing of the 5th to 7th power taking units 114, the spacing of the 8th to 11th power taking units 114, the spacing of the 12th to 14th power taking units 114, and the spacing of the 15th to 18th power taking units 114.
  • the parallel direction is the row direction.
  • the 1st to 4th power taking units 114 in the second distribution area can be divided into a first sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the 5th to 7th power taking units 114 can be divided into a first sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • 14 is divided into a second sub-region, which includes 9 chips 111 arranged in 3 rows and 3 columns;
  • the 8th to 11th power taking units 114 are divided into a third sub-region, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the 12th to 14th power taking units 114 are divided into a fourth sub-region, which includes 9 chips
  • the 18 power taking units 114 in the second distribution area can be divided according to the spacing between adjacent power taking units 114, and the 18 power taking units 114 can be divided into 5 sub-areas, and the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between two adjacent sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 at both ends of the series connection direction in each sub-area and the chip 111 at the center position is smaller, which effectively reduces the temperature of the chip 111 at the center position in each sub-area, and further improves the performance of the power taking units 114. This reduces the temperature difference between the multiple chips 111 in the sub-region.
  • the number of power taking units 114 in each distribution area can be reduced.
  • the number of power taking units 114 in the first distribution area can be 22, and the number of power taking units 114 in the second distribution area can be 18.
  • the present application is not limited to this.
  • the number of power taking units 114 in the distribution area is greater than 2, the number of power taking units 114 in each distribution area can be gradually reduced in sequence, and can be partially gradually reduced or partially reduced.
  • the number of distribution areas is 6 for illustration.
  • the number of power taking units 114 in multiple distribution areas can be 15, 14, 13, 12, 11, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 12, 12, 11, 11, 10, 10 respectively; or, the number of power taking units 114 in multiple distribution areas can be 11, 10, 10, 10, 10 respectively.
  • Metal parts may be arranged between adjacent power taking units 114. In the series direction, at least some of the metal parts between adjacent power taking units 114 are longer than other adjacent power taking units 114, wherein the long direction is perpendicular to the parallel direction.
  • the metal parts may be copper sheets.
  • the metal parts arranged in this way can reduce the resistance of the current channel, reduce the voltage drop of the current channel, and thus reduce the energy loss on the current channel.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are in a straight line.
  • the centers of the three chips 111 at the end of the first distribution area and the three chips 111 at the end of the corresponding sub-area are in a straight line.
  • the gap between two adjacent sub-areas corresponds to the chips 111 in the 5th row, the 9th row, the 14th row, and the 18th row of the first distribution area in the first direction.
  • the 120 chips 111 in the chip array are arranged in 22 rows and 6 columns, and the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the row spacing of the chips 111 in the first 3 columns is the same, and the chips 111 in the 5th row, the 9th row, the 14th row and the 18th row of the chips 111 in the last 3 columns are missing.
  • the number of chips 111 in the first 3 columns is 66, and the number of chips 111 in the last 3 columns is 54.
  • the row direction of the chip array can be the heat dissipation direction.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the second half near the air outlet, which can also reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the distance between the first distribution area and the second distribution area can be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area can be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 can include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be provided corresponding to each row power taking unit 114 or each column power taking unit 114.
  • 120 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the heat dissipation direction from the air inlet to the air outlet of the heat dissipation air duct.
  • the number of chips 111 in the 5th row, the 9th row, the 14th row and the 18th row is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 5th row, the 9th row, the 14th row and the 18th row is less than the number of chips 111 in other rows.
  • At least part of the bosses can be set at the corresponding position between the 4th power taking unit 114 and the 5th power taking unit 114, the corresponding position between the 7th power taking unit 114 and the 8th power taking unit 114, the corresponding position between the 11th power taking unit 114 and the 12th power taking unit 114, and the corresponding position between the 14th power taking unit 114 and the 15th power taking unit 114 in the second distribution area.
  • FIG5 shows a schematic diagram of the structure of the circuit board 110 according to the fifth embodiment of the present application.
  • the number of chips 111 in the chip array on the circuit board 110 is 120.
  • the chip array includes a plurality of power taking units 114 composed of parallel chips 111, and the plurality of power taking units 114 are connected in series. Among them, the distances between at least some adjacent power taking units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet.
  • the first distribution area includes 66 chips 111 arranged in 22 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form a power extraction unit 114, so the first distribution area includes 22 power extraction units 114.
  • the spacing between the power extraction units 114 in the first distribution area can be equal.
  • the second distribution area includes 54 chips 111 arranged in 18 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form a power extraction unit 114, so the second distribution area includes 18 power extraction units 114.
  • the spacing between the 4th power taking unit 114 and the 5th power taking unit 114 of the second distribution area, the spacing between the 7th power taking unit 114 and the 8th power taking unit 114, the spacing between the 10th power taking unit 114 and the 11th power taking unit 114, and the spacing between the 14th power taking unit 114 and the 15th power taking unit 114 can be greater than the spacing between other adjacent power taking units 114.
  • the above-mentioned "other adjacent power taking units 114" are non-edge power taking units 114 in the chip array.
  • the spacing of other adjacent power taking units 114 can be the spacing of the 1st to 4th power taking units 114 arranged in the same column, the spacing of the 5th to 7th power taking units 114, the spacing of the 8th to 10th power taking units 114, the spacing of the 11th to 14th power taking units 114, and the spacing of the 15th to 18th power taking units 114.
  • the parallel direction is the row direction.
  • the 1st to 4th power taking units 114 in the second distribution area can be divided into a first sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the 5th to 7th power taking units 114 are divided into a second sub-region, which includes 9 chips 111 arranged in 3 rows and 3 columns;
  • the 8th to 10th power taking units 114 are divided into a third sub-region, which includes 9 chips 111 arranged in 3 rows and 3 columns;
  • the 11th to 14th power taking units 114 are divided into a fourth sub-region, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the 15th to 18th power taking units 114 are divided into a fifth
  • the 18 power taking units 114 in the second distribution area can be divided according to the spacing between adjacent power taking units 114, and the 18 power taking units 114 can be divided into 5 sub-areas.
  • the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between two adjacent sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 at both ends of the series direction in each sub-area and the chip 111 at the center position is smaller, thereby effectively reducing the temperature of the chip 111 at the center position in each sub-area, and thereby reducing the temperature difference between multiple chips 111 in the sub-area.
  • the number of power taking units 114 in each distribution area can be reduced. As shown in FIG5 , the number of power taking units 114 in the first distribution area can be 22, and the number of power taking units 114 in the second distribution area can be 18.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are in a straight line.
  • the centers of the three chips 111 at the end of the first distribution area and the three chips 111 at the end of the corresponding sub-area are in a straight line.
  • the gap between two adjacent sub-areas corresponds to the chips 111 in the 5th row, the 9th row, the 13th row, and the 18th row of the first distribution area in the first direction.
  • the 120 chips 111 in the chip array are arranged in 22 rows and 6 columns, and the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the row spacing of the chips 111 in the first 3 columns is the same, and the chips 111 in the 5th row, the 9th row, the 13th row and the 18th row of the chips 111 in the last 3 columns are missing.
  • the number of chips 111 in the first 3 columns is 66, and the number of chips 111 in the last 3 columns is 54.
  • the row direction of the chip array can be the heat dissipation direction.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the second half near the air outlet, which can also reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the distance between the first distribution area and the second distribution area can be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area can be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 may include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be connected to each row power taking unit 114 or each column power taking unit.
  • the electrical unit 114 is configured accordingly.
  • 120 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the heat dissipation direction from the air inlet to the air outlet of the heat dissipation air duct.
  • the number of chips 111 in the 5th row, the 9th row, the 13th row and the 18th row is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 5th row, the 9th row, the 13th row and the 18th row is less than the number of chips 111 in other rows.
  • At least part of the bosses can be set at the corresponding position between the 4th power taking unit 114 and the 5th power taking unit 114, the corresponding position between the 7th power taking unit 114 and the 8th power taking unit 114, the corresponding position between the 10th power taking unit 114 and the 11th power taking unit 114, and the corresponding position between the 14th power taking unit 114 and the 15th power taking unit 114 in the second distribution area.
  • FIG6A and FIG6B show a schematic diagram of the structure of the circuit board 110 according to the sixth embodiment of the present application.
  • the number of chips 111 in the chip array on the circuit board 110 is 117.
  • the chip array includes a plurality of power extraction units 114 composed of parallel chips 111, and the plurality of power extraction units 114 are connected in series. Among them, the distances between at least some adjacent power extraction units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet.
  • the first distribution area includes 60 chips 111 arranged in 20 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form a power extraction unit 114, so the first distribution area includes 20 power extraction units 114.
  • the distances between the 20 power extraction units 114 in the first distribution area can be equal.
  • the second distribution area includes 57 chips 111 arranged in 19 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form a power extraction unit 114, so the second distribution area includes 19 power extraction units 114.
  • the spacing between the 10th power taking unit 114 and the 11th power taking unit 114 in the first distribution area can be greater than the spacing between other adjacent power taking units 114; the spacing between the 7th power taking unit 114 and the 8th power taking unit 114 in the second distribution area and the spacing between the 12th power taking unit 114 and the 13th power taking unit 114 can be greater than the spacing between other adjacent power taking units 114.
  • the parallel connection direction is the row direction.
  • the first distribution area can be divided into two sub-areas, each of which includes 20 chips 111 arranged in 10 rows and 3 columns.
  • the 1st to 7th power taking units 114 in the second distribution area can be divided into the first sub-area, which includes 21 chips 111 arranged in 7 rows and 3 columns;
  • the 8th to 12th power taking units 114 are divided into the second sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns;
  • the 13th to 19th power taking units 114 are divided into the third sub-area, which also includes 21 chips 111 arranged in 7 rows and 3 columns. Chip 111.
  • the power taking units 114 in the first distribution area and the second distribution area can be divided according to the spacing between adjacent power taking units 114, and the 20 power taking units 114 in the first distribution area can be divided into two sub-areas, and the 19 power taking units 114 in the second distribution area can be divided into three sub-areas.
  • the power taking units 114 in each sub-area can be arranged at equal intervals, and the spacing between two adjacent sub-areas can be greater than the spacing between adjacent power taking units 114 in each sub-area, so that the distance between the chips 111 at both ends of the series direction in each sub-area and the chip 111 at the center position is smaller, thereby effectively reducing the temperature of the chip 111 at the center position in each sub-area, and thereby reducing the temperature difference between multiple chips 111 in the sub-area.
  • the number of power taking units 114 in each distribution area can be reduced. As shown in FIG6A , the number of power taking units 114 in the first distribution area can be 20, and the number of power taking units 114 in the second distribution area can be 19.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are on a straight line.
  • the 117 chips 111 in the chip array are arranged in 21 rows and 6 columns, with the centers of the chips 111 in each row being in a straight line, and the centers of the chips 111 in each column being in a straight line.
  • the 11th row of the first 3 columns of chips 111 is missing, and the 8th and 14th rows of the last 3 columns of chips 111 are missing.
  • the number of chips 111 in the first 3 columns is 60, and the number of chips 111 in the last 3 columns is 57.
  • the row direction of the chip array can be the heat dissipation direction.
  • the total number of chips 111 in the front half near the air inlet is greater than the total number of chips 111 in the second half near the air outlet, which can also reduce the maximum temperature difference between the chips 111 near the air outlet and the chips 111 near the air inlet, thereby improving the temperature uniformity of the chips 111.
  • the second distribution area is distributed in two end areas and one middle area.
  • the number of chips 111 in each end area is greater than or equal to the number of chips 111 in the middle area.
  • the chips 111 in the end area are the chips 111 in the first sub-area and the chips 111 in the third sub-area
  • the chips 111 in the middle area are the chips 111 in the second sub-area.
  • the number of chips 111 in the end areas is 21, and the number of chips 111 in the middle area is 15. Therefore, when the circuit board 110 is applied to the electronic device 3100, the chips 111 in the two end areas are closer to the external environment and the heat dissipation is better.
  • the temperature of the chips 111 in the middle area can be effectively reduced, thereby reducing the temperature difference between the chips 111 in the middle area and the chips 111 in the end areas, improving the heat dissipation effect of the circuit board 110, and ensuring the overall performance of the circuit board 110.
  • the distance between the first distribution area and the second distribution area can be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area can be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 can include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be provided corresponding to each row power taking unit 114 or each column power taking unit 114.
  • 117 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the number of chips 111 in the 8th row, the 11th row and the 14th row is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 8th row, the 11th row and the 14th row is less than the number of chips 111 in other rows.
  • At least part of the bosses can be set at the corresponding position between the 10th power extraction unit 114 and the 11th power extraction unit 114 in the first distribution area, the corresponding position between the 7th power extraction unit 114 and the 8th power extraction unit 114 in the second distribution area, and the corresponding position between the 12th power extraction unit 114 and the 13th power extraction unit 114.
  • FIG7 shows a schematic diagram of the structure of the circuit board 110 according to the seventh embodiment of the present application.
  • the number of chips 111 in the chip array on the circuit board 110 is 117.
  • the chip array includes a plurality of power taking units 114 composed of parallel chips 111, and the plurality of power taking units 114 are connected in series. Among them, the distances between at least some adjacent power taking units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet.
  • the first distribution area includes 60 chips 111 arranged in 20 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form a power extraction unit 114, so the first distribution area includes 20 power extraction units 114.
  • the distances between the 20 power extraction units 114 in the first distribution area can be equal.
  • the second distribution area includes 57 chips 111 arranged in 19 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form a power extraction unit 114, so the second distribution area includes 19 power extraction units 114.
  • the spacing between the 10th power taking unit 114 and the 11th power taking unit 114 in the first distribution area can be greater than the spacing between other adjacent power taking units 114; the spacing between the 6th power taking unit 114 and the 7th power taking unit 114 in the second distribution area and the spacing between the 13th power taking unit 114 and the 14th power taking unit 114 can be greater than the spacing between other adjacent power taking units 114.
  • the parallel connection direction is the row direction.
  • the first distribution area can be divided into two sub-areas, each of which includes 20 chips 111 arranged in 10 rows and 3 columns.
  • the 1st to 6th power taking units 114 in the second distribution area can be divided into the first sub-area, which includes 18 chips 111 arranged in 6 rows and 3 columns;
  • the 7th to 13th power taking units 114 in the second distribution area can be divided into the second sub-area, which includes 18 chips 111 arranged in 6 rows and 3 columns;
  • the power unit 114 is divided into a second sub-region, which includes 21 chips 111 arranged in 7 rows and 3 columns;
  • the 14th to 19th power units 114 are divided into a third sub-region, which includes 18 chips 111 arranged in 6 rows and 3 columns
  • the number of power taking units 114 in each distribution area can be reduced. As shown in FIG7 , the number of power taking units 114 in the first distribution area can be 20, and the number of power taking units 114 in the second distribution area can be 19.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are on a straight line.
  • the 117 chips 111 in the chip array are arranged in 21 rows and 6 columns, the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the 11th row of the first 3 columns of chips 111 is missing, and the 7th and 15th rows of the last 3 columns of chips 111 are missing.
  • the number of chips 111 in the first 3 columns is 60, and the number of chips 111 in the last 3 columns is 57.
  • the row direction of the chip array can be the heat dissipation direction.
  • the distance between the first distribution area and the second distribution area may be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area may be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 may gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 can include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be provided corresponding to each row power taking unit 114 or each column power taking unit 114.
  • 117 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • the number of chips 111 in the 7th row, the 11th row and the 15th row is 3 respectively, and the number of chips 111 in other rows is 6, so the number of chips 111 in the 7th row, the 11th row and the 15th row is less than the number of chips 111 in other rows.
  • At least part of the bosses can be set at the corresponding position between the 10th power extraction unit 114 and the 11th power extraction unit 114 in the first distribution area, the corresponding position between the 6th power extraction unit 114 and the 7th power extraction unit 114 in the second distribution area, and the corresponding position between the 13th power extraction unit 114 and the 14th power extraction unit 114.
  • FIG8 is a schematic diagram showing the structure of a circuit board 110 according to an eighth embodiment of the present application.
  • the number of chips 111 in the chip array on the circuit board 110 is 114.
  • the chip array includes a plurality of power taking units 114 composed of parallel chips 111, and the plurality of power taking units 114 are connected in series. Among them, the distances between at least some adjacent power taking units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet.
  • the first distribution area includes 60 chips 111 arranged in 20 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form a power extraction unit 114, so the first distribution area includes 20 power extraction units 114.
  • the distances between the 20 power extraction units 114 in the first distribution area can be equal.
  • the second distribution area includes 54 chips 111 arranged in 18 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form a power extraction unit 114, so the second distribution area includes 18 power extraction units 114.
  • the spacing between the 10th power taking unit 114 and the 11th power taking unit 114 in the first distribution area can be greater than the spacing between other adjacent power taking units 114; the spacing between the 5th power taking unit 114 and the 6th power taking unit 114, the spacing between the 9th power taking unit 114 and the 10th power taking unit 114, and the spacing between the 13th power taking unit 114 and the 14th power taking unit 114 in the second distribution area can be greater than the spacing between other adjacent power taking units 114.
  • the parallel connection direction is the row direction.
  • the first distribution area can be divided into two sub-areas, each of which includes 20 chips 111 arranged in 10 rows and 3 columns.
  • the 1st to 5th power taking units 114 in the second distribution area can be divided into a first sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns;
  • the 6th to 9th power taking units 114 are divided into a second sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the 10th to 13th power taking units 114 are divided into a third sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the number of power taking units 114 in each distribution area can be reduced. As shown in FIG8 , the number of power taking units 114 in the first distribution area can be 20, and the number of power taking units 114 in the second distribution area can be 18.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are on a straight line.
  • the 114 chips 111 in the chip array are arranged in 21 rows and 6 columns, the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the 11th row of the first 3 columns of chips 111 is missing, and the 6th row, 11th row and 16th row of the last 3 columns of chips 111 are missing.
  • the number of chips 111 in the first 3 columns is 60, and the number of chips 111 in the last 3 columns is 54.
  • the row direction of the chip array can be the heat dissipation direction.
  • the distance between the first distribution area and the second distribution area may be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area may be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 may gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 may include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface The second surface is connected to the heat dissipation fins and is provided with a plurality of bosses, each of which can be provided corresponding to each row of power taking units 114 or each column of power taking units 114 .
  • 114 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • at least part of the bosses can be set at the corresponding position between the 10th power taking unit 114 and the 11th power taking unit 114 in the first distribution area, the corresponding position between the 5th power taking unit 114 and the 6th power taking unit 114 in the second distribution area, the corresponding position between the 9th power taking unit 114 and the 10th power taking unit 114, and the corresponding position between the 13th power taking unit 114 and the 14th power taking unit 114.
  • FIG9 shows a schematic diagram of the structure of the circuit board 110 according to the ninth embodiment of the present application.
  • the number of chips 111 in the chip array on the circuit board 110 is 120.
  • the chip array includes a plurality of power taking units 114 composed of parallel chips 111, and the plurality of power taking units 114 are connected in series. Among them, the distances between at least some adjacent power taking units 114 are not equal.
  • the chip array includes a first distribution area arranged near the air inlet and a second distribution area arranged near the air outlet.
  • the first distribution area includes 60 chips 111 arranged in 20 rows and 3 columns, and the 3 chips 111 in each row in the first distribution area are connected in parallel to form a power extraction unit 114, so the first distribution area includes 20 power extraction units 114.
  • the distances between the 20 power extraction units 114 in the first distribution area can be equal.
  • the second distribution area includes 54 chips 111 arranged in 18 rows and 3 columns, and the 3 chips 111 in each row in the second distribution area are connected in parallel to form a power extraction unit 114, so the second distribution area includes 18 power extraction units 114.
  • the spacing between the 10th power taking unit 114 and the 11th power taking unit 114 in the first distribution area can be greater than the spacing between other adjacent power taking units 114; the spacing between the 5th power taking unit 114 and the 6th power taking unit 114, the spacing between the 9th power taking unit 114 and the 10th power taking unit 114, and the spacing between the 13th power taking unit 114 and the 14th power taking unit 114 in the second distribution area can be greater than the spacing between other adjacent power taking units 114.
  • the parallel connection direction is the row direction.
  • the first distribution area can be divided into two sub-areas, each of which includes 20 chips 111 arranged in 10 rows and 3 columns.
  • the 1st to 5th power taking units 114 in the second distribution area can be divided into a first sub-area, which includes 15 chips 111 arranged in 5 rows and 3 columns;
  • the 6th to 9th power taking units 114 are divided into a second sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the 10th to 13th power taking units 114 are divided into a third sub-area, which includes 12 chips 111 arranged in 4 rows and 3 columns;
  • the number of power taking units 114 in each distribution area can be reduced. As shown in FIG8 , the number of power taking units 114 in the first distribution area can be 20, and the number of power taking units 114 in the second distribution area can be 18.
  • the row spacing of the chips 111 in each distribution area is the same, and the centers of the multiple chips 111 in each row are on a straight line.
  • the 114 chips 111 in the chip array are arranged in 21 rows and 6 columns, the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the 11th row of the first 3 columns of chips 111 is missing, and the 6th row, 11th row, and 16th row of the last 3 columns of chips 111 are missing.
  • the number of chips 111 in the first 3 columns is 60, and the number of chips 111 in the last 3 columns is 54.
  • the row direction of the chip array can be the heat dissipation direction.
  • the distance between the first distribution area and the second distribution area may be greater than the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between the first distribution area and the second distribution area may be equal to the distance between two adjacent columns of chips 111 in each distribution area; or, along the parallel direction, the distance between multiple columns of chips 111 may gradually increase or decrease.
  • the circuit board 110 can be applied to the working component 2100.
  • the working component 2100 can include a heat sink 2110.
  • the heat sink 2110 includes a heat sink body and heat sink fins.
  • the heat sink body includes a first surface and a second surface opposite to each other. The first surface is connected to the heat sink fins.
  • the second surface is provided with a plurality of bosses. Each boss can be provided corresponding to each row power taking unit 114 or each column power taking unit 114.
  • 114 chips 111 on the circuit board 110 are arranged in multiple rows, and the row direction is parallel to the direction from the air inlet to the air outlet of the heat dissipation duct.
  • at least part of the bosses can be set at the corresponding position between the 10th power taking unit 114 and the 11th power taking unit 114 in the first distribution area, the corresponding position between the 5th power taking unit 114 and the 6th power taking unit 114 in the second distribution area, the corresponding position between the 9th power taking unit 114 and the 10th power taking unit 114, and the corresponding position between the 13th power taking unit 114 and the 14th power taking unit 114.
  • the circuit board 110 includes two first chip arrays arranged near the air inlet and four second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the two first chip arrays are arranged at intervals in the second direction, and the four second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent first chip arrays and the distance between two adjacent second chip arrays are both greater than the row spacing of the chips 111.
  • one of the first chip arrays includes 30 chips 111 arranged in 10 rows and 3 columns, and the other first chip array includes 33 chips 111 arranged in 11 rows and 3 columns.
  • the row spacing of the chips 111 in each first chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the first second chip array, the third second chip array, and the fourth second chip array respectively include 15 chips 111 arranged in 5 rows and 3 columns, and the second second chip array includes 12 chips 111 arranged in 4 rows and 3 columns.
  • the row spacing of the chips 111 in each second chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the gap between the second second chip array and the third second chip array is the first gap.
  • the gap between the two first chip arrays is on the same straight line as the first gap.
  • chips 111 are arranged in an array on the circuit board 110.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the 11th row of the first three columns of chips 111 is missing, and the 6th row, 11th row and 17th row of the last three columns of chips 111 are missing.
  • the number of chips 111 in the first three columns is 63, and the number of chips 111 in the last three columns is 57.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG10 shows a schematic diagram of the structure of the circuit board 110 according to the tenth embodiment of the present application.
  • the circuit board 110 includes a first chip array arranged near the air inlet and three second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the three second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent second chip arrays is greater than the row spacing of the chips 111.
  • the first chip array includes 60 chips 111 arranged in 20 rows and 3 columns.
  • the row spacing of the chips 111 in the first chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the first second chip array and the third second chip array respectively include 21 chips 111 arranged in 7 rows and 3 columns, and the second second chip array includes 15 chips 111 arranged in 5 rows and 3 columns.
  • the row spacing of the chips 111 in each second chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the centers of the three chips 111 at one end of the first chip array and the three chips 111 at the end of the corresponding second chip array are not in a straight line, and the centers of the three chips 111 at the other end of the first chip array and the three chips 111 at the end of the corresponding second chip array are in a straight line.
  • 117 chips 111 are arranged in an array on the circuit board 110.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the first row of the first three columns of chips 111 is missing, and the eighth and fourteenth rows of the last three columns of chips 111 are missing.
  • the number of chips 111 in the first three columns is 60, and the number of chips 111 in the last three columns is 57.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG11 shows a schematic diagram of the structure of a circuit board 110 according to the eleventh embodiment of the present application.
  • the circuit board 110 includes a first chip array arranged near the air inlet and three second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the three second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent second chip arrays is greater than the row spacing of the chips 111.
  • the first chip array includes 57 chips 111 arranged in 19 rows and 3 columns.
  • the row spacing of the chips 111 in the first chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the first second chip array and the third second chip array respectively include 21 chips 111 arranged in 7 rows and 3 columns, and the second second chip array includes 15 chips 111 arranged in 5 rows and 3 columns.
  • the row spacing of the chips 111 in each second chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the centers of the three chips 111 at the end of the first chip array and the three chips 111 at the end of the corresponding second chip array are not in a straight line.
  • chips 111 are arranged in an array on the circuit board 110.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the first and 22 rows of the first three columns of chips 111 are missing, and the 8th and 14th rows of the last three columns of chips 111 are missing.
  • the number of chips 111 in the first three columns is 57, and the number of chips 111 in the last three columns is 57.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG12 shows a schematic diagram of the structure of the circuit board 110 according to the twelve embodiment of the present application.
  • the circuit board 110 includes three first chip arrays arranged near the air inlet and three second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the three first chip arrays are arranged at intervals in the second direction, and the three second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent first chip arrays and the distance between two adjacent second chip arrays are both greater than the row spacing of the chips 111.
  • each first chip array located at the end includes 21 chips 111 arranged in 7 rows and 3 columns, and the first chip array located in the middle includes 15 chips 111 arranged in 5 rows and 3 columns.
  • the row spacing of the chips 111 in each first chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • each second chip array located at the end includes 21 chips 111 arranged in 7 rows and 3 columns, and the second chip array located in the middle includes 15 chips 111 arranged in 5 rows and 3 columns.
  • the chips 111 in each second chip array are arranged in a straight line.
  • the row spacings of the chips 111 are equal, and the centers of the three chips 111 in each row are on a straight line.
  • the gap between two adjacent first chip arrays and the gap between two adjacent second chip arrays are on the same straight line.
  • chips 111 are arranged in an array on the circuit board 110.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the 8th and 14th rows of the first three columns of chips 111 are missing, and the 8th and 14th rows of the last three columns of chips 111 are missing.
  • the number of chips 111 in the first three columns is 57, and the number of chips 111 in the last three columns is 57.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG13 shows a schematic diagram of the structure of the circuit board 110 according to the thirteenth embodiment of the present application.
  • the circuit board 110 includes three first chip arrays arranged near the air inlet and three second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the three first chip arrays are arranged at intervals in the second direction, and the three second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent first chip arrays and the distance between two adjacent second chip arrays are both greater than the row spacing of the chips 111.
  • each first chip array located at the end includes 18 chips 111 arranged in 6 rows and 3 columns, and the first chip array located in the middle includes 21 chips 111 arranged in 7 rows and 3 columns.
  • the row spacing of the chips 111 in each first chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • each second chip array located at the end includes 21 chips 111 arranged in 7 rows and 3 columns, and the second chip array located in the middle includes 15 chips 111 arranged in 5 rows and 3 columns.
  • the row spacing of the chips 111 in each second chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the gap between two adjacent first chip arrays is staggered with the gap between two adjacent second chip arrays.
  • chips 111 are arranged in an array on the circuit board 110.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the 7th and 15th rows of the first three columns of chips 111 are missing, and the 8th and 14th rows of the last three columns of chips 111 are missing.
  • the number of chips 111 in the first three columns is 57, and the number of chips 111 in the last three columns is 57.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG14 shows a schematic diagram of the structure of the circuit board 110 according to the fourteenth embodiment of the present application.
  • the circuit board 110 includes three first chip arrays arranged near the air inlet and four second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the three first chip arrays are arranged at intervals in the second direction, and the four second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent first chip arrays and the distance between two adjacent second chip arrays are both greater than the row spacing of the chips 111.
  • each first chip array located at the end includes 21 chips 111 arranged in 7 rows and 3 columns, and the first chip array located in the middle includes 18 chips 111 arranged in 6 rows and 3 columns.
  • the row spacing of the chips 111 in each first chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the first second chip array, the third second chip array, and the fourth second chip array respectively include 15 chips 111 arranged in 5 rows and 3 columns, and the second second chip array includes 12 chips 111 arranged in 4 rows and 3 columns.
  • the row spacing of the chips 111 in each second chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the gap between two adjacent first chip arrays is staggered with the gap between two adjacent second chip arrays.
  • 117 chips 111 are arranged in an array on the circuit board 110.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the 8th and 15th rows of the first three columns of chips 111 are missing, and the 6th, 11th and 17th rows of the last three columns of chips 111 are missing.
  • the number of chips 111 in the first three columns is 60, and the number of chips 111 in the last three columns is 57.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG15 shows a schematic diagram of the structure of the circuit board 110 according to the fifteenth embodiment of the present application.
  • the circuit board 110 includes four first chip arrays arranged near the air inlet and five second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the four first chip arrays are arranged at intervals in the second direction, and the five second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent first chip arrays and the distance between two adjacent second chip arrays are both greater than the row spacing of the chips 111.
  • the first first chip array and the fourth first chip array respectively include 15 chips 111 arranged in 5 rows and 3 columns, and the second first chip array and the third first chip array respectively include 12 chips 111 arranged in 4 rows and 3 columns.
  • the row spacing of the chips 111 in each first chip array is equal. And the centers of the three chips 111 in each row are in a straight line.
  • the first second chip array includes 6 chips 111 arranged in 2 rows and 3 columns; the second second chip array, the third second chip array and the fifth second chip array respectively include 12 chips 111 arranged in 4 rows and 3 columns, and the fourth second chip array includes 3 chips 111 arranged in 3 rows and 3 columns.
  • the row spacing of the chips 111 in each second chip array is equal, and the centers of the three chips 111 in each row are in a straight line. Among them, the gap between two adjacent first chip arrays and the gap between two adjacent second chip arrays are staggered.
  • chips 111 are arranged in an array on the circuit board 110.
  • the centers of the chips 111 in each row are in a straight line, and the centers of the chips 111 in each column are in a straight line.
  • the 6th, 11th and 16th rows of the first three columns of chips 111 are missing, and the 3rd, 8th, 13th and 17th rows of the last three columns of chips 111 are missing.
  • the number of chips 111 in the first three columns is 54, and the number of chips 111 in the last three columns is 51.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG16 shows a schematic diagram of the structure of the circuit board 110 according to the sixteenth embodiment of the present application.
  • the circuit board 110 includes six first chip arrays arranged near the air inlet and six second chip arrays arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the six first chip arrays are arranged at intervals in the second direction, and the six second chip arrays are arranged at intervals in the second direction, and the distance between two adjacent first chip arrays and the distance between two adjacent second chip arrays are both greater than the row spacing of the chips 111.
  • the first to fifth first chip arrays respectively include 9 chips 111 arranged in 3 rows and 3 columns
  • the first first chip array includes 9 chips 111 arranged in 2 rows and 3 columns
  • the sixth first chip array includes 3 chips 111 arranged in 1 row and 3 columns.
  • the row spacing of the chips 111 in each first chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the first first chip array includes 3 chips 111 arranged in 1 row and 3 columns
  • the second to sixth second chip arrays respectively include 9 chips 111 arranged in 3 rows and 3 columns.
  • the row spacing of the chips 111 in each second chip array is equal, and the centers of the three chips 111 in each row are in a straight line.
  • the gap between two adjacent first chip arrays is staggered with the gap between two adjacent second chip arrays.
  • the circuit board 110 is provided with 93 chips 111 arranged in an array.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the first row, the fourth row, the eighth row, the twelfth row, the sixteenth row, and the twentieth row of the chips 111 in the first three columns are missing, and the second row, the sixth row, the tenth row, and the sixth row are missing.
  • the number of chips 111 in the first three columns is 45, and the number of chips 111 in the last three columns is 48.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG17 shows a schematic diagram of the structure of the circuit board 110 according to the seventeenth embodiment of the present application.
  • the circuit board 110 includes three first chip arrays arranged near the air inlet and one second chip array arranged near the air outlet.
  • the multiple chips 111 in the first chip array and the second chip array are arranged in rows.
  • the two first chip arrays are spaced apart in the second direction, and the distance between the two first chip arrays is greater than the row spacing of the chips 111.
  • each first chip array located at the end includes 21 chips 111 arranged in 7 rows and 3 columns, and the first chip array located in the middle includes 15 chips 111 arranged in 5 rows and 3 columns, and the row spacing of the chips 111 in each first chip array is equal.
  • the second chip array includes 63 chips 111 arranged in 21 rows and 3 columns, and the row spacing of the chips 111 in the second chip array is equal, and the centers of the multiple chips 111 in each row are in a straight line.
  • the centers of the three chips 111 at the end of the first chip array and the three chips 111 at the end of the corresponding second chip array are in a straight line.
  • the gap between two adjacent first chip arrays corresponds to the chips 111 in the 8th and 14th rows of the second chip array in the first direction, respectively.
  • a total of 120 chips 111 are arranged in 21 rows and 6 columns on the circuit board 110.
  • the centers of the chips 111 in each row are on a straight line, and the centers of the chips 111 in each column are on a straight line.
  • the row spacings of the chips 111 in the last three columns are the same, and the 8th and 14th rows of the chips 111 in the first three columns are missing.
  • the number of chips 111 in the first three columns is 57, and the number of chips 111 in the last three columns is 63.
  • the distance between the first chip array and the second chip array can be greater than the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between the first chip array and the second chip array can be equal to the distance between two adjacent columns of chips 111 in each chip array; or, along the first direction, the distance between multiple columns of chips 111 can gradually increase or decrease.
  • FIG18 is a schematic diagram showing the structure of a circuit board 110 according to the eighteenth embodiment of the present application.
  • a total of 21 rows and 6 columns of chips 111 are arranged on the circuit board 110.
  • the 10th row, 11th row and 12th row of the sixth column of chips 111 are missing.
  • the number of chips 111 in the first three columns is 63, and the number of chips 111 in the last three columns is 60.
  • the distance between two adjacent columns of chips 111 can be gradually increased; or, along the first direction, the distance between adjacent two columns of chips 111 can be gradually increased.
  • the distance between two columns of chips 111 may gradually decrease; or, along the first direction, the distance between the third column and the fourth column of chips 111 may be greater than the distance between the chips 111 between the remaining two adjacent columns; of course, the present application is not limited thereto, for example, along the first direction, the distance between each two adjacent columns of chips 111 may be equal, or the column spacing of multiple chips 111 may not have any regularity.
  • FIG19A shows a schematic diagram of the structure of a circuit board 110 according to the nineteenth embodiment of the present application. As shown in FIG19A , a total of 10 columns and 8 rows of chips 111 are arranged on the circuit board 110. The total number of chips 111 is 76, and the third to sixth rows of the third column of chips 111 are missing.
  • the distance between two adjacent columns of chips 111 can gradually increase; or, along the first direction, the distance between two adjacent columns of chips 111 can gradually decrease; or, along the first direction, the distance between the third and fourth columns of chips 111 is greater than the distance between the remaining two adjacent columns of chips 111; of course, the present application is not limited to this, for example, along the first direction, the distance between each two adjacent columns of chips 111 is equal, or the column spacing of multiple chips 111 can have no regularity.
  • FIG19B shows a current diagram of the circuit board 110 shown in FIG19A.
  • the circuit board 110 when the heat dissipation direction is the up-down direction, the circuit board 110 includes three first chip arrays arranged near the air inlet and three second chip arrays arranged near the air outlet.
  • the first chip array located at the edge of the first direction includes 10 chip 111 groups
  • the two second chip arrays located in the middle of the first direction include 2 and 7 chip 111 groups, respectively.
  • the second chip array located at the edge of the first direction includes 10 chip 111 groups
  • the two second chip arrays located in the middle of the first direction include 2 and 7 chip 111 groups, respectively.
  • Each chip 111 group is composed of 2 chips 111 connected in parallel to form a power extraction unit 114.
  • the length of the electrical connection line between adjacent chip arrays is greater than the length of the electrical connection line between adjacent chip 111 groups, and the length of the signal line 116 between adjacent chip arrays is greater than the length of the signal line 116 between adjacent chip 111 groups.
  • the first and second rows of chips form a chip array
  • the third and fourth rows of chips are divided into two chip arrays by the vacant position 113
  • the fifth and sixth rows of chips are divided into two chip arrays by the vacant position 113
  • the seventh and eighth rows of chips form a chip array.
  • the parallel connection direction of the chips is perpendicular to the heat dissipation direction
  • the vacant position 113 is located in the chip array near the air outlet.
  • FIG20 is a schematic diagram showing the structure of the circuit board 110 according to the twenty-first embodiment of the present application.
  • the total number of chips 111 is 129, and the tenth to twelfth columns of the first row of chips 111 are missing.
  • the distance between two adjacent columns of chips 111 can gradually increase; or, along the first direction, the distance between two adjacent columns of chips 111 can gradually decrease; or, along the first direction, the distance between the third and fourth columns of chips 111 is greater than the distance between the remaining two adjacent columns of chips.
  • the present application is not limited thereto, for example, the distance between each two adjacent columns of chips 111 may be equal along the first direction, or the column spacing of the multiple chips 111 may have no regularity.
  • Fig. 21A shows a schematic diagram of the structure of a circuit board 110 according to Embodiment 21 of the present application. As shown in Fig. 21A, the total number of chips 111 on the circuit board 110 is 100, and the sixth row of chips 111 is missing.
  • FIG21B shows a current diagram of the circuit board 110 shown in FIG21A.
  • the circuit board 110 includes a first chip array disposed near the air inlet and a second chip array disposed near the air outlet.
  • the first chip array and the second chip array include five chip 111 groups, respectively.
  • Each chip 111 group is composed of 10 chips 111 connected in parallel to form a power extraction unit 114.
  • the length of the electrical connection line between the first chip array and the second chip array is greater than the length of the electrical connection line between adjacent chip 111 groups in each chip array, and the length of the signal line 116 between adjacent chip arrays is greater than the length of the signal line 116 between adjacent chip 111 groups in each chip array.
  • circuit board 110 and the working component 2100 of the above embodiment can adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the terms “installed”, “connected”, “connected”, “fixed” and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection
  • it can be a mechanical connection, an electrical connection, or a communication
  • it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • a first feature being “on” or “below” a second feature may include the first and second features being in direct contact, or the first and second features being in contact not directly but through another feature between them.
  • “Above”, “below” and “below” the second feature include the first feature being directly above and diagonally above the second feature, or simply means that the first feature is higher in level than the second feature.
  • “Below”, “below” and “below” the second feature include the first feature being directly above and diagonally above the second feature, or simply means that the first feature is lower in level than the second feature.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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Abstract

一种电路板（110），电路板（110）上设置有芯片阵列，芯片阵列包括多个取电单元（114），取电单元（114）包括至少一个芯片（111），其中，至少部分相邻取电单元（114）之间的距离不相等，从而有利于电路板（110）的散热、均温。

Description

电路板和工作组件
本申请要求于2022年10月20日提交中国专利局、申请号为202211291965.1、名称为“工作组件和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请要求于2022年11月11日提交中国专利局、申请号为202211415822.7、名称为“电路板和工作组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及散热技术领域，尤其涉及一种电路板和工作组件。
背景技术
通常，现有技术的电路板上仅设置单颗或较少数量的芯片，此时对于整个电路板的芯片散热性能和均温性能要求不高。且通常多颗芯片的情况下，芯片排布方式也不具备规律性。而对于具有较多芯片的电路板，需要具有较高的散热性能和均温性能。
发明内容
本申请实施例提供一种电路板和电子设备，以解决或缓解现有技术中的一项或更多项技术问题。
作为本申请实施例的一个方面，本申请实施例提供一种电路板，电路板上设置有芯片阵列，芯片阵列包括多个取电单元，取电单元包括至少一个芯片，其中，至少部分相邻取电单元之间的距离不相等。
作为本申请实施例的二个方面，本申请实施例提供一种电路板，电路板设置有芯片阵列，芯片阵列包括多个芯片及至少一个空缺位。
作为本申请实施例的三个方面，本申请实施例提供一种电路板，电路板上设置有多个芯片组，各芯片组包括至少一行芯片和/或至少一列芯片，至少部分相邻芯片组的间距，与任一芯片组内相邻芯片的间距不相等。
作为本申请实施例的四个方面，本申请实施例提供一种工作组件，包括电路板，散热器，散热器包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接。
上述概述仅仅是为了说明书的目的，并不意图以任何方式进行限制。除上述描述 的示意性的方面、实施方式和特征之外，通过参考附图和以下的详细描述，本申请进一步的方面、实施方式和特征将会是容易明白的。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本申请公开的一些实施方式，而不应将其视为是对本申请范围的限制。
图1A示出根据本申请一种实施例的电路板的结构示意图。
图1B示出根据本申请实施例一的电路板的结构示意图。
图2A示出根据本申请实施例二的电路板的结构示意图。
图2B示出了图2A所示的电路板的电流图。
图2C示出了图2A所示的电路板的信号图。
图3示出根据本申请实施例三的电路板的结构示意图。
图4示出根据本申请实施例四的电路板的结构示意图。
图5示出根据本申请实施例五的电路板的结构示意图。
图6A示出根据本申请实施例六的电路板的结构示意图。
图6B示出根据本申请实施例六的电路板的另一个结构示意图。
图7示出根据本申请实施例七的电路板的结构示意图。
图8示出根据本申请实施例八的电路板的结构示意图。
图9示出根据本申请实施例九的电路板的结构示意图。
图10示出根据本申请实施例十的电路板的结构示意图。
图11示出根据本申请实施例十一的电路板的结构示意图。
图12示出根据本申请实施例十二的电路板的结构示意图。
图13示出根据本申请实施例十三的电路板的结构示意图。
图14示出根据本申请实施例十四的电路板的结构示意图。
图15示出根据本申请实施例十五的电路板的结构示意图。
图16示出根据本申请实施例十六的电路板的结构示意图。
图17示出根据本申请实施例十七的电路板的结构示意图。
图18示出根据本申请实施例十八的电路板的结构示意图。
图19A示出根据本申请实施例十九的电路板的结构示意图。
图19B示出图19A所示的电路板的电流图。
图20示出根据本申请实施例二十的电路板的结构示意图。
图21A示出根据本申请实施例二十一的电路板的结构示意图。
图21B示出图21A所示的电路板的电流图；
图22示出根据本申请实施例的电子设备的结构示意图。
图23示出根据本申请实施例的工作组件的结构示意图。
附图标记：
110：电路板；111：芯片；113：空缺位；114：取电单元；115：电源线；116：
信号线；117：焊接盘；118：芯片组；119：第一电连接件；119’：第二电连接件；
2100：工作组件；2110：散热器；
3100：电子设备。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可认识到的那样，在不脱离本申请的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
现有技术中，芯片在电路板上的布置方案为单颗芯片布置或多颗芯片不均匀或不规则布置，其散热均温性不好。
图1A为本申请涉及的电路板110的结构示意图。如图1A所示，电路板110上的多个芯片阵列排布，且多个芯片111的行间距均相同，多个芯片111的列间距均相同。芯片阵列中的芯片总数较多，可以提升电路板110的计算能力，从而提升电路板110的整体性能，且阵列排布的方式能提升多个芯片111的散热均温性。
为了进一步提升多个芯片111的散热均温性，本申请公开以下实施例。
本申请实施例提供一种电路板110，电路板110上设置有芯片阵列，芯片阵列包括多个取电单元114，取电单元114包括至少一个芯片111，其中，至少部分相邻取电单元114之间的距离不相等。在本申请的描述中，“多个”的含义是两个或两个以上。取电单元114可以串联连接，取电单元114中的各芯片111可以并联连接。
例如，如图1B所示，芯片阵列包括40个串联连接的取电单元114，40个取电单元114串联连接。每个取电单元114中包括3个并联连接的芯片111，从而左边有21个取电单元114，右边有19个取电单元114。其中，从上到下数右边的第9个和第10个取电单元114之间的距离与其他相邻取电单元114之间的距离不相等。
也就是说，在图1B中，至少部分相邻取电单元114之间的距离不相等，类似情况也存在于图2A至图17以及图19A至图21B的电路板110中。
由此，距离不相等的相邻取电单元114之间形成了散热通道，有利于电路板110的散热。
在一种实施方式中，芯片阵列中的芯片尺寸相同，芯片阵列中芯片总数大于等于20个或50个。例如，在图1B的示例中，各芯片均为矩形，芯片阵列中的芯片总数为120个。因此，图1B中，芯片阵列中的芯片尺寸相同，芯片阵列中芯片总数大于等于20个或50个。类似情况也存在于图2A至图21B的电路板110中。
本实施例中，通过使芯片阵列中的芯片111尺寸相同，可以提升芯片111的通用性，方便加工；通过使芯片阵列中芯片111总数大于等于20个或50个，芯片阵列中的芯片总数较多，可以提升电路板110的计算能力，从而提升电路板110的整体性能。
在一种实施方式中，沿垂直于并联方向的方向或串联方向(例如，图1B中的上下方向)，至少部分相邻取电单元114之间的距离大于其他相邻取电单元114之间的距离。例如，在图1B的示例中，左3列即第一分布区的21个取电单元114均匀间隔设置，右3列即第二分布区从上到下数第9个和第10个取电单元114之间的距离大于其他相邻取电单元114之间的距离。这样，在上下方向上，可以根据相邻取电单元114之间的间距对第二分布区中的19个取电单元114进行分割，将19个取电单元114分为两个子区域，各子区域中的取电单元114可以等间距排布，两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片111的温度，进而减小子区域内多个芯片111之间的温差。
在一种实施方式中，参照图2A-图2C，沿垂直于并联方向的方向或串联方向，至少部分相邻取电单元114之间的电连接线长度长于其他相邻取电单元114之间的电连接线长度，其中，长度方向垂直于取电单元114的并联方向。其中，电连接线可以包括电源线115和/或信号线116。示例性地，结合图2A-图2C，在上下方向上，右侧第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距可以大于其他相邻取电单元114的间距，因而在上下方向上，右侧第7个取电单元114和第8个取电单元114之间的电连接线长度以及第12个取电单元114和第13个取电单元114之间的电连接线长度长于其他相邻取电单元114之间的电连接线长度；即代表相邻取电单元114之间存在较大的空缺以形成散热通道，形成了散热通道，有利于电路板110的散热。类似情况也存在于图1B、图3至图17以及图 19A至图21B的电路板110中。
进一步地，上述其他相邻取电单元114为同一行或同一列的相邻取电单元114。例如，在图2A-图2C的示例中，上述其他相邻取电单元114可以为芯片阵列中在垂直于取电单元114的并联方向上非边缘的取电单元114。例如，可以为右侧同一列设置的第1至7个取电单元114中相邻的取电单元114、右侧同一列设置的第8至12个取电单元114中相邻的取电单元114以及右侧同一列设置的第13至19个取电单元114中相邻的取电单元114。类似情况也存在于图1B、图3至图17以及图19A至图21B的电路板110中。
在一种实施方式中，沿散热方向，相邻取电单元114之间的距离增加，和/或相邻芯片111之间的距离增加。示例性地，结合图22，电路板110可以应用于电子设备3100例如计算设备中。电子设备3100内限定出散热风道，电路板110可以工作在散热风道内。电路板110的散热方向为散热风道的入风口到出风口的方向。其中，电路板110的散热源可以为风冷散热源(例如风扇)或液冷散热源。例如，散热方向为从左至右的方向。沿左右方向，左右两侧取电单元114之间的距离可以大于各取电单元114内相邻两列芯片之间的距离。当然，沿左右方向，左右两侧取电单元114之间的距离可以等于各取电单元114内相邻两列芯片之间的距离；又或者，沿左右方向，左右两侧取电单元114之间的距离可以小于各取电单元114内相邻两列芯片之间的距离；再或者，沿左右方向，多列芯片之间的距离可以逐渐增大或逐渐减小。
在一种实施方式中，在散热方向上，芯片阵列所占电路板110的矩形区域划分为多个分布区，至少两个分布区内的取电单元114数量不相等。
示例性地，结合图1B，在左右方向上，芯片阵列所占电路板110的矩形区域划分为两个分布区，即行芯片数最大的数值Y将芯片阵列等分为两个分布区，两个分布区分别为第一分布区(例如，图1B中的左三列芯片)和第二分布区(例如，图1B中的右三列芯片)，第一分布区和第二分布区内的取电单元114数量不相等。具体地，第一分布区包括呈21行3列排布的63个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括21个取电单元114。第二分布区包括呈19行3列排布的57个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括19个取电单元114。当然，行芯片最大的数值Y还可以将芯片阵列划分为大于两个分布区。本申请对分布区的数量不作限定。
进一步地，当芯片行方向为散热方向时，各分布区的芯片列数相同；当芯片列方向为散热方向时，各分布区的芯片行数相同。例如，在图1B的示例中，芯片行方向为 散热方向，第一分布区和第二分布区的列数均为3列。类似情况也存在于图1B、图3至图17中。
在一种实施方式中，沿散热方向，多个分布区内的取电单元114数量减小。示例性地，如图1B所示，第一分布区中取电单元114的数量为21，第二分布区中取电单元114的数量为19。当然，本申请不限于此，在分布区的取电单元114数量大于2的情况下，相邻分布区内取电单元114的数量并非逐一减小，允许若干个相邻分布区内取电单元114的数量沿散热方向增加，只要总体上相邻分布区的间距沿左右方向为增大趋势即可。以分布区数量为6进行说明。沿左右方向，多个分布区的取电单元114数量可以分别为15，14，13，12，11，10；或者，多个分布区的取电单元114数量可以分别为12，12，11，11，10，10；又或者，多个分布区的取电单元114数量可以分别为11，10，10，10，10，10；再或者，多个分布区内取电单元114的数量可以分别为16，15，13，14，12，10。这样，靠近入风口的前半部分芯片总数大于靠近出风口的后半部分芯片总数，可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
在一种实施方式中，芯片阵列所占电路板110的矩形区域划分为多个子区域。
可以理解为因为存在芯片空缺位113从而将芯片阵列划分为多个子区域，使得至少部分相邻子区域的间距大于或等于容纳一个芯片所需的间距。
如图1B所示，芯片阵列中右侧三列芯片第9行至第10行之间存在芯片空缺位113，从而将左侧三列芯片划分为一个子区域，将右侧三列芯片第1行至第9行划分为一个子区域，将右侧三列芯片第10行至第19行划分为一个子区域，即芯片空缺位113将芯片阵列划分为3个子区域。
如图2A所示，芯片阵列中右侧三列芯片第7行至第8行之间、第12行至第13行之间存在芯片空缺位113，从而将左侧三列芯片划分为一个子区域，将右侧三列芯片第1行至第7行划分为一个子区域，将右侧三列芯片第8行至第12行划分为一个子区域，将右侧三列芯片第13行至第19行划分为一个子区域，即芯片空缺位113将芯片阵列划分为4个子区域。
如图6A所示，芯片阵列中左侧三列芯片第10行至第11行之间存在芯片空缺位113，芯片阵列中右侧三列芯片第7行至第8行之间、第12行至第13行之间存在芯片空缺位113，从而将左侧三列芯片第1行至第10行划分为一个子区域，将左侧三列芯片第11行至第20行划分为一个子区域，将右侧三列芯片第1行至第7行划分为一个子区域，将右侧三列芯片第8行至第12行划分为一个子区域，将右侧三列芯片第13行至第19 行划分为一个子区域，即芯片空缺位113将芯片阵列划分为5个子区域。
子区域由至少一个取电单元114构成，部分相邻两个子区域之间的距离大于子区域内相邻取电单元114之间的距离，取电单元114包括至少一个芯片111。当取电单元114包括多个芯片111时，取电单元114中的芯片111同处一行或一列且并联连接。各子区域的芯片并联方向相同，沿垂直芯片并联方向的方向，至少部分相邻子区域的间距，与任一子区域内相邻取电单元114的间距不相等。子区域包括多个取电单元114，多个取电单元114串联连接。各子区域的芯片串联方向相同，沿芯片串联方向，至少部分相邻子区域的间距，与任一子区域内相邻取电单元114的间距不相等。子区域之间的芯片111可沿行列方向等间距或不等间距或间距递增或间距递减布置，但是至少部分相邻子区域之间的间距会因芯片空缺位113的存在，与子区域内包含的相邻芯片间距不同。需要说明的是，上述实施例中芯片111的电连接方式，并不仅限于串联和并联，芯片之间还可以是串联和并联组合等其他电连接方式。
可选的，至少两个子区域的取电单元114数量可以相等也可以不相等。其中，芯片阵列的列芯片数最大的数值为X，基于X可以将芯片阵列所占电路板区域分为多个子区域。在图1B的示例中，X为21，基于X，可以将第二分布区中第1至9个取电单元114分为一个子区域，该子区域包括9行3列排布的27个芯片；将第10至19个取电单元114分为另一个子区域，该子区域包括呈10行3列排布的30个芯片。由此，在上下方向上，对第二分布区中的19个取电单元114进行分割，将19个取电单元114分为两个子区域，各子区域中的取电单元114可以等间距排布，两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片的温度，进而减小子区域内多个芯片111之间的温差。
当然，本申请不限于此，芯片阵列所占电路板区域在垂直散热方向上的高度为H，还可以基于H将芯片阵列所占电路板区域分为多个子区域。
进一步地，多个子区域包括两个端部区域和一个中间区域，两个端部区域及一个中间区域高度均为H/3。例如，此时各端部区域和中间区域的行数量可以相等。上述区域高度不仅仅局限于H/3，基于高度为H，还可将端部区域设定为H/4，中间区域高度H/2，这里本申请不做具体限定，根据设计需求将取电单元114划分至不同的子区域即可，保证至少部分相邻取电单元114之间的距离不相等即可，以实现形成散热通道，有利于电路板110的散热。
在一种实施方式中，如图2A-图2C，多个子区域包括两个端部区域和一个中间区 域，端部区域的取电单元114数量大于中间区域的取电单元114数量。例如，在图2A中，基于第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距，可以将第二分布区中第1至7个取电单元114分为第一个子区域，该子区域包括呈7行3列排布的21个芯片111；将第8至12个取电单元114分为第二个子区域，该子区域包括呈5行3列排布的15个芯片111；将第13至19个取电单元114分为第三个子区域，该子区域同样包括呈7行3列排布的21个芯片111。端部区域的取电单元114数量为7，中间区域的取电单元114数量为5。
在一种实施方式中，如图2A-图2C所示，由中间区域向端部区域，取电单元114的数量增加。例如，在图2A中，端部区域的取电单元114数量为7，中间区域的取电单元114数量为5。端部区域的芯片数量分别为21个，中间区域的芯片数量为15个。由此，由于在电路板110应用于电子设备3100的情况下，两端区域的芯片与外部环境距离较近，散热更好，通过使端部区域布置数量较多的芯片111，且中间区域布置数量较少的芯片111，可以有效降低中间区域的芯片温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
在一种实施方式中，多个子区域包括两个端部区域和一个中间区域，端部区域对应的芯片数量大于或等于中间区域芯片总数。例如，在图2A中，端部区域的芯片即为第一个子区域中的芯片111以及第三个子区域中的芯片111，中间区域的芯片111即为第二个子区域中的芯片111。第一个子区域和第三个子区域分别包括21个芯片111，第二个子区域包括15个芯片111，端部区域对应的芯片数量大于中间区域芯片总数。由此，可以进一步降低中间区域的芯片温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
在一种实施方式中，端部区域的平均芯片间距小于中间区域的平均芯片间距。如此设置，由于在电路板110应用于电子设备3100的情况下，两端区域的芯片111与外部环境距离较近，散热更好，通过使端部区域的芯片111较密，且中间区域的芯片111较疏，同样可以有效降低中间区域的芯片温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
在一种实施方式中，如图5或图9或图14或图15所示，两个端部区域包括第一端部区域和第二端部区域，第一端部区域的取电单元114数量小于第二端部区域的取电单元114数量，其中，在电路板110的垂直放置状态下，第一端部区域靠近电路板110的顶部，第二端部区域靠近电路板110的底部。这样，由于靠近顶部设置的端部区 域更够更好地与外部环境进行热交换，通过上述设置，可以减小第二端部区域的芯片111的总发热量，从而可以有效降低第二端部区域的芯片温度，进而减小第一端部区域的芯片111以及第二端部区域的芯片111的温差，提升电路板110散热效果。
此外，因为烟囱效应，部分密度较轻的热风是流向电路板110的上部，所以减小上部的芯片111以便于减小发热量同时留出更多的散热区域，使得上部区域更够更好地与外部环境进行热交换，进而减小上部区域的芯片111以及下部区域的芯片111的温差，提升电路板110散热效果。
在一种实施方式中，相邻取电单元114之间设置有金属件，沿串联方向，至少部分相邻取电单元114之间的金属件长度长于其他相邻取电单元114，其中，长度方向垂直于取电单元114的并联方向。示例性地，结合图2A-图2C，长度方向即为上下方向。右侧第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距可以大于其他相邻取电单元114的间距，因而在上下方向上，右侧第7个取电单元114和第8个取电单元114之间的金属件长度以及第12个取电单元114和第13个取电单元114之间的金属件长度长于其他相邻取电单元114之间的金属件长度。类似情况也存在于图1B、图3至图17以及图19A至图21B的电路板110中。类似地，上述其他相邻取电单元114为同一行或同一列的相邻取电单元114；在与并联方向垂直的方向上，其他相邻取电单元114为芯片阵列中非边缘的取电单元114。
上述布置，金属件长度增加，使得取电单元114避让出空间而形成散热风道，两个取电组之间的间距可以大于各取电组中相邻取电单元114的间距，从而使得各取电组内位于串联方向两端的芯片与中心位置的芯片之间的距离较小，有效降低各取电组内位于中心位置的芯片的温度，进而减小取电组内多个芯片之间的温差。
可选地，金属件可以为铜片或铝片，焊接在电路板110上，用于对所连接的相邻两个工作芯片进行散热，并降低所连接的相邻两个工作芯片之间的压降。由此，提升了工作芯片的工作稳定性和可靠性。示例性地，金属件的厚度小于或者等于芯片的厚度。其中，金属件的厚度方向和芯片的厚度方向为垂直于电路板110的方向。
在一种实施方式中，如图1B所示，芯片行方向可以为多个芯片111的并联方向(例如，图1B中的左右方向)。类似情况也存在于图2A至图17的电路板110中。当然，芯片行方向也可以垂直芯片111的并联方向，(例如，图19A中的左右方向)。
在一种实施方式中，芯片行方向为散热方向(例如，图1B中的左右方向)，此时芯片列方向垂直于散热方向。类似情况也存在于图2A至图17的电路板110中。
在一种实施方式中，芯片阵列的并联方向为散热方向(例如，图1B中的左右方向)。 类似情况也存在于图2A至图17的电路板110中。
在一种实施方式中，芯片阵列的各芯片111之间的工作温差范围是0～10℃(包括端点值)。例如，在散热源为风扇的情况下，当风扇的转速为4000转/分钟时，各芯片111之间的温差可以为8～10℃(包括端点值)。当然，上述工作温差范围不仅仅只限定于0～10℃。
在一种实施方式中，电路板上芯片最高温与最低温的温差范围是5-12℃(包括端点值)。只要本申请能相对图1A中的取电单元114布置形式，实现降低多个芯片之间的温差即可，比如图1A中的布置形式芯片的温差为20～40℃(包括端点值)，而本申请图1B至图21B的取电单元114布置形式，芯片温差为10～20℃(包括端点值)。
在一种实施方式中，每行芯片或每列芯片的中心在同一直线上。例如，在图1B的示例中，芯片阵列中的120个芯片呈21行6列排布，各行芯片的中心在一条直线上，各列芯片的中心在一条直线上。其中，前3列芯片的行间距相同，后3列芯片的第10行和第11行缺失。前3列芯片的数量为63个，后3列芯片的数量为57个。芯片阵列的行方向为可以为散热方向。这样，靠近入风口的前半部分芯片总数大于靠近出风口的后半部分芯片总数，入风口处的芯片111的数量较多，可以增大入风口处的芯片111的发热量，出风口处的芯片111的数量较少，可以减小出风口处的芯片111的发热量，从而可以进一步降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。类似情况也存在于图2A至图21B的电路板110中。
在一种实施方式中，芯片阵列中芯片数量及空缺位113数量的总数为X*Y个。例如，在图1B的示例中，X为21，Y为6。芯片阵列中芯片数量及空缺位113数量的总数为126个。其中，芯片阵列的芯片数量为120个，空缺位113的数量为6个。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列划分为至少两个分布区。
示例性地，在若Y为偶数，芯片阵列前Y/2列的总芯片数量A，大于芯片阵列后Y/2列的总芯片数量B。例如，在图1B中，Y为偶数6，芯片阵列前3列的总芯片数量为63个，芯片阵列后3列的总芯片数量为57个。
若Y为奇数，芯片阵列前(Y-1)/2列的总芯片数量C，大于芯片阵列后(Y-1)/2列的总芯片数量D。例如，以Y为7为例进行说明。此时芯片阵列前3列的总芯片数量C大于芯片阵列后3列的总芯片数量D。这样，靠近入风口的前半部分芯片总数大于靠近出风口的后半部分芯片总数，可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
或者，若Y为偶数，芯片阵列前Y/2列及对应列的总芯片数量A还可以小于芯片 阵列后Y/2列及对应列的总芯片数量B。例如，在图17中，Y为偶数6，芯片阵列前3列的总芯片数量为57个，芯片阵列后3列的总芯片数量为63个。
若Y为奇数，芯片阵列前(Y-1)/2列及对应列的总芯片数量C，还可以小于芯片阵列后(Y-1)/2列及对应列的总芯片数量D。例如，以Y为7为例进行说明。此时芯片阵列前3列的总芯片数量C可以小于芯片阵列后3列的总芯片数量D。
当然，本申请不限于此，若Y为偶数，芯片阵列前Y/2列及对应列的总芯片数量A，还可以等于芯片阵列后Y/2列及对应列的总芯片数量B。例如，在图12的示例中，Y为偶数6，芯片阵列前3列的总芯片数量为57个，芯片阵列后3列的总芯片数量为57个。
若Y为奇数，芯片阵列前(Y-1)/2列及对应列的总芯片数量C，等于芯片阵列后(Y-1)/2列及对应列的总芯片数量D。例如，以Y为7为例进行说明。此时芯片阵列前3列的总芯片数量C可以等于芯片阵列后3列的总芯片数量D。
本申请还提供了一种工作组件2100，包括电路板110和散热器2110。其中，电路板110为上述任一实施方式中的电路板110，散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接。
示例性地，散热器2110可以为风冷式散热器2110或液冷式散热器2110。散热器2110可以位于电路板110的设置有工作芯片的一侧，用于为电路板110进行散热。散热器2110也可以位于电路板110的未设置有芯片的一侧。或者，在电路板110的两侧均设置芯片，且电路板110的两侧均分别设置有散热器2110。
在一种实施方式中，第二面设置有多个凸台，各凸台与各行取电单元114或各列取电单元114对应设置。这样，取电单元114中的芯片工作过程中产生的热量能够有效通过凸台传导至散热器2110，从而提升散热效果。
或者，在另一种实施方式中，第二面设置有多个凸台，至少部分凸台还可以设置于至少部分相邻取电单元114之间的对应位置。例如，在图3中，电路板110上的117个芯片呈多行排布，行方向平行于散热风道的入风口到出风口的方向。第6行、第11行和第16行芯片的数量分别为3个，其他各行芯片的数量为6个，因而第6行、第11行和第16行芯片的数量小于其他行芯片的数量。其中，至少部分凸台可以设置于第二分布区中第5个取电单元114和第6个取电单元114的对应位置、第9个取电单元114和第10个取电单元114的对应位置以及第13个取电单元114和第14个取电单元114的对应位置
本申请实施例提供一种电路板110，电路板110上设置有芯片阵列，芯片阵列包括 多个芯片111及至少一个空缺位113。在本申请的描述中，“多个”的含义是两个或两个以上。
其中，芯片阵列可以包含串联和并联两种芯片111连接方式。例如，如图1B所示，芯片阵列包括120个芯片111和6个空缺位113。其中，芯片阵列中的左侧三列包括63个芯片111，左侧三列未设置空缺位113。芯片阵列中右侧三列包括57个芯片111，右侧三列从上到下数右边的第9行芯片111和第10行芯片111之间设置有2行共6个空缺位113。
也就是说，在图1B中，芯片阵列包括多个芯片111及至少一个空缺位113，类似情况也存在于图2A至图21B的电路板110中。由此，芯片阵列的空缺位113处形成了散热通道，有利于电路板110的散热。
在一种实施方式中，芯片阵列中的芯片111尺寸相同，芯片阵列中芯片111总数大于等于20个或50个。例如，在图1B的示例中，各芯片111均为矩形，芯片阵列中的芯片111总数为120个。因此，图1B中，芯片阵列中的芯片111尺寸相同，芯片阵列中芯片111总数大于等于20个或50个。类似情况也存在于图2A至图21B的电路板110中。
本实施例中，通过使芯片阵列中的芯片111尺寸相同，可以提升芯片111的通用性，方便加工；通过使芯片阵列中芯片111总数大于等于20个或50个，芯片阵列中的芯片111总数较多，可以提升电路板110的计算能力，从而提升电路板110的整体性能。
在一种实施方式中，空缺位113的尺寸大于或等于芯片阵列中的单颗芯片111尺寸，此时空缺位113对应的空间可以容纳至少一个芯片111。其中，“空缺位113的尺寸”包括空缺位113的长度和/或宽度。如此设置，芯片阵列的空缺位113处的散热通道尺寸较大，可以减小风阻，提升散热效果。
在一种实施方式中，芯片阵列中至少部分相邻芯片111间距不相等。
在一个示例中，至少一个空缺位113设置于芯片阵列的行方向上，使芯片阵列中至少一行芯片111中存在不相等的相邻芯片111间距。例如，结合图19A，行方向为左右方向。芯片阵列包括76个芯片111和4个空缺位113。其中，4个空缺位113分别位于第3行第3列、第4行第3列、第5行第3列以及第6行第3列。从而，第3行中从右往左数第2个芯片111和第3个芯片111之间的距离大于其余相邻芯片111之间的距离；第4行中从右往左数第2个芯片111和第3个芯片111之间的距离大于其余相邻芯片111之间的距离；第5行中从右往左数第2个芯片111和第3个芯片111 之间的距离大于其余相邻芯片111之间的距离；第6行中从右往左数第2个芯片111和第3个芯片111之间的距离大于其余相邻芯片111之间的距离。
在另一个示例中，至少一个空缺位113位于芯片阵列的列方向上，使芯片阵列中至少一列芯片111中存在不相等的相邻芯片111间距。例如，如图18所示，行方向为左右方向。芯片阵列包括123个芯片111和3个空缺位113。其中，3个空缺位113分别位于从左往右数第6列第10-12行。从而，第6行中从上往下数第9个芯片111和第10个芯片111之间的距离大于其余相邻芯片111之间的距离。
在一种实施方式中，芯片阵列包括多个取电单元114，取电单元114内的芯片111连接方式为并联。例如，如图1B所示，芯片阵列包括40个取电单元114，40个取电单元114串联连接。每个取电单元114中包括3个并联连接的芯片111，从而左边有21个取电单元114，右边有19个取电单元114。其中，从上到下数右边的第9个和第10个取电单元114之间的距离与其他相邻取电单元114之间的距离不相等。如图21B所示，芯片阵列包括10个取电单元114，10个取电单元114串联连接。每个取电单元114中包括10个并联连接的芯片111，从而上侧有5个取电单元114，下侧有5个取电单元114。其中，从上到下数第5个和第6个取电单元114之间的距离与其他相邻取电单元114之间的距离不相等。
在一种实施方式中，空缺位113的总数量是一个取电单元114中所包含芯片111数量的整数倍。示例性地，芯片阵列中的芯片111总数可以是取电单元114的整数倍。例如，如图1B所示，芯片阵列包括120个芯片111和6个空缺位113，一个取电单元114中所包含芯片111数量为3，空缺位113的总数量是一个取电单元114中所包含芯片111数量的2倍。如图21B所示，芯片阵列包括100个芯片111和10个空缺位113，一个取电单元114中所包含芯片111数量为10，空缺位113的总数量是一个取电单元114中所包含芯片111数量的1倍。
在一种实施方式中，在垂直芯片阵列的芯片111并联方向上，与空缺位113前后相邻的两个取电单元114之间的电连接线长度，长于其他相邻取电单元114间的电连接线长度，其中，长度方向垂直于芯片阵列的芯片111并联方向。例如，结合图2A-图2C，芯片111并联方向为左右方向，垂直芯片阵列的芯片111并联方向为上下方向。其中，电连接线可以包括电源线115和/或信号线116。示例性地，结合图2A-图2C，在上下方向上，右侧第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距可以大于其他相邻取电单元114的间距，因而在上下方向上，右侧第7个取电单元114和第8个取电单元114之间的电连接线长 度以及第12个取电单元114和第13个取电单元114之间的电连接线长度长于其他相邻取电单元114之间的电连接线长度。类似情况也存在于图1B、图3至图17以及图19A至图21B的电路板110中。
进一步地，上述其他相邻取电单元114具有相同行或相同列。例如，在图2A-图2C的示例中，上述其他相邻取电单元114可以为芯片阵列中在垂直于取电单元114的并联方向上非边缘的取电单元114。例如，可以为右侧同一列设置的第1至7个取电单元114中相邻的取电单元114、右侧同一列设置的第8至12个取电单元114中相邻的取电单元114以及右侧同一列设置的第13至19个取电单元114中相邻的取电单元114。类似情况也存在于图1B、图3至图17以及图19A至图21B的电路板110中。
在一种实施方式中，芯片阵列设置为X*Y，芯片阵列的列方向上，列芯片数最大的数值为X，芯片阵列的行方向上，行芯片数最大的数值为Y。其中，芯片阵列中芯片111数量及空缺位113数量的总数为X*Y个。例如，在图1B的示例中，X为21，Y为6。芯片阵列中芯片111数量及空缺位113数量的总数为126个。其中，芯片阵列的芯片111数量为120个，空缺位113的数量为6个。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列划分为至少两个部分，每个部分的芯片111总数不完全相等。
示例性地，结合图1B，行芯片数最大的数值6将芯片阵列等分为两个部分，两个部分分别为第一部分(例如，图1B中的左三列芯片111)和第二部分(例如，图1B中的右三列芯片111)，第一部分和第二部分内的取电单元114数量不相等。具体地，第一部分包括呈21行3列排布的63个芯片111，第一部分中每行的3个芯片111并联连接，构成1个取电单元114，因而第一部分包括21个取电单元114。第二部分包括呈19行3列排布的57个芯片111，第二部分中每行的3个芯片111并联连接，构成1个取电单元114，因而第二部分包括19个取电单元114。当然，行芯片111最大的数值Y还可以将芯片阵列划分为大于两个部分。本申请对部分的数量不作限定。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列划分为至少两个部分，沿散热方向，每个部分的芯片111总数减少。示例性地，电路板110可以应用于电子设备3100例如计算设备中。电子设备3100内限定出散热风道，电路板110可以工作在散热风道内。电路板110的散热方向为散热风道的入风口到出风口的方向。其中，电路板110的散热源可以为风冷散热源(例如风扇)或液冷散热源。例如，在图1B中，散热方向为从左至右的方向。沿从左至右的方向，第一部分中芯片111总数为63，第二部分中芯片111总数为57，即每个部分的芯片111总数减少。
当然，本申请不限于此，在部分的数量大于2的情况下，相邻部分内芯片111总数不仅限于逐一减小，允许若干个相邻部分内芯片111总数沿散热方向增加，只要总体上部分内芯片111总数沿左右方向为减小趋势即可。以部分数量为6进行说明。沿左右方向，多个部分内芯片111总数可以分别为25，24，23，22，21，20；或者，多个部分内芯片111总数可以分别为22，22，21，21，20，20；又或者，多个部分的取电单元114数量可以分别为21，20，20，20，20，20；再或者，多个部分内取电单元114的数量可以分别为26，25，23，24，22，20。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列划分为至少两个部分，每个部分的行或列的数量不完全相等和/或每个部分芯片111布局非对称。例如，在图1B中，行芯片数最大的数值Y为6，行芯片数最大的数值Y将芯片阵列划分为第一部分和第二部分。其中，第一部分包括呈21行3列排布的63个芯片111，第二部分包括呈19行3列排布的57个芯片111，第一部分和第二部分的行数量不相等，且每个部分芯片111布局非对称。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，前半部分的列平均间距小于后半部分的列平均间距。需要说明的是，上述“等分”是在数量上，对芯片111的列数等分；在尺寸上不一定对电路板110等分。在Y为偶数时，如图1B所示，Y为偶数6，此时前半部分和后半部分的列数分别为Y/2＝3。当Y为奇数时，前半部分和后半部分的芯片111列数可以分别为(Y-1)/2，例如在Y为7的情况下，前半部分和后半部分的芯片111列数分别为3。
由此，由于散热方向的前半部分靠近入风口设置，环境温度相对较低，散热方向的后半部分靠近出风口设置，环境温度相对较高，通过使前半部分的列平均间距小于后半部分的列平均间距，靠近出风口设置的芯片111密度可以相对较小，从而可以减小靠近出风口设置的芯片111的总发热量，进而减小前半部分芯片111和后半部分芯片111的温差。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，前半部分与后半部分的芯片111行数和/或芯片111数量和/或空缺位113数量不相等。例如，在图1B的示例中，前半部分即为第一部分，后半部分即为第二部分，第一部分包括呈21行3列排布的63个芯片111，第一部分的空缺位113数量为零。第二部分包括呈19行3列排布的57个芯片111，第一部分的空缺位113数量为6。因此， 前半部分与后半部分的芯片111行数不同、芯片111数量不同且空缺位113数量不相等。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，前半部分大于后半部分的芯片111行数和/或芯片111数量。例如，在图1B的示例中，第一部分包括呈21行3列排布的63个芯片111，第二部分包括呈19行3列排布的57个芯片111。因此，前半部分大于后半部分的芯片111行数，且前半部分大于后半部分的芯片111数量。这样，可以进一步减小靠近出风口设置的芯片111的总发热量，进而减小前半部分芯片111和后半部分芯片111的温差。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，前半部分等于后半部分的芯片111行数和/或芯片111数量。例如，如图12所示，第一部分包括呈19行3列排布的57个芯片111，第二部分包括呈19行3列排布的57个芯片111。因此，前半部分等于后半部分的芯片111行数，且前半部分等于后半部分的芯片111数量。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，前半部分小于或等于后半部分的空缺位113数量。例如，在图8的示例中，第一部分包括60个芯片111和3个空缺位113，第二部分包括54个芯片111和9个空缺位113。因此，前半部分小于后半部分的空缺位113数量。
在一种实施方式中，如图9和图12所示，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，前半部分与后半部分至少部分行空缺位113在同一直线上。例如，图9中，第一部分中的第11行包括3个空缺位113。第二部分中的第6行、第11行和第17行分别包括3个空缺位113。其中，第一部分中空缺位113与第二部分中的第11行空缺位113在同一直线上。图12中，第一部分中的第8行和第14行分别包括3个空缺位113。第二部分中的第8行和第14行分别包括3个空缺位113。其中，第一部分中的第8行空缺位113与第二部分中的第8行空缺位113在同一直线上，且第一部分中的第14行空缺位113与第二部分中的第14行空缺位113在同一直线上。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，前半部分与后半部分至少部分行空缺位113不在同一直线上。例如，图9中，第一部分中的第11行包括3个空缺位113。第二部分中的第6行、第11行和第17行分别包括3个空缺位113。其中，第一部分中空缺位113与第二部分中的第11行空缺位113在同一直线上，第一部分中空缺位113与第二部分中的第6行和第17行不在同一直线上。图6A中，第一部分中的第11行包括3个空缺位113。第二部分中的第8行 和第14行分别包括3个空缺位113。其中，第一部分中空缺位113与第二部分中空缺位113均不在同一直线上。
沿散热方向，空缺位113位于芯片阵列的上边缘和/或下边缘。
在一种实施方式中，如图10和图11所示，行芯片数最大的数值Y将芯片阵列等分为两个部分，沿散热方向，空缺位113位于前半部分的上边缘和/或下边缘。其中，“前半部分的上边缘”指的是前半部分在垂直于散热方向上的上边缘；“前半部分的下边缘”指的是前半部分在垂直于散热方向上的下边缘。
例如，在图10的示例中，前半部分包括一行空缺位113，一行空缺位113位于前半部分的上边缘。在图11的示例中，前半部分包括两行空缺位113，两行空缺位113分别位于前半部分的上边缘和下边缘。如此设置，空缺位113可以形成风道，有利用芯片111的散热，进一步提升散热效果。
在一种实施方式中，芯片阵列所占电路板110区域分为两端及中间三个区域。例如，在图2A中，基于第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距，可以将第二部分中第1至7个取电单元114分为第一个子区域，该子区域包括呈7行3列排布的21个芯片111；将第8至12个取电单元114分为第二个子区域，该子区域包括呈5行3列排布的15个芯片111；将第13至19个取电单元114分为第三个子区域，该子区域同样包括呈7行3列排布的21个芯片111。端部区域的取电单元114数量为7，中间区域的取电单元114数量为5。
在一种实施方式中，两端区域对应的芯片111总数大于或等于中间区域芯片111总数。例如，在图2A中，将第二部分中第1至7个取电单元114分为第一个子区域，该子区域包括呈7行3列排布的21个芯片111；将第8至12个取电单元114分为第二个子区域，该子区域包括呈5行3列排布的15个芯片111；将第13至19个取电单元114分为第三个子区域，该子区域同样包括呈7行3列排布的21个芯片111。其中，第一个子区域和第二个子区域为两端区域，第二个子区域为中间区域。因此，两端区域对应的芯片111总数大于中间区域芯片111总数。
本实施例中，由于在电路板110应用于电子设备3100的情况下，两端区域的芯片111与外部环境距离较近，散热更好，通过使端部区域布置数量较多的芯片111，且中间区域布置数量较少的芯片111，可以有效降低中间区域的芯片111温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
在一种实施方式中，两端区域芯片111的行平均间距小于中间区域芯片111的行平均间距。如此设置，由于在电路板110应用于电子设备3100的情况下，两端区域的芯片111与外部环境距离较近，散热更好，通过使两端区域芯片111的行平均间距小于中间区域芯片111的行平均间距，同样可以有效降低中间区域的芯片111温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
在一种实施方式中，将芯片阵列所占电路板110区域分为两端及中间三个区域，包括：芯片阵列的列芯片数最大的数值为X，基于X将芯片阵列所占电路板110区域分为两端及中间三个区域。例如，结合图1B，以X(即21)为分割依据，在一种实施例中，分割方式为平均分割，将电路板110从上至下分割为三部分，一列中的7个芯片111对应分割为一部分，则第一部分的芯片111总数为42个，第二部分的芯片111总数为36个，第三部分的芯片111总数为42个。靠近电路板110两端的第一部分(42个)或第三部分的芯片111总数(42个)，大于中间第二部分的芯片111数量(36个)；或者，结合图1B，分割方式为使两端区域的芯片111数量大于中间区域的芯片111数量，例如，可以将电路板110从上至下分割为三部分，一列中自上而下的8个芯片111为一部分、5个芯片111为一部分、8个芯片111为一部分。则第一部分的芯片111总数为48个，第二部分的芯片111总数为24个，第三部分的芯片111总数为个18。
当然，本申请不限于此，在另一种实施方式中，将芯片阵列所占电路板110区域分为两端及中间三个区域，包括：芯片阵列所占电路板110区域在垂直散热方向上的高度为H；基于H将芯片阵列所占电路板110区域分为两端及中间三个区域。例如，在分割方式为平均分割的情况下，两个端部区域及一个中间区域高度均为H/3。
需要说明的是，将芯片阵列所占电路板110区域可分为多个区域，可根据实际情况来划分，不仅限于上述所提到的三个区域。
本领域技术人员可以理解的是，分割方式不限于上述记载，当第一发热列芯片111总数为奇数或者偶数时，可以灵活选择分割的方式。当然，也可以以电路板110排布芯片111的边沿，所形成的整体面积为基准，对其进行分割划分，可以为平均分割，当然也可以按其他比例进行分割，以使得每一部分的芯片111总数符合预设分布要求。
总之，芯片111的排布方式，可以结合风道中各个位置的散热情况而设置。例如入风口环境温度低，整体散热效率高，则可以多布置芯片111数量，出风口环境温度高，整体散热效率低，则可以少布置芯片111数量，靠近出风口芯片111总数小于入风口芯片111总数。同时，电路板110的上下两端，与风的方向垂直的方向上，两端 的温度低于电路板110中心的温度，则两端可以多布置芯片111，中心位置少布置芯片111，两端芯片111总数大于中心芯片111总数，也可以分成两部分后，下半部分的芯片111总数大于上半部分的芯片111总数。这与通常改变散热器2110的热阻实现均温，是完全不同的设计思路。
在一种实施方式中，两个端部区域包括第一端部区域和第二端部区域，第一端部区域的芯片111数量小于第二端部区域的芯片111数量，其中，在电路板110的垂直放置状态下，第一端部区域靠近电路板110的顶部，第二端部区域靠近电路板110的底部。这样，由于靠近顶部设置的端部区域更够更好地与外部环境进行热交换，通过上述设置，可以减小第二端部区域的芯片111的总发热量，从而可以有效降低第二端部区域的芯片111温度，进而减小第一端部区域的芯片111以及第二端部区域的芯片111的温差，提升电路板110散热效果。
在一种实施方式中，在垂直芯片阵列的芯片111并联方向上，芯片阵列所占电路板110区域分为两端及中间三个区域。例如，在图2A中，基于第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距，可以将第二部分中第1至7个取电单元114分为第一个子区域，该子区域包括呈7行3列排布的21个芯片111；将第8至12个取电单元114分为第二个子区域，该子区域包括呈5行3列排布的15个芯片111；将第13至19个取电单元114分为第三个子区域，该子区域同样包括呈7行3列排布的21个芯片111。端部区域的取电单元114数量为7，中间区域的取电单元114数量为5。
在一种实施方式中，各区域内对应芯片111的行数相同或列数相同。例如，当芯片111行方向为散热方向时，各部分的芯片111列数相同；当芯片111列方向为散热方向时，各部分的芯片111行数相同。例如，在图1B的示例中，芯片111行方向为散热方向，第一部分和第二部分的列数均为3列。类似情况也存在于图1B、图3至图17中。
在一种实施方式中，至少两个区域对应的取电单元114数量不相等。例如，在图2A的示例中，将第二部分中第1至7个取电单元114分为第一个子区域，该子区域包括呈7行3列排布的21个芯片111；将第8至12个取电单元114分为第二个子区域，该子区域包括呈5行3列排布的15个芯片111；将第13至19个取电单元114分为第三个子区域，该子区域同样包括呈7行3列排布的21个芯片111。端部区域的取电单元114数量为7，中间区域的取电单元114数量为5。
在一种实施方式中，各区域的取电单元114数量由中间向两端区域增加。例如， 在图2A中，端部区域的取电单元114数量为7，中间区域的取电单元114数量为5。由此，由于在电路板110应用于电子设备3100的情况下，两端区域的芯片111与外部环境距离较近，散热更好，通过使端部区域布置数量较多的芯片111，且中间区域布置数量较少的芯片111，可以有效降低中间区域的芯片111温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
在一种实施方式中，每个空缺位113分别对应一个焊接盘117。例如，空缺位113可以对应设置导电金属件，焊接盘117用于焊接导电金属件。
可选地，导电金属件可以为铜片或铝片，焊接在焊接盘117上，用于对所连接的相邻两个工作芯片111进行散热，并降低所连接的相邻两个工作芯片111之间的压降。由此，提升了工作芯片111的工作稳定性和可靠性。示例性地，导电金属件的厚度小于或者等于芯片111的厚度。其中，导电金属件的厚度方向和芯片111的厚度方向为垂直于电路板110的方向。
在一种实施方式中，多个连续的空缺位113上不能共用同一个导电金属件。例如，每个空缺位113可以分别对应一个金属件。
在一种实施方式中，在芯片阵列所占电路板110区域内，在垂直芯片阵列的芯片111并联方向上，与空缺位113前后相邻的两个芯片111之间的金属件长度，长于未间隔空缺位113的相邻芯片111间设置的金属件长度，其中，长方向与并联方向垂直。示例性地，上述未间隔空缺位113的相邻芯片111可以为同一行或同一列，未间隔空缺位113的相邻芯片111，在垂直芯片阵列的芯片111并联方向上，为芯片阵列中非边缘的芯片111。结合图2A-图2C，长度方向即为上下方向，上述未间隔空缺位113的相邻芯片111为同一列。右侧第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距可以大于其他相邻取电单元114的间距，因而在上下方向上，右侧第7个取电单元114和第8个取电单元114之间的金属件长度以及第12个取电单元114和第13个取电单元114之间的金属件长度长于其他相邻取电单元114之间的金属件长度。类似情况也存在于图1B、图3至图17以及图19A至图21B的电路板110中。
在一种实施方式中，在芯片阵列所占电路板110区域内，在垂直芯片阵列的芯片111并联方向上，与空缺位113前后相邻的两个芯片111之间的信号线116长度，长于未间隔空缺位113的相邻芯片111间的信号线116长度，其中，长方向与并联方向垂直；和或，与空缺位113相邻的两个芯片111之间的电源线115长度，长于未间隔空 缺位113的相邻芯片111间的电源线115长度，其中，长方向与并联方向垂直。
示例性地，未间隔空缺位113的相邻芯片111可以为同一行或同一列。未间隔空缺位113的相邻芯片111，在垂直芯片阵列的芯片111并联方向上，为芯片阵列中非边缘的芯片111。
例如，结合图2A-图2C，图2A为电路板110的结构示意图；图2B示出了图2A所示的电路板110的电流图；图2C示出了图2A所示的电路板110的信号图。其中，芯片111并联方向为左右方向，垂直芯片阵列的芯片111并联方向为上下方向。结合图2A-图2C，在上下方向上，右侧第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距可以大于其他相邻取电单元114的间距，因而在上下方向上，右侧第7个取电单元114和第8个取电单元114之间的电源线115长度以及第12个取电单元114和第13个取电单元114之间的电源线115长度长于其他相邻取电单元114之间的电源线115长度，且右侧第7个取电单元114和第8个取电单元114之间的信号线116长度以及第12个取电单元114和第13个取电单元114之间的信号线116长度长于其他相邻取电单元114之间的信号线116长度。类似情况也存在于图1B、图3至图17以及图19A至图21B的电路板110中。
在一种实施方式中，芯片阵列的各芯片111之间的工作温差范围是0～10℃(包括端点值)。例如，在散热源为风扇的情况下，当风扇的转速为4000转/分钟时，各芯片111之间的温差可以为8～10℃(包括端点值)。这样，各芯片111之间的工作温差较小，从而提升电路板110的工作性能。
可选地，空缺位113为3个以上，沿散热方向，相邻空缺位113间距不相等。例如，此时芯片阵列中相邻列的列间距可以不相等。
进一步地，空缺位113为3个以上，沿散热方向，相邻空缺位113间距可以增大。例如，沿散热方向，芯片阵列中相邻列的列间距可以逐渐增大，这样，靠近出风口设置的芯片111较疏，从而可以降低靠近出风口设置的芯片111的工作温度，减小入风口和出风口处的芯片111温差。
在一种实施方式中，参照图1B-图9、图12-图15、图17-图19B、图21A-图21B，在垂直芯片阵列的芯片111并联方向上，空缺位113为芯片阵列中非边缘的芯片111。
在一种实施方式中，在垂直芯片阵列的芯片111并联方向上，空缺位113前后相邻的芯片111以外的其他非空缺位113相邻芯片111间距相等。如图1B所示，在上下方向上，右侧第10行和第11行为空缺位113。其中，右侧第1至9行中相邻芯片111间距相等，且第12行至21行中相邻芯片111的间距相等。
在一种实施方式中，在垂直芯片阵列的芯片111并联方向上，在空缺位113补齐芯片111后的前后相邻芯片111间距大于或等于其他非空缺位113相邻芯片111间距。也就是说，在空缺位113上补齐芯片111的情况下，该空缺位113上的芯片111与相邻芯片111之间的距离大于或等于其余相邻芯片111之间的距离。
在一种实施方式中，芯片阵列中的芯片111呈行列排布，每行或每列芯片111的中心在同一直线上。例如，在图1B的示例中，芯片阵列中的120个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的行间距相同，后3列芯片111的第10行和第11行缺失。前3列芯片111的数量为63个，后3列芯片111的数量为57个。芯片阵列的行方向为可以为散热方向，芯片阵列的列方向为垂直芯片111的散热方向。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，入风口处的芯片111的数量较多，可以增大入风口处的芯片111的发热量，出风口处的芯片111的数量较少，可以减小出风口处的芯片111的发热量，从而可以进一步降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。类似情况也存在于图2A至图21B的电路板110中。
在一种实施方式中，芯片阵列中的芯片111呈行列排布，每一个空缺位113的中心与行或列在同一直线上。示例性地，每一个空缺位113可以均设置在芯片阵列行列的交叉点上，即：空缺位113的中心与对应行芯片111中其他芯片111的中心在一条直线上，且空缺位113的中心与对应列芯片111中其他芯片111的中心在一条直线上。
在一种实施方式中，沿散热方向，芯片阵列中，电路板110上远离散热源的区域，空缺位113的数量增多。例如，在散热源为风扇的情况下，风扇设置于散热风道的入风口处，电路板110上远离散热源的区域即为电路板110上靠近出风口的区域。通过使电路板110上远离散热源的区域在散热方向上空缺位113的数量增多，可以使靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
在一种实施方式中，在高温容易发生区域,空缺位113的数量增多。例如，在散热源为风扇的情况下，风扇设置于散热风道的入风口处，电路板110上远离散热源的区域即为电路板110上靠近出风口的区域。通过使电路板110上远离散热源的区域在散热方向上空缺位113的数量增多，可以使靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，可以降低靠近出风口的芯片111与靠近入风口的 芯片111的最大温差，从而提升芯片111的均温性。
在一种实施方式中，环境温度高低与空缺位113的数量多少呈正比，电路板110上，环境温度越高的区域，设置的空缺位113的数量越多。其中，环境文字包括空气温度、芯片111温度、其他电子元器件温度以及电路板110的温度。例如，电路板110上对应的空缺位113所占区域内，不设置芯片111。空缺位113的数量多少与空缺位113所处区域的芯片111密度负相关，即空缺位113的数量越多，芯片111密度越小，空缺位113的数量越少，芯片111密度越大。如此设置，可以保证在环境温度较高的情况下芯片111的密度较小，从而有利于芯片111散热，减小芯片阵列中芯片111的最大温差。
在一种实施方式中，行芯片数最大的数值Y将芯片阵列划分为至少两个部分。
示例性地，在若Y为偶数，芯片阵列前Y/2列的总芯片数量A，大于芯片阵列后Y/2列的总芯片数量B。例如，在图1B中，Y为偶数6，芯片阵列前3列的总芯片数量为63个，芯片阵列后3列的总芯片数量为57个。
若Y为奇数，芯片阵列前(Y-1)/2列的总芯片数量C，大于芯片阵列后(Y-1)/2列的总芯片数量D。例如，以Y为7为例进行说明。此时芯片阵列前3列的总芯片数量C大于芯片阵列后3列的总芯片数量D。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
或者，若Y为偶数，芯片阵列前Y/2列及对应列的总芯片数量A还可以小于芯片阵列后Y/2列及对应列的总芯片数量B。例如，在图17中，Y为偶数6，芯片阵列前3列的总芯片数量为57个，芯片阵列后3列的总芯片数量为63个。
若Y为奇数，芯片阵列前(Y-1)/2列及对应列的总芯片数量C，还可以小于芯片阵列后(Y-1)/2列及对应列的总芯片数量D。例如，以Y为7为例进行说明。此时芯片阵列前3列的总芯片数量C可以小于芯片阵列后3列的总芯片数量D。
当然，本申请不限于此，若Y为偶数，芯片阵列前Y/2列及对应列的总芯片数量A，还可以等于芯片阵列后Y/2列及对应列的总芯片数量B。例如，在图12的示例中，Y为偶数6，芯片阵列前3列的总芯片数量为57个，芯片阵列后3列的总芯片数量为57个。
若Y为奇数，芯片阵列前(Y-1)/2列及对应列的总芯片数量C，等于芯片阵列后(Y-1)/2列及对应列的总芯片数量D。例如，以Y为7为例进行说明。此时芯片阵列前3列的总芯片数量C可以等于芯片阵列后3列的总芯片数量D。
本申请还提供了一种工作组件2100，包括电路板110和散热器2110。其中，电路板110为上述任一实施方式中的电路板110，散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接。
示例性地，散热器2110可以为风冷式散热器2110或液冷式散热器2110。散热器2110可以位于电路板110的设置有工作芯片111的一侧，用于为电路板110进行散热。散热器2110也可以位于电路板110的未设置有芯片111的一侧。或者，在电路板110的两侧均设置芯片111，且电路板110的两侧均分别设置有散热器2110。
在一种实施方式中，第二面设置有多个凸台，各凸台与各行取电单元114或各列取电单元114对应设置。这样，取电单元114中的芯片111工作过程中产生的热量能够有效通过凸台传导至散热器2110，从而提升散热效果。
或者，在另一种实施方式中，第二面设置有多个凸台，至少部分凸台还可以设置于至少部分相邻取电单元114之间的对应位置。例如，在图3中，电路板110上的117个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。第6行、第11行和第16行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第6行、第11行和第16行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第二部分中第5个取电单元114和第6个取电单元114的对应位置、第9个取电单元114和第10个取电单元114的对应位置以及第13个取电单元114和第14个取电单元114的对应位置。
在一种实施方式中，如图2A所示，靠近出风口的多个芯片111沿第二方向划分为多组发热元器件组，相邻两组发热元器件组之间的间隙大于各发热元器件组中相邻两个芯片111之间的间隙。
例如，在图2A的示例中示出了六列芯片111。为方便描述，将沿第一方向依次排布的六列芯片111分别称为第一发热列、第二发热列……第六发热列。第一发热列至第三发热列中的芯片111的数量为21个，第四发热列至第六发热列中的芯片111的数量为19个。其中，第一发热列至第三发热列中的21个芯片111均匀间隔设置。第四发热列至第六发热列中的19个芯片111划分为三组发热元器件组，且三组发热元器件组中位于第二方向两端的发热元器件组中的芯片111的数量相同，位于第二方向中部的发热元器件组中的芯片111的数量小于两端的发热元器件组中的芯片111的数量。
本实施例中，出风口处的相邻两组发热元器件组之间可以具有较大的散热间隙，可以降低靠近出风口的温度，进而可以降低入风口与出风口的最大温差，从而提升工作组件100的均温性。
在一种实施方式中，芯片111的排布方式可以有多种形式。靠近入风口的第一列(如上述第一发热列)至出风口的最后一列(如上述第六发热列)，每列芯片数量不完全相等。可以为每列芯片数量逐渐递减，例如21个、20个、19个、18个、17个、16个；可以为部分递减，例如21个，21个，21个，19个、19个、19个；也可以为数量跳变，例如21个，21个，20个，19个，20个，21个；或者21个，21个，20个，19个，18个，21个；还可以根据散热需求，设置其他数量的芯片阵列，使得靠近入风口的前半部分芯片总数，大于靠近出风口的后半部分芯片总数，这里的前半部分和后半部分，可以是芯片列数的对半分割，也可以是电路板110尺寸上的对半分割。如图2A，设置靠近入风口的前三列芯片总数大于靠近出风口的后三列芯片总数。
由于每列芯片数量的变化，每行芯片的排布也可以进行不同形式的组合，且每行芯片的数量可以不同。例如，部分行芯片以芯片中心点呈一直线排列，部分行芯片的中心点未形成一直线，例如阶梯排布(如配合上述“每列芯片数量逐渐递减，例如21个、20个、19个、18个、17个、16个”行方向呈现阶梯排布)。每行芯片的数量也存在不同实施例，例如第二方向上，靠近电路板110两端的行芯片数量大于靠近电路板110中心位置行芯片数量。总之，对总芯片分布和/或数量进行分割，分割成的各部分芯片总数，符合预设分布要求。
具体的，第二方向上，以第一发热列芯片数量为分割依据，将电路板110从左至右分割为三部分，第一部分，第二部分及第三部分，靠近电路板110两端的第一部分或第三部分的芯片总数，大于中间第二部分的芯片数量。在另一实施例中，若第二方向上，以第一发热列芯片数量为分割依据，将电路板110从左至右分割为两部分，则第一部分的芯片数量小于或者等于第二部分的芯片数量。
上述具体的分割，参考图2A，第二方向上，以第一发热列芯片数量为分割依据，在一种实施例中，分割方式为平均分割，将电路板110从左至右分割为三部分，第一发热列共有21个芯片，将电路板110从左至右分割为三部分，每第一发热列中的7个芯片对应分割为一部分，则第一部分的芯片总数为42个，第二部分的芯片总数为36个，第三部分的芯片总数为42个。靠近电路板110两端的第一部分(42个)或第三部分的芯片总数(42个)，大于中间第二部分的芯片数量(36个)；若第二方向上，以第一发热列芯片数量为分割依据，将电路板110从左至右分割为两部分，可以以第一发热列的中间第11个芯片中心轴为分割点，将电路板110从左至右分割为两部分，则第一部分的芯片数量(57个)等于第二部分的芯片数量(57个)。本领域技术人员可以理解的是，分割方式不限于上述记载，当第一发热列芯片总数为奇数或者偶数时，可 以灵活选择分割的方式。当然，也可以以电路板排布芯片的边沿，所形成的整体面积为基准，对其进行分割划分，可以为平均分割，当然也可以按其他比例进行分割，以使得每一部分的芯片总数符合预设分布要求。
总之，芯片111的排布方式，可以结合风道中各个位置的散热情况而设置。例如入风口环境温度低，整体散热效率高，则可以多布置芯片数量，出风口环境温度高，整体散热效率低，则可以少布置芯片数量，靠近出风口芯片总数小于入风口芯片总数。同时，电路板110的上下两端，与风的方向垂直的方向上，两端的温度低于电路板110中心的温度，则两端可以多布置芯片111，中心位置少布置芯片111，两端芯片总数大于中心芯片总数，也可以分成两部分后，下半部分的芯片总数大于上半部分的芯片总数。这与通常改变散热器的热阻实现均温，是完全不同的设计思路。
在一些实施例中，本申请还提供一种电路板110，该电路板110上设置有多个芯片组118，各芯片组110包括至少一行芯片和/或至少一列芯片，至少部分相邻两个芯片组之间的组间间距与任一芯片组内相邻芯片间距不相等。
多个芯片组118排列构成芯片阵列，在构成芯片阵列时，沿行方向或者列方向，至少部分相邻芯片组118的间距大于或等于容纳一个芯片所需的间距，也即部分相邻芯片组118之间存在芯片空缺位。
如图1B所示，左侧三列芯片为一个芯片组118，右侧三列芯片第1行至第9行为一个芯片组118，右侧三列芯片第10行至第19行为一个芯片组118，3个芯片组118构成芯片阵列，右侧三列芯片的2个芯片组118之间存在一行芯片空缺位。
如图2A所示，左侧三列芯片为一个芯片组118，右侧三列芯片第1行至第7行为一个芯片组118，右侧三列芯片第8行至第12行为一个芯片组118，右侧三列芯片第13行至第19行为一个芯片组118，4个芯片组118构成芯片阵列，右侧三列芯片的3个芯片组118之间存在两行芯片空缺位。
如图6A所示，左侧三列芯片第1行至第10行为一个芯片组118，将左侧三列芯片第11行至第20行为一个芯片组118，将右侧三列芯片第1行至第7行为一个芯片组118，将右侧三列芯片第8行至第12行为一个芯片组118，将右侧三列芯片第13行至第19行为一个芯片组118，5个芯片组118构成芯片阵列，左侧三列芯片的3个芯片组118之间存在一行芯片空缺位，右侧三列芯片的3个芯片组118之间存在两行芯片空缺位。
芯片组118由至少一个取电单元114构成，取电单元114包括至少一个芯片。当取电单元114包括多个芯片时，取电单元114中的芯片同处一行或一列且并联连接。 各芯片组118的芯片并联方向相同，沿垂直芯片并联方向的方向，至少部分相邻芯片组118的间距，与任一芯片组118内相邻取电单元114的间距不相等。芯片组118包括多个取电单元114，多个取电单元114串联连接。各芯片组118的芯片串联方向相同，沿芯片串联方向，至少部分相邻芯片组118的间距，与任一芯片组118内相邻取电单元114的间距不相等。芯片组118之间的芯片可沿行列方向等间距或不等间距或间距递增或间距递减布置，但是至少部分相邻芯片组118之间的间距会因芯片空缺位的存在，与芯片组118内的相邻芯片间距不同。需要说明的是，上述实施例中芯片的电连接方式，并不仅限于串联和并联，芯片之间还可以是串联和并联组合等其他电连接方式。
本实施例中电路板110上的芯片按组划分，且设置为各芯片组110之间的组间间距大于各芯片组118内的芯片间距，在各芯片组之间形成了散热通道，从而使得排布于电路板上的芯片更便于散热。例如，如图1B中所示的电路板110上各芯片之间是等间距密集排布的，不利于靠近中心区域的芯片散热。通过本申请实施例，将所有芯片按组划分多个组118，并且将组间间距设置为大于组内芯片间距，从而使得靠近电路板中心区域的芯片可以通过更宽的组件间距实现散热，从而提升了整个电路板上所有芯片的均温性。示例性地，芯片组之间的间距对应于图1B中的一个或者多个连续空缺位113。
在一些实施例中，垂直芯片的并联方向上，相邻两个芯片组118之间的间距大于或等于容纳一个芯片111所需的间距。
本实施例中，通过将芯片组118之间的间距设置为大于或等于容纳一个芯片111所需的距离，确保了各芯片组118之间的间距足够大，从而保证了靠近中心区域的芯片的散热。
在一些实施例中，各芯片组118包括多行芯片，且至少存在两个芯片组118的芯片行数不同。例如，各芯片组118包括至少一行芯片，各芯片组118所包含的芯片行数不唯一。如图16所示，电路板110上划分了只包含一行芯片的芯片组、包含两行芯片的芯片组、包含三行芯片的芯片组等，各芯片组分别形成了芯片阵列。
本实施例中对芯片组内芯片的行数不做限定，方便根据电路板空间以及芯片总数的实际情况，进行各芯片组的排布及划分。
在一些实施例中，各芯片组118包括多列芯片，且各芯片组118的芯片列数相同。如图1B所示，电路板110上包括了三个芯片组118，其中位于电路板110所示左半部分的三列芯片为一个芯片组118，位于电路板所示右半部分的三列芯片划分为两个芯片 组118，且该两个芯片组118之间设置有较大间隙，可以容纳至少两行芯片。
示例性地，本实施例中在对电路板110进行散热时，电路板110所示的左侧位于散热方向的上游，右侧位于散热方向的下游。通过将靠近散热方向下游的三列芯片划分为两组或者更多组(例如三组，参考图2A、图4、图5、图10、图11、图18)，确保组间间隙，从而提升了散热方向下游芯片的散热性能，改善了整个电路板上芯片间的均温性。
在一些实施例中，多个芯片组118之间串联供电连接，且各芯片组118的各行芯片之间串联供电连接。
示例性地，如图2B所示，电路板110上包括四个芯片组118，其中包括位于电路板110左半部分的第一芯片组(三列芯片)，位于电路板右半部分的从上至下的第二芯片组、第三芯片组和第四芯片组。电路板上还包括第一电连接件和第二电连接件，其中，一个用于连接电源正极，一个用于连接电源负极。第一芯片组、第二芯片组、第三芯片组和第四芯片组依次顺序串联在第一电连接件119和第二电连接件119’之间实现串联供电。
本实施例中，各芯片组118所包含的芯片列数相同，从而确保在各芯片组118之间进行串联连接时，便于布置成串的多个芯片组在电路板上所占空间区域，有利于电路板设计的通用性以及电路板上走线(例如，芯片之间以及芯片组之间的电源线115和信号线)的合理规划。
在一些实施例中，各芯片组118的各行芯片内的芯片之间并联供电连接。示例性地，各芯片组118内所包含的芯片行之间同样为串联供电连接，并且各芯片组118内每行芯片并联连接。
本实施例中通过各行芯片之间进行并联连接，可以使得各行芯片内各芯片的电压一致，从而确保各芯片获得相同的工作电压，提升工作稳定性。
进一步地，在电路板110上所有芯片一致时(例如，相同型号芯片)，由于各行芯片数量相同，从而并联的各行芯片在串联方向上的压降基本一致且稳定，即有利于将各行芯片之间的工作电压稳定预定范围内，提升芯片工作的稳定性。
在一些实施例中，列方向与垂直芯片的并联方向，行方向平行于芯片的并联方向。电路板110上的芯片至少部分呈行列排布，其中行方向垂直于电路板110上并联芯片的并联方向。
在一些实施例中，各芯片组118由至少一个取电单元114组成，其中，取电单元114中的芯片并联连接，取电单元114中的芯片呈行排列。示例性地，芯片组118中包 括多行芯片，每行芯片之间并联连接构成一个取电单元，并且多行芯片构成的多个取电单元114之间串联连接。
本实施例中将取电单元114内所包含的多个芯片并联连接，确保了取电单元114内各芯片所获取电压的大小一致，有利于提升取电单元114内各芯片工作性能的一致性(例如，算力一致性或者工作频率的一致性等)。
在一些实施例中，沿散热方向，多个芯片组118划分至少一个芯片组集合。
本申请实施例中所提及的散热方向，例如可以为风的方向。例如在风冷散热中，采用散热风扇对电路板110进行散热，风把电路板110上芯片工作所产生的热量带走，从而实现散热。
如图21A所示，电路板110上包括上下两个芯片组118，两个芯片组118之间的间距大于各组芯片内芯片之间的间距。本实施例中将电路板110上上下两个芯片组118划分为一个芯片组集合。此外，两个芯片组118之间形成散热风道，散热风道方向平行于散热方向，且贯穿整个电路板110上的芯片矩阵的中部区域，便于电路板110中部及后部区域上芯片111的散热。
在一些实施例中，多个芯片组118划分为第一芯片组集合和第二芯片组集合。
如图6和图7所示实施例中，电路板110上包括了5个芯片组118，划分为两个芯片组集合，第一芯片组集合包括上下分布的两个芯片组118，第二芯片组集合包括上中下三个芯片组118。进一步地，该实施例中各芯片组集合中的芯片组118之间所形成间隙(即，散热风道)相互之间错位，这样当风从第一芯片组集合中的散热风道流向第二芯片组集合时，直接流向芯片排布密集的区域，有利于形成扰流，增大散热效率。此外，图13-16中也同样存在散热风道错位的情况，在此不再赘述。
在一些实施例中，芯片组集合内的芯片串联电流方向相同。
进一步地，如图21B示出了图21A中各芯片的串联供电连接关系，本实施例中，整行芯片内的各芯片并联，各行芯片之间串联，并且通过两个电连接件实现于外部电源的连接。图中连接线上的箭头方向为串联电流方向，整体上电流方向从一个电连接件流入第一行芯片，再经由各行芯片顺序流入最后一行芯片后经另一个电连接件流出。
在一些实施例中，第一芯片组集合和第二芯片组集合中的芯片数量相等。
如图12和图13所示的实施例中，第一芯片组集合和第二芯片组集合中分别包括了三个芯片组，并且第一芯片组集合中包括两个第一间隙，第二芯片组集合中包括两个第二间隙，并且两芯片组集合中所包含的芯片数量相等，均为57个。
本实施例中在对电路板110上芯片进行分组的，形成组件间隙实现散热的同时， 第一芯片组集合和第二芯片组集合中芯片数量保持一致，便于电路板110上芯片的布局。
进一步地，第一芯片组集合和第二芯片组集合的芯片列数相同，且第一芯片组集合的芯片数量等于第二芯片组集合的芯片数量。
各芯片组集合所包含的芯片列数相同，从而确保在各集合内芯片组之间进行串联连接时，便于布置成串的多个芯片组118在电路板110上所占空间区域，有利于电路板110设计的通用性以及电路板110上走线(例如，芯片之间以及芯片组之间的电源线115和信号线116)的合理规划。
在一些实施例中，第一芯片组集合小于第二芯片组集合中的芯片数量。
如图16和图17所示实施例中，电路板110上将所有芯片划分为了左右两部分，分别对应第一芯片组集合和第二芯片组集合。其中，第一芯片组集合小于第二芯片组集合中的芯片数量。本实施例中，第二芯片组集合可以处于散热效率较高区域，第一芯片组集合可以处于散热效率较低区域，从而便于实现整个电路板110上芯片的均温性。
进一步地，第一芯片组集合和第二芯片组集合的芯片列数相同，且第一芯片组集合的芯片数量小于第二芯片组集合的芯片数量。
各芯片组集合所包含的芯片列数相同，从而确保在各集合内芯片组118之间进行串联连接时，便于布置成串的多个芯片组118在电路板110上所占空间区域，有利于电路板110设计的通用性以及电路板110上走线(例如，芯片之间以及芯片组之间的电源线115和信号线116)的合理规划。
在一些实施例中，第一芯片组集合大于第二芯片组集合中的芯片数量。
如图14、图15和图6-9中，电路板110上将所有芯片划分为了左右两部分，分别对应第一芯片组集合和第二芯片组集合。其中，第一芯片组集合中的芯片数量大于第二芯片组集合中的芯片数量。
本实施例中，第一芯片组集合中芯片111的数量大于第二芯片组集合中芯片111的数量，从而第一芯片组集合整体上的芯片密度要大于第二芯片组集合整体上的芯片密度。第一芯片组集合可以处于散热效率较高区域，第二芯片组集合可以处于散热效率较低区域，从而便于实现整个电路板110上芯片111的均温性。
示例性地，本实施例中的电路板110可以设置为：第一芯片组集合靠近散热源。例如，散热源为风扇，风扇配置为风向平行于电路板110上芯片111的并联方向，并且第一芯片组集合靠近风扇。
进一步地，第一芯片组集合和第二芯片组集合的芯片列数相同，且第一芯片组集合的芯片数量大于第二芯片组集合的芯片数量。
各芯片组集合所包含的芯片列数相同，从而确保在各集合内芯片组之间进行串联连接时，便于布置成串的多个芯片组118在电路板110上所占空间区域，有利于电路板110设计的通用性以及电路板110上走线(例如，芯片之间以及芯片组之间的电源线115和信号线116)的合理规划。
在一些实施例中，第一芯片组集合的平均芯片间距，小于第二芯片组集合的平均芯片间距。
如图2A所示，电路板110上包括前三列芯片构成的第一芯片组集合和后三列芯片构成的第二芯片组集合，其中第一芯片组集合中仅包括一个芯片组，第二芯片组集合中包括沿列方向的三个芯片组。第一芯片组集合中三列芯片之间的列间距的平均值小于第二芯片组集合中三列芯片之间的列平均间距。
本实施例中的电路板110处于工作环境中时，第一芯片组集合和第二芯片组集合沿散热方向分布。以风冷散热为例，散热方向为风扇的吹风方向，第一新芯片组集合位于散热方向的上游，第二芯片组集合位于散热方向的下游(其中，上游和下游仅仅是相对于电路板110于风扇所处位置来说的，电路板110更靠近风扇一端为上游，相对的另一端为下游)。相对来说，从上游至下游，风的温度逐步提高，通过将第二芯片组集合中的列间距设置为大于第一芯片组集合中的列间距，从而有利于改善电路板110上芯片111的均温性。
在一些实施例中，第一芯片组集合中，垂直芯片111的并联方向上，包括1个芯片组；沿垂直方向，第一芯片组集合中芯片组内相邻芯片间的芯片间距相等。
如图2A所示，位于电路板110左侧的第一芯片组集合包括一个芯片组，并且组内各芯片111在垂直芯片111的并联方向上的间距是相等的。由于各芯片组118内垂直芯片111的并联方向上，各行芯片111是串联连接的，通过等间距的设置芯片111，有利于电路板110的硬件设计。例如，芯片111间连接件或者布线采取统一的大小或者长度即可，一方面简化了设计，另一方面也可以降低成本。其中，连接件可以是贴于芯片111之间的铜片或者焊盘等。需要注意的是，以上仅为示例，本申请并不限于此。
在一些实施例中，第一芯片组集合中，垂直芯片111的并联方向上，包括多个芯片组118；第一芯片组集合中各相邻芯片组118之间的组间距大于各芯片组118内相邻芯片间的芯片间距。
本实施例中电路板110上的芯片111包括第一芯片组集合，且该集合中设置为各 芯片组118之间的组间间距大于各芯片组118内的芯片间距，在各组芯片之间形成了散热通道，从而使得排布于电路板110上的芯片111更便于散热。
在一些实施例中，第二芯片组集合中，垂直芯片的并联方向上，包括1个芯片组；沿垂直方向，第二芯片组集合中芯片组内相邻芯片111间的芯片间距相等。
如图17所示，位于电路板110右侧的第二芯片组集合包括一个芯片组118，并且组内各芯片在垂直芯片的并联方向上的间距是相等的。由于各芯片组118内垂直芯片的并联方向上，各行芯片111是串联连接的，通过等间距的设置芯片，有利于电路板110的硬件设计。例如，芯片间连接件或者布线采取统一的大小或者长度即可，一方面简化了设计，另一方面也可以降低成本。其中，连接件可以是贴于芯片之间的铜片或者焊盘等。需要注意的是，以上仅为示例，本申请并不限于此。
在一些实施例中，第二芯片组集合中，垂直芯片111的并联方向上，包括多个芯片组118；第二芯片组集合中各相邻芯片组118之间的组间距大于各芯片组118内相邻芯片间的芯片间距。
本实施例中电路板110上的芯片包括第二芯片组集合，且该集合中设置为各芯片组118之间的组间间距大于各芯片组118内的芯片间距，在各组芯片之间形成了散热通道，从而使得排布于电路板110上的芯片更便于散热。
在一些实施例中，垂直芯片111的并联方向上，第一芯片组集合中的多对相邻芯片组之间形成多个第一间隙；第二芯片组集合中的多对相邻芯片组之间形成多个第二间隙。
示例性地，各芯片组118之间的间隙大于或等于容纳一个芯片111所需的间距。本实施例中电路板110上的芯片包括第一芯片组集合和第二芯片组集合，且集合内各芯片组118之间形成间隙，在各组芯片之间形成了散热通道，从而使得排布于电路板110上的芯片111更便于散热。
在一些实施例中，多个第一间隙和多个第二间隙一一对应，且至少部分相互对应的第一间隙和第二间隙共线。如图8、9、12所示实施例中至少部分相互对应的第一间隙和第二间隙共线。其中图8和图9所示实施例中，存在一个第一间隙，三个第二间隙，并且只有一对第一间隙和第二间隙共线；图12所示实施例中存在两个第一间隙和两个第二间隙，并且两对第一间隙和第二间隙分别共线。
本实施例中通过将位于第一芯片组集合中的第一间隙和位于第二芯片组集合中的第二间隙设置为共线，大大减少了风阻，从而提升风速及风量，提高散热效率。
在一些实施例中，对于至少一个第一间隙，第二芯片组集合中不存在共线的第二 间隙。如图6和图7所示实施例中，电路板110上包括了5个芯片组118，划分为两个芯片组集合，第一芯片组集合包括上下分布的两个芯片组，第二芯片组集合包括上中下三个芯片组。
进一步地，本实施例中各芯片组集合中的芯片组118之间所形成间隙(即，散热风道)相互之间错位，这样当风从第一芯片组集合中的散热风道流向第二芯片组集合时，直接流向芯片排布密集的区域，有利于形成扰流，增大散热效率。此外，图13-16中也同样存在散热风道错位的情况，在此不再赘述。
在一些实施例中，多个第一间隙的数量小于多个第二间隙的数量。
如图6-图9、图14和图15，电路板110上包括左右分布的第一芯片组集合和第二芯片组集合，分别包括三列芯片，其中，第一芯片组集合中的第一间隙数量小于第二芯片组集合中的间隙数量。以图6为例，第一芯片组集合中包括一个第一间隙，第二芯片组集合中包括两个第二间隙。
本实施例中在第一芯片组集合中设置了较少的第一间隙，在第二芯片组集合中设置了较多的第二间隙，间隙越多，可设置芯片111的空间就越少，从而第一芯片组集合中芯片数量就大于第二芯片组集合中芯片数量，从而整体上第一芯片组集合中芯片111分布较密集，第二芯片组集合中芯片111分布较稀疏。可见，本实施例中沿散热方向(或者沿芯片并联方向)，芯片整体排布呈前密后疏的趋势，便于电路板110上各区域芯片111的均温性。
在一些实施例中，垂直芯片的并联方向上，第一芯片组集合中至少一列芯片的数量大于第二芯片组集合中至少一列芯片的数量。
如图1B-图10、图14、图15、图18和图20所示，电路板110上均包括左右分布的第一芯片组集合和第二芯片组集合，分别包括三列芯片111，其中，第一芯片组集合中至少一列芯片的数量大于第二芯片组集合中至少一列芯片的数量。以图4为例，第一芯片组集合中包括一个芯片组，第二芯片组集合中包括5个芯片组，并且第一芯片组集合中的任意一列芯片的芯片数都大于第二芯片组中任意一列芯片的芯片数。
进一步地，第一芯片组集合中所有芯片列的芯片数量均大于第二芯片组集合中所有芯片列的芯片数量。本实施例中将第一芯片组集合中芯片列所包含芯片111的数量设置为小于第二芯片组集合中芯片列所包含芯片111的数量，从而可以整体上使得第一芯片组集合中芯片数量大于第二芯片组集合中芯片数量。
第一芯片组集合和第二芯片组集合沿散热方向分布，从而以上实施例中芯片数量的设置可以提升电路板110上芯片111的均温性。
在一些实施例中，第一芯片组集合中至少一列芯片的首芯片至尾芯片的距离小于第二芯片组集合中至少一列芯片的首芯片至尾芯片的距离。
如图10、图11和图16所示实施例，电路板110上均包括左右分布的第一芯片组集合和第二芯片组集合，分别包括三列芯片，其中，第一芯片组合集中仅包括一个芯片组，并且该芯片组中缺失第一行三个芯片(如图10和图16所示)，或者该芯片组118中缺失第一行和最后一行芯片(如图11所示)，而第二芯片组集合中未缺失上下端部的芯片，从而使得第一芯片组集合中的芯片列中首芯片至尾芯片的距离小于第二芯片组集合中至少一列芯片的首芯片至尾芯片的距离。
示例性地，第一芯片组集合和第二芯片组集合沿散热方向分布。本实施例中第一芯片组集合中缺失芯片行的区域形成延伸至第二芯片组集合的散热通道。以风冷散热为例，风可以通过散热通道进入第二芯片组集合进行散热，增大了进入第二芯片组集合的风量。此外，由于散热通道的仅上侧或者下侧存在芯片，使得经散热通道进入第二芯片组集合的风吸收热量较少，温度相对较低，便于第二芯片组集合的散热降温，改善了整个电路板110上芯片的均温性。
在一些实施例中，第一芯片组集合中芯片组的数量小于第二芯片组集合中芯片组的数量。
如图1B-图10、图14、图15、图18和图20所示实施例中，电路板110上均包括左右分布的第一芯片组集合和第二芯片组集合，第一芯片组集合中芯片组的数量小于第二芯片组集合中芯片组的数量。整体上第一芯片组集合中所形成的芯片组之间的第一间隙的数量小于第二芯片组集合中所形成的芯片组之间的第二间隙的数量。更多的第二间隙使得第二芯片组集合中的芯片111具有更高的散热效率，对于风冷散热，虽然经第一芯片组集合后进入第二芯片组集合的风温度较高，但由于第二芯片组集合中第二间隙较多，平衡了风温度较多的问题，从而提升了电路板110上芯片111的均温性。
在一些实施例中，垂直芯片的并联方向上，第二芯片组集合包括两个端部芯片组和一个中部芯片组，其中，各端部芯片组的芯片数量大于中部芯片组的芯片数量。
如图6所示实施例中，电路板110上均包括左右分布的第一芯片组集合和第二芯片组集合，其中，第二芯片组集合中各芯片组118包含相同列芯片，且两端部芯片组分别包括7行芯片111，中部芯片组包括5行芯片111，两端部芯片组中所包含芯片的数量大于中部芯片组所包含芯片111的数量。
示例性地，第一芯片组集合和第二芯片组集合沿散热方向分布。以风冷散热为例， 风先进入第一芯片组集合吸收热量后进入第二芯片组集合。示例性地，本实施例的电路板110竖直配置于电子设备的壳体中，电子设备壳体的上下两端有利于电路板110上下两端芯片111的散热，因此该两端的芯片数量可以相对中部更多，以便实现芯片111之间的均温性。
在一些实施例中，两个端部芯片组包括第一端部芯片组和第二端部芯片组，第一端部芯片组的芯片数量小于第二端部芯片组的芯片数量，其中，在电路板110的垂直放置状态下，第一端部芯片组靠接电路板110的顶部，第二端部芯片组靠近电路板110的底部。
示例性地，第一芯片组集合和第二芯片组集合沿散热方向分布。以风冷散热为例，风先进入第一芯片组集合吸收热量后进入第二芯片组集合。在散热方向上，风温度逐渐升高，由于温度越高的风越趋于上升，因此较高温度的风上升至第一端部芯片组，温度较低的风进入第二端部芯片组。通过将第一端部芯片组所包含芯片数量设置为少于第二端部芯片组所包含芯片数量，可以更好的实现芯片的均温性。
在一些实施例中，垂直芯片的并联方向上，各端部芯片组中芯片111间的平均间距小于中部芯片组中芯片111间的平均间距。
示例性地，第一芯片组集合和第二芯片组集合沿散热方向分布。以风冷散热为例，风先进入第一芯片组集合吸收热量后进入第二芯片组集合。示例性地，本实施例的电路板110竖直配置于电子设备的壳体中，电子设备壳体的上下两端有利于电路板110上下两端芯片的散热，因此该两端的芯片间距可以相对中部更小，以便实现芯片111之间的均温性。
在一些实施例中，沿散热方向，第一芯片组集合中平均芯片间距小于第二芯片组集合中平均芯片间距。
示例性地，第一芯片组集合和第二芯片组集合沿散热方向分布。以风冷散热为例，风先进入第一芯片组集合吸收热量后进入第二芯片组集合，进入第二芯片组集合的风温度更高。通过第一芯片组集合中平均芯片间距设置为小于第二芯片组集合中平均芯片间距，使得第二芯片组集合中芯片列更稀疏，便于实现整个电路板110上芯片111之间的均温性。
在一些实施例中，垂直芯片的并联方向上，相邻芯片组之间的电连接线长度大于芯片组内相邻芯片之间的电连接线长度。示例性地，电连接线包括电源线115和/或信号线116。
如图2B所示实施例中，电路板110上均包括左右分布的第一芯片组集合和第二芯 片组集合，其中，第二芯片组集合中包括上中下三个芯片组，可以看出各芯片组118之间的电源线115长度要长于各芯片组118内芯片件的电源线115长度。同样的情况存在于图19B和图21B中，在此不再赘述。
如图2C所示实施例中，电路板110上均包括左右分布的第一芯片组集合和第二芯片组集合，其中，第二芯片组集合中包括上中下三个芯片组，可以看出各芯片组118之间的信号线116长度要长于各芯片组118内芯片件的信号线116长度。
在一些实施例中，垂直芯片的并联方向上，相邻芯片组之间设置有金属件。通过在相邻芯片组之间设置金属件，可以较小相邻芯片组之间的压降。
在一些实施例中，垂直芯片的并联方向上，各芯片组118内的相邻芯片间设置有金属件，相邻芯片组之间的金属件长度大于相邻芯片111间的金属件长度。通过在相邻芯片组之间以及芯片组内的芯片111之间设置金属件，可以较小相邻芯片111之间的压降。
另一方面，如图23所示本申请还提供一种工作组件2100，其包括：
电路板110，如前述任一实施例所述；
散热器2110，该散热器包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接。此外，第二面设置有多个凸台，各凸台与各行芯片或各列芯片对应设置。
进一步地，第二面设置有多个凸台，至少部分凸台设置于至少部分相邻芯片组118之间或至少部分相邻取电单元之间或至少部分空缺位的对应位置。
需要说明的是，若电路板110上具有空缺位113时，可能的一种情况是至少部分凸台与空缺位113对应。
本实施例中至少部分凸台设置于至少部分相邻芯片组118之间的对应位置，即将凸台对应于芯片组118之间的间隙设置，在凸台与间隙之间形成散热通道。在风冷散热中可以提升通过此散热通道的风量，有利于整个电路板上芯片的均温性。
下面结合图1B-图21B描述根据本申请多个实施例的电路板110。
实施例一
图1B示出根据本申请实施例一的电路板110的结构示意图。在实施例一中，散热方向为图1B中从左向右的方向，并联方向和行方向为图1B中的左右方向，垂直于并联方向的方向、垂直于散热方向的方向和列方向均为图1B中的上下方向。
如图1B所示，电路板110上设置有芯片阵列，芯片阵列的芯片111数量大于20个或50个，例如，图1B中芯片阵列的芯片111数量为120个。芯片阵列设置为X*Y， 芯片阵列的列方向上，列芯片数最大的数值为X，芯片阵列的行方向上，行芯片数最大的数值为Y。在实施例一中，X为21，Y为6。
在图1B的示例中，在左右方向上，芯片阵列所占电路板110的矩形区域划分为两个分布区，即行芯片数最大的数值Y将芯片阵列等分为两个分布区，两个分布区分别为第一分布区(例如，图1B中的左三列芯片111)和第二分布区(例如，图1B中的右三列芯片111)，第一分布区和第二分布区内的取电单元114数量不相等。具体地，第一分布区包括呈21行3列排布的63个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括21个取电单元114。第二分布区包括呈19行3列排布的57个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括19个取电单元114。
当然，行芯片111最大的数值Y还可以将芯片阵列划分为大于两个分布区。本申请对分布区的数量不作限定。
在实施例一中，芯片111行方向为散热方向，第一分布区和第二分布区的列数相同(均为三列)。当然，本申请不限于此，当芯片111列方向为散热方向时，各分布区的芯片111行数可以相同。
沿左右方向，两个分布区内的取电单元114数量减小。如图1B所示，第一分布区中取电单元114的数量为21，第二分布区中取电单元114的数量为19。当然，本申请不限于此，在分布区的取电单元114数量大于2的情况下，相邻分布区内取电单元114的数量并非逐一减小，允许若干个相邻分布区内取电单元114的数量沿散热方向增加，只要总体上相邻分布区的间距沿左右方向为增大趋势即可。以分布区数量为6进行说明。沿左右方向，多个分布区的取电单元114数量可以分别为15，14，13，12，11，10；或者，多个分布区的取电单元114数量可以分别为12，12，11，11，10，10；又或者，多个分布区的取电单元114数量可以分别为11，10，10，10，10，10；再或者，多个分布区内取电单元114的数量可以分别为16，15，13，14，12，10。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
沿上下方向，第一分布区中的21个取电单元114之间的距离可以相等。第二分布区的第9个取电单元114和第10个取电单元114的间距可以大于其他相邻取电单元114的间距。其中，在上下方向上，上述“其他相邻取电单元114”为芯片阵列中非边缘的取电单元114。例如，其他相邻取电单元114的间距可以为同一列设置的第1至9个取 电单元114中相邻取电单元114的间距以及第10至19个取电单元114中相邻取电单元114的间距。上述“其他相邻取电单元114的间距”可以等于第一分布区中相邻取电单元114的间距，此时第一分布区的列平均间距小于第二分布区的列平均间距。
沿左右方向，相邻取电单元114之间的距离增加，和/或相邻芯片111之间的距离增加。例如，沿左右方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿散热方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿散热方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
在上下方向上，芯片阵列所占电路板110的矩形区域划分为多个子区域，至少两个子区域的取电单元114数量不相等。在实施例一中，基于第二分布区中第9个取电单元114和第10个取电单元114的间距，可以将第二分布区中第1至9个取电单元114分为一个子区域，该子区域包括9行3列排布的27个芯片111；将第10至19个取电单元114分为另一个子区域，该子区域包括呈10行3列排布的30个芯片111。
由此，在上下方向上，可以根据相邻取电单元114之间的间距对第二分布区中的19个取电单元114进行分割，将19个取电单元114分为两个子区域，各子区域中的取电单元114可以等间距排布，两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片111的温度，进而减小子区域内多个芯片111之间的温差。
沿左右方向，第一分布区与第二分布区的至少部分取电单元114分别在同一直线上。具体地，在图1B中，芯片阵列中的120个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的行间距相同，后3列芯片111的第10行和第11行缺失。前3列芯片111的数量为63个，后3列芯片111的数量为57个。芯片阵列的行方向为可以为散热方向。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，入风口处的芯片111的数量较多，可以增大入风口处的芯片111的发热量，出风口处的芯片111的数量较少，可以减小出风口处的芯片111的发热量，从而可以进一步降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
可选地，各分布区内芯片111的行间距可以相同，各行中的多个芯片111的中心可以在一条直线上。沿串联方向，第一分布区端部的3个芯片111与对应的子区域端 部的3个芯片111的中心在一条直线上。两个子区域之间的间隙与第一分布区的第10行和第11行芯片111在第一方向上对应。
其中，相邻取电单元114之间可以设置有金属件，沿上下方向，至少部分相邻取电单元114之间的金属件长度长于其他相邻取电单元114。由此，如此设置的金属件可以减小电流通道的电阻，减小电流通道的电压降，从而减小电流通道上的能量损耗。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图1B中，电路板110上的120个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。第10行和第11行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第10行和第11行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第9个取电单元114和第10个取电单元114之间的对应位置。
图1A中未设置芯片空缺位时，在预设总功率下，芯片阵列工作一段时间的温度如下所示，可见芯片温度在65℃至75℃的范围内波动，温差在10℃左右。

图1B中设置芯片空缺位113，在预设总功率不变的情况下，芯片阵列工作一段时间的温度如下所示,可见芯片温度在70℃至75℃的范围内波动，温差在5℃左右。需说明的是，预设功率不变但是芯片的数量减少，所以平均每个芯片的功率增加，导致每个芯片111的发热量也增加，但是图1B中因为芯片空缺位113的存在温度最高值仍为75℃左右，芯片散热得到改善，且芯片均温性得到了进一步的改善。如此说明，本申请有利于电路板110的散热和均温。上述实施例并不代表最终实际使用效果，只是针对本申请散热和均温的发明点进行说明。

实施例二
图2A示出根据本申请实施例二的电路板110的结构示意图。如图2A所示，电路板110上芯片阵列的芯片111数量为120个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分布区。具体地，第一分布区包括呈21行3列排布的63个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括21个取电单元114。第一分布区中的21个取电单元114之间的距离可以相等。第二分布区包括呈19行3列排布的57个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括19个取电单元114。在串联方向上，第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距可以大于其他相邻取电单元114的间距。
其中，在与并联方向垂直的方向上，上述“其他相邻取电单元114”为芯片阵列中非边缘的取电单元114。例如，其他相邻取电单元114的间距可以为同一列设置的第1至7个取电单元114的间距、第8至12个取电单元114的间距以及第13至19个取电单元114的间距。在图2A中，并联方向为行方向。
基于第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距，可以将第二分布区中第1至7个取电单元114分为第一个子区域，该子区域包括呈7行3列排布的21个芯片111；将第8至12个取电单元114分为第二个子区域，该子区域包括呈5行3列排布的15个芯片111；将第13至19个取电单元114分为第三个子区域，该子区域同样包括呈7行3列排布的21个芯片111。
由此，在串联方向上，可以根据相邻取电单元114之间的间距对第二分布区中的19个取电单元114进行分割，将19个取电单元114分为三个子区域，各子区域中的取电单元114可以等间距排布，相邻两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片111的温度，进而减小子区域内多个芯片111之间的温差。
沿并联方向，各分布区的取电单元114数量可以减小。如图2A所示，第一分布区中取电单元114的数量可以为21，第二分布区中取电单元114的数量可以为19。当然，本申请不限于此，在分布区的取电单元114数量大于2的情况下，各分布区的取电单元114数量可以依次逐渐减小，可以部分逐渐减小，也可以部分减小。以分布区数量为6进行说明。沿并联方向，多个分布区的取电单元114数量可以分别为15，14，13，12，11，10；或者，多个分布区的取电单元114数量可以分别为12，12，11，11，10，10；又或者，多个分布区的取电单元114数量可以分别为11，10，10，10，10，10。
相邻取电单元114之间可以设置有金属件，沿串联方向，至少部分相邻取电单元114之间的金属件长于其他相邻取电单元114，其中，长方向与并联方向垂直。例如，金属件可以为铜片。由此，如此设置的金属件可以减小电流通道的电阻，减小电流通道的电压降，从而减小电流通道上的能量损耗。
其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。沿串联方向，第一分布区端部的3个芯片111与对应的子区域端部的3个芯片111的中心在一条直线上。相邻两个子区域之间的间隙分别与第一分布区的第8行和第14行芯片111在第一方向上对应。
也就是说，芯片阵列中的120个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的行间距相同，后3列芯片111的第8行和第14行缺失。前3列芯片111的数量为63个，后3列芯片111的数量为57个。芯片阵列的行方向为可以为散热方向。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，同样可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
可选地，沿垂直于散热方向，第二分布区分布在两个端部区域和一个中间区域。各端部区域的芯片111数量大于等于中间区域的芯片111数量。在图2A中，端部区域的芯片111即为第一个子区域中的芯片111以及第三个子区域中的芯片111，中间区域的芯片111即为第二个子区域中的芯片111。端部区域的芯片111数量分别为21个，中间区域的芯片111数量为15个。由此，由于在电路板110应用于电子设备3100的情况下，两端区域的芯片111与外部环境距离较近，散热更好，通过使端部区域布置数量较多的芯片111，且中间区域布置数量较少的芯片111，可以有效降低中间区域的芯片111温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
其中，沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图2A中，电路板110上的120个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。第8行和第14行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第8行和第14行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第7个取电单元114和第8个取电单元114的对应位置以及第12个取电单元114和第13个取电单元114的对应位置。
图2B示出了图2A所示的电路板110的电流图；图2C示出了图2A所示的电路板110的信号图。如图2B和图2C所示，沿各芯片111组的串联方向，相邻分布区之间的电连接线长度大于各分布区内相邻取电单元114之间的电连接线长度。其中，电连接线可以为电源线115和/或信号线116长度。
此外，电路板110的上边缘设置有第一电连接件119和第二电连接件119'，第一电连接件119和第二电连接件119'可为L型。以上仅为示例，第一电连接件119和第二电连接件119'的位置及形状均不做限制，具体的，第一电连接件119和第二电连接件119'不仅限于设置在如图2A所示的上边缘，还可设置在其他边缘的位置。即各图中所示的L型供电端，其在图中所处的位置，并不以图中的为限，还可以设置在电路板的上下左右或任意位置。
需要说明的是，如图2B所示，电路板上110上的多个芯片111采用串并联供电连接方式，具体为：每三个芯片并联构成一个取电单元114，多个取电单元114串联连接在第一电连接件119和第二电连接件119'之间。以上取电单元114由三个芯片构成，仅作为示例，取电单元114还可以是2、4、5个甚至更多芯片并联构成，本申请对此不做限定。
图2A中设置芯片空缺位113，在预设总功率不变的情况下，芯片阵列工作一段时间的温度如下所示,可见芯片温度在70℃至75℃的范围内波动，温差在5℃左右。需说明的是，预设功率不变但是芯片111的数量减少，所以平均每个芯片111的功率增 加，导致每个芯片111的发热量也增加，但是图1B中因为芯片空缺位113的存在温度最高值仍为75℃左右，芯片散热得到改善，且芯片均温性得到了进一步的改善。如此说明，本申请有利于电路板111的散热和均温。上述实施例并不代表最终实际使用效果，只是针对本申请散热和均温的发明点进行说明。
实施例三
图3示出根据本申请实施例三的电路板110的结构示意图。如图3所示，电路板110上芯片阵列的芯片111数量为117个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分 布区。具体地，第一分布区包括呈21行3列排布的63个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括21个取电单元114。第一分布区中各取电单元114的间距可以相等。第二分布区包括呈18行3列排布的54个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括18个取电单元114。在串联方向上，第5个取电单元114和第6个取电单元114的间距、第9个取电单元114和第10个取电单元114、第13个取电单元114和第14个取电单元114的间距可以大于其他相邻取电单元114的间距。
其中，在与并联方向垂直的方向上，上述“其他相邻取电单元114”为芯片阵列中非边缘的取电单元114。其他相邻取电单元114的间距可以为同一列设置的第1至5个取电单元114的间距、第6至9个取电单元114的间距、第10至13个取电单元114的间距以及第13至19个取电单元114的间距。在图3中，并联方向为行方向。
基于第5个取电单元114和第6个取电单元114的间距、第9个取电单元114和第10个取电单元114、第13个取电单元114和第14个取电单元114的间距，可以将第二分布区中第1至5个取电单元114分为第一个子区域，该子区域包括呈5行3列排布的15个芯片111；将第6至9个取电单元114分为第二个子区域，该子区域包括呈4行3列排布的12个芯片111；将第10至13个取电单元114分为第三个子区域，该子区域同样包括呈4行3列排布的12个芯片111；将第14至18个取电单元114分为第四个子区域，该子区域包括呈5行3列排布的15个芯片111。
由此，在串联方向上，可以根据相邻取电单元114之间的间距对第二分布区中的18个取电单元114进行分割，将18个取电单元114分为4个子区域，各子区域中的取电单元114可以等间距排布，相邻两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片111的温度，进而减小子区域内多个芯片111之间的温差。
沿并联方向，各分布区的取电单元114数量可以减小。如图3所示，第一分布区中取电单元114的数量可以为21，第二分布区中取电单元114的数量可以为18。当然，本申请不限于此，在分布区的取电单元114数量大于2的情况下，各分布区的取电单元114数量可以依次逐渐减小，可以部分逐渐减小，也可以部分减小。以分布区数量为6进行说明。沿并联方向，多个分布区的取电单元114数量可以分别为15，14，13，12，11，10；或者，多个分布区的取电单元114数量可以分别为12，12，11，11，10，10；又或者，多个分布区的取电单元114数量可以分别为11，10，10，10，10，10。
相邻取电单元114之间可以设置有金属件，沿串联方向，至少部分相邻取电单元114之间的金属件长于其他相邻取电单元114，其中，长方向与并联方向垂直。例如，金属件可以为铜片。由此，如此设置的金属件可以减小电流通道的电阻，减小电流通道的电压降，从而减小电流通道上的能量损耗。
其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。沿串联方向，第一分布区端部的3个芯片111与对应的子区域端部的3个芯片111的中心在一条直线上。相邻两个子区域之间的间隙分别与第一分布区的第6行、第11行和第16行芯片111在第一方向上对应。
也就是说，芯片阵列中的117个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的行间距相同，后3列芯片111的第6行、第11行和第16行缺失。前3列芯片111的数量为63个，后3列芯片111的数量为54个。芯片阵列的行方向为可以为散热方向。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，同样可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
其中，沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图3中，电路板110上的117个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。第6行、第11行和第16行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第6行、第11行和第16行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第二分布区中第5个取电单元114和第6个取电单元114的对应位置、第9个取电单元114和第10个取电单元114的对应位置以及第13个取电单元114和第14个取电单元114的对应位置。
实施例四
图4示出根据本申请实施例四的电路板110的结构示意图。如图4所示，电路板 110上芯片阵列的芯片111数量为120个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分布区。具体地，第一分布区包括呈22行3列排布的66个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括22个取电单元114。第一分布区中各取电单元114的间距可以相等。第二分布区包括呈18行3列排布的54个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括18个取电单元114。在串联方向上，第二分布区的第4个取电单元114和第5个取电单元114的间距、第7个取电单元114和第8个取电单元114的间距、第11个取电单元114和第12个取电单元114的间距以及第14个取电单元114和第15个取电单元114的间距可以大于其他相邻取电单元114的间距。
其中，在与并联方向垂直的方向上，上述“其他相邻取电单元114”为芯片阵列中非边缘的取电单元114。其他相邻取电单元114的间距可以为同一列设置的第1至4个取电单元114的间距、第5至7个取电单元114的间距、第8至11个取电单元114的间距、第12至14个取电单元114的间距以及第15至18个取电单元114的间距。在图4中，并联方向为行方向。
基于第4个取电单元114和第5个取电单元114的间距、第7个取电单元114和第8个取电单元114的间距、第11个取电单元114和第12个取电单元114的间距以及第14个取电单元114和第15个取电单元114的间距，可以将第二分布区中第1至4个取电单元114分为第一个子区域，该子区域包括呈4行3列排布的12个芯片111；将第5至7个取电单元114分为第二个子区域，该子区域包括呈3行3列排布的9个芯片111；将第8至11个取电单元114分为第三个子区域，该子区域包括呈4行3列排布的12个芯片111；将第12至14个取电单元114分为第四个子区域，该子区域包括呈3行3列排布的9个芯片111；将第15至18个取电单元114分为第五个子区域，该子区域包括呈4行3列排布的12个芯片111。
由此，在串联方向上，可以根据相邻取电单元114之间的间距对第二分布区中的18个取电单元114进行分割，将18个取电单元114分为5个子区域，各子区域中的取电单元114可以等间距排布，相邻两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片111的温度，进 而减小子区域内多个芯片111之间的温差。
沿并联方向，各分布区的取电单元114数量可以减小。如图4所示，第一分布区中取电单元114的数量可以为22，第二分布区中取电单元114的数量可以为18。当然，本申请不限于此，在分布区的取电单元114数量大于2的情况下，各分布区的取电单元114数量可以依次逐渐减小，可以部分逐渐减小，也可以部分减小。以分布区数量为6进行说明。沿并联方向，多个分布区的取电单元114数量可以分别为15，14，13，12，11，10；或者，多个分布区的取电单元114数量可以分别为12，12，11，11，10，10；又或者，多个分布区的取电单元114数量可以分别为11，10，10，10，10，10。
相邻取电单元114之间可以设置有金属件，沿串联方向，至少部分相邻取电单元114之间的金属件长于其他相邻取电单元114，其中，长方向与并联方向垂直。例如，金属件可以为铜片。由此，如此设置的金属件可以减小电流通道的电阻，减小电流通道的电压降，从而减小电流通道上的能量损耗。
其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。沿串联方向，第一分布区端部的3个芯片111与对应的子区域端部的3个芯片111的中心在一条直线上。相邻两个子区域之间的间隙分别与第一分布区的第5行、第9行、第14行芯片111和第18行芯片111在第一方向上对应。
也就是说，芯片阵列中的120个芯片111呈22行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的行间距相同，后3列芯片111的第5行、第9行、第14行芯片111和第18行缺失。前3列芯片111的数量为66个，后3列芯片111的数量为54个。芯片阵列的行方向为可以为散热方向。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，同样可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
其中，沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图4中，电路板110上的120个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的散热方向。第5行、第9行、第14行芯片111和第18行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第5行、第9行、第14行芯片111和第18行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第二分布区中第4个取电单元114和第5个取电单元114之间的对应位置、第7个取电单元114和第8个取电单元114之间的对应位置、第11个取电单元114和第12个取电单元114之间的对应位置以及第14个取电单元114和第15个取电单元114之间的对应位置。
实施例五
图5示出根据本申请实施例五的电路板110的结构示意图。如图5所示，电路板110上芯片阵列的芯片111数量为120个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分布区。具体地，第一分布区包括呈22行3列排布的66个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括22个取电单元114。第一分布区中各取电单元114的间距可以相等。第二分布区包括呈18行3列排布的54个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括18个取电单元114。在串联方向上，第二分布区的第4个取电单元114和第5个取电单元114的间距、第7个取电单元114和第8个取电单元114的间距、第10个取电单元114和第11个取电单元114的间距以及第14个取电单元114和第15个取电单元114的间距可以大于其他相邻取电单元114的间距。
其中，在与并联方向垂直的方向上，上述“其他相邻取电单元114”为芯片阵列中非边缘的取电单元114。其他相邻取电单元114的间距可以为同一列设置的第1至4个取电单元114的间距、第5至7个取电单元114的间距、第8至10个取电单元114的间距、第11至14个取电单元114的间距以及第15至18个取电单元114的间距。在图5中，并联方向为行方向。
基于第4个取电单元114和第5个取电单元114的间距、第7个取电单元114和第8个取电单元114的间距、第10个取电单元114和第11个取电单元114的间距以及第14个取电单元114和第15个取电单元114的间距，可以将第二分布区中第1至4个取电单元114分为第一个子区域，该子区域包括呈4行3列排布的12个芯片111； 将第5至7个取电单元114分为第二个子区域，该子区域包括呈3行3列排布的9个芯片111；将第8至10个取电单元114分为第三个子区域，该子区域包括呈3行3列排布的9个芯片111；将第11至14个取电单元114分为第四个子区域，该子区域包括呈4行3列排布的12个芯片111；将第15至18个取电单元114分为第五个子区域，该子区域包括呈4行3列排布的12个芯片111。
由此，在串联方向上，可以根据相邻取电单元114之间的间距对第二分布区中的18个取电单元114进行分割，将18个取电单元114分为5个子区域，各子区域中的取电单元114可以等间距排布，相邻两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片111的温度，进而减小子区域内多个芯片111之间的温差。
沿并联方向，各分布区的取电单元114数量可以减小。如图5所示，第一分布区中取电单元114的数量可以为22，第二分布区中取电单元114的数量可以为18。
其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。沿串联方向，第一分布区端部的3个芯片111与对应的子区域端部的3个芯片111的中心在一条直线上。相邻两个子区域之间的间隙分别与第一分布区的第5行、第9行、第13行芯片111和第18行芯片111在第一方向上对应。
也就是说，芯片阵列中的120个芯片111呈22行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的行间距相同，后3列芯片111的第5行、第9行、第13行芯片111和第18行缺失。前3列芯片111的数量为66个，后3列芯片111的数量为54个。芯片阵列的行方向为可以为散热方向。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，同样可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
其中，沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取 电单元114对应设置。
在图5中，电路板110上的120个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的散热方向。第5行、第9行、第13行芯片111和第18行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第5行、第9行、第13行芯片111和第18行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第二分布区中第4个取电单元114和第5个取电单元114之间的对应位置、第7个取电单元114和第8个取电单元114之间的对应位置、第10个取电单元114和第11个取电单元114之间的对应位置以及第14个取电单元114和第15个取电单元114之间的对应位置。
实施例六
图6A和图6B示出根据本申请实施例六的电路板110的结构示意图。如图6A和图6B所示，电路板110上芯片阵列的芯片111数量为117个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分布区。具体地，第一分布区包括呈20行3列排布的60个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括20个取电单元114。第一分布区中的20个取电单元114之间的距离可以相等。第二分布区包括呈19行3列排布的57个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括19个取电单元114。在列方向上，第一分布区的第10个取电单元114和第11个取电单元114的间距可以大于其他相邻取电单元114的间距；第二分布区的第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距可以大于其他相邻取电单元114的间距。在图6A中，并联方向为行方向。
基于第一分布区的第10个取电单元114和第11个取电单元114的间距，可以将第一分布区分为两个子区域，各子区域分别包括呈10行3列排布的20个芯片111。基于第二分布区中第7个取电单元114和第8个取电单元114的间距以及第12个取电单元114和第13个取电单元114的间距，可以将第二分布区中第1至7个取电单元114分为第一个子区域，该子区域包括呈7行3列排布的21个芯片111；将第8至12个取电单元114分为第二个子区域，该子区域包括呈5行3列排布的15个芯片111；将第13至19个取电单元114分为第三个子区域，该子区域同样包括呈7行3列排布的21 个芯片111。
由此，在串联方向上，可以根据相邻取电单元114之间的间距对第一分布区以及第二分布区中的取电单元114进行分割，将第一分布区中的20个取电单元114分割为两个子区域，且将第二分布区中的19个取电单元114分为三个子区域，各子区域中的取电单元114可以等间距排布，相邻两个子区域之间的间距可以大于各子区域中相邻取电单元114的间距，从而使得各子区域内位于串联方向两端的芯片111与中心位置的芯片111之间的距离较小，有效降低各子区域内位于中心位置的芯片111的温度，进而减小子区域内多个芯片111之间的温差。
沿并联方向，各分布区的取电单元114数量可以减小。如图6A所示，第一分布区中取电单元114的数量可以为20，第二分布区中取电单元114的数量可以为19。其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。
结合图6A，芯片阵列中的117个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第11行缺失，后3列芯片111的第8行和第14行缺失。前3列芯片111的数量为60个，后3列芯片111的数量为57个。芯片阵列的行方向为可以为散热方向。这样，靠近入风口的前半部分芯片111总数大于靠近出风口的后半部分芯片111总数，同样可以降低靠近出风口的芯片111与靠近入风口的芯片111的最大温差，从而提升芯片111的均温性。
沿垂直于散热方向，第二分布区分布在两个端部区域和一个中间区域。各端部区域的芯片111数量大于等于中间区域的芯片111数量。在图6A中，端部区域的芯片111即为第一个子区域中的芯片111以及第三个子区域中的芯片111，中间区域的芯片111即为第二个子区域中的芯片111。端部区域的芯片111数量分别为21个，中间区域的芯片111数量为15个。由此，由于在电路板110应用于电子设备3100的情况下，两端区域的芯片111与外部环境距离较近，散热更好，通过使端部区域布置数量较多的芯片111，且中间区域布置数量较少的芯片111，可以有效降低中间区域的芯片111温度，从而减小中间区域的芯片111以及端部区域的芯片111的温差，提升电路板110散热效果，保证电路板110的整体性能。
其中，沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图6A中，电路板110上的117个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。第8行、第11行和第14行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第8行、第11行和第14行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第一分布区中第10个取电单元114和第11个取电单元114之间的对应位置、第二分布区中第7个取电单元114和第8个取电单元114之间的对应位置以及第12个取电单元114和第13个取电单元114之间的对应位置。
实施例七
图7示出根据本申请实施例七的电路板110的结构示意图。如图7所示，电路板110上芯片阵列的芯片111数量为117个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分布区。具体地，第一分布区包括呈20行3列排布的60个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括20个取电单元114。第一分布区中的20个取电单元114之间的距离可以相等。第二分布区包括呈19行3列排布的57个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括19个取电单元114。在列方向上，第一分布区的第10个取电单元114和第11个取电单元114的间距可以大于其他相邻取电单元114的间距；第二分布区的第6个取电单元114和第7个取电单元114的间距以及第13个取电单元114和第14个取电单元114的间距可以大于其他相邻取电单元114的间距。在图7中，并联方向为行方向。
基于第一分布区的第10个取电单元114和第11个取电单元114的间距，可以将第一分布区分为两个子区域，各子区域分别包括呈10行3列排布的20个芯片111。基于第二分布区中第6个取电单元114和第7个取电单元114的间距以及第13个取电单元114和第14个取电单元114的间距，可以将第二分布区中第1至6个取电单元114分为第一个子区域，该子区域包括呈6行3列排布的18个芯片111；将第7至13个取 电单元114分为第二个子区域，该子区域包括呈7行3列排布的21个芯片111；将第14至19个取电单元114分为第三个子区域，该子区域包括呈6行3列排布的18个芯片111。
沿并联方向，各分布区的取电单元114数量可以减小。如图7所示，第一分布区中取电单元114的数量可以为20，第二分布区中取电单元114的数量可以为19。其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。
结合图7，芯片阵列中的117个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第11行缺失，后3列芯片111的第7行和第15行缺失。前3列芯片111的数量为60个，后3列芯片111的数量为57个。芯片阵列的行方向为可以为散热方向。
沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图7中，电路板110上的117个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。第7行、第11行和第15行芯片111的数量分别为3个，其他各行芯片111的数量为6个，因而第7行、第11行和第15行芯片111的数量小于其他行芯片111的数量。其中，至少部分凸台可以设置于第一分布区中第10个取电单元114和第11个取电单元114之间的对应位置、第二分布区中第6个取电单元114和第7个取电单元114之间的对应位置以及第13个取电单元114和第14个取电单元114之间的对应位置。
实施例八
图8示出根据本申请实施例八的电路板110的结构示意图。如图8所示，电路板110上芯片阵列的芯片111数量为114个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分 布区。具体地，第一分布区包括呈20行3列排布的60个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括20个取电单元114。第一分布区中的20个取电单元114之间的距离可以相等。第二分布区包括呈18行3列排布的54个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括18个取电单元114。在列方向上，第一分布区的第10个取电单元114和第11个取电单元114的间距可以大于其他相邻取电单元114的间距；第二分布区的第5个取电单元114和第6个取电单元114的间距、第9个取电单元114和第10个取电单元114的间距以及第13个取电单元114和第14个取电单元114的间距可以大于其他相邻取电单元114的间距。在图8中，并联方向为行方向。
基于第一分布区的第10个取电单元114和第11个取电单元114的间距，可以将第一分布区分为两个子区域，各子区域分别包括呈10行3列排布的20个芯片111。基于第二分布区中第5个取电单元114和第6个取电单元114的间距、第9个取电单元114和第10个取电单元114的间距以及第13个取电单元114和第14个取电单元114的间距，可以将第二分布区中第1至5个取电单元114分为第一个子区域，该子区域包括呈5行3列排布的15个芯片111；将第6至9个取电单元114分为第二个子区域，该子区域包括呈4行3列排布的12个芯片111；将第10至13个取电单元114分为第三个子区域，该子区域包括呈4行3列排布的12个芯片111；将第14至18个取电单元114分为第四个子区域，该子区域包括呈5行3列排布的15个芯片111。
沿并联方向，各分布区的取电单元114数量可以减小。如图8所示，第一分布区中取电单元114的数量可以为20，第二分布区中取电单元114的数量可以为18。其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。
结合图7，芯片阵列中的114个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第11行缺失，后3列芯片111的第6行、第11行和第16行缺失。前3列芯片111的数量为60个，后3列芯片111的数量为54个。芯片阵列的行方向为可以为散热方向。
沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面 与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图8中，电路板110上的114个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。其中，至少部分凸台可以设置于第一分布区中第10个取电单元114和第11个取电单元114之间的对应位置、第二分布区中第5个取电单元114和第6个取电单元114之间的对应位置、第9个取电单元114和第10个取电单元114之间的对应位置以及第13个取电单元114和第14个取电单元114之间的对应位置。
实施例九
图9示出根据本申请实施例九的电路板110的结构示意图。如图9所示，电路板110上芯片阵列的芯片111数量为120个。芯片阵列包括多个由并联芯片111构成的取电单元114，多个取电单元114串联连接。其中，至少部分相邻取电单元114之间的距离不相等。
具体地，芯片阵列包括靠近入风口设置的第一分布区和靠近出风口设置的第二分布区。具体地，第一分布区包括呈20行3列排布的60个芯片111，第一分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第一分布区包括20个取电单元114。第一分布区中的20个取电单元114之间的距离可以相等。第二分布区包括呈18行3列排布的54个芯片111，第二分布区中每行的3个芯片111并联连接，构成1个取电单元114，因而第二分布区包括18个取电单元114。在列方向上，第一分布区的第10个取电单元114和第11个取电单元114的间距可以大于其他相邻取电单元114的间距；第二分布区的第5个取电单元114和第6个取电单元114的间距、第9个取电单元114和第10个取电单元114的间距以及第13个取电单元114和第14个取电单元114的间距可以大于其他相邻取电单元114的间距。在图8中，并联方向为行方向。
基于第一分布区的第10个取电单元114和第11个取电单元114的间距，可以将第一分布区分为两个子区域，各子区域分别包括呈10行3列排布的20个芯片111。基于第二分布区中第5个取电单元114和第6个取电单元114的间距、第9个取电单元114和第10个取电单元114的间距以及第13个取电单元114和第14个取电单元114的间距，可以将第二分布区中第1至5个取电单元114分为第一个子区域，该子区域包括呈5行3列排布的15个芯片111；将第6至9个取电单元114分为第二个子区域，该子区域包括呈4行3列排布的12个芯片111；将第10至13个取电单元114分为第三个子区域，该子区域包括呈4行3列排布的12个芯片111；将第14至18个取电单元114分为第四个子区域，该子区域包括呈5行3列排布的15个芯片111。
沿并联方向，各分布区的取电单元114数量可以减小。如图8所示，第一分布区中取电单元114的数量可以为20，第二分布区中取电单元114的数量可以为18。其中，各分布区内芯片111的行间距相同，各行中的多个芯片111的中心在一条直线上。
结合图9，芯片阵列中的114个芯片111呈21行6列排布，各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第11行缺失，后3列芯片111的第6行、第11行和第16行缺失。前3列芯片111的数量为60个，后3列芯片111的数量为54个。芯片阵列的行方向为可以为散热方向。
沿并联方向，第一分布区与第二分布区之间的距离可以大于各分布区内相邻两列芯片111之间的距离；或者，沿并联方向，第一分布区与第二分布区之间的距离可以等于各分布区内相邻两列芯片111之间的距离；又或者，沿并联方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
电路板110可以应用于工作组件2100。其中，工作组件2100可以包括散热器2110。散热器2110包括散热主体和散热鳍片，散热主体包括相对的第一面和第二面，第一面与散热鳍片连接，第二面设置有多个凸台，各凸台可以与各行取电单元114或各列取电单元114对应设置。
在图9中，电路板110上的114个芯片111呈多行排布，行方向平行于散热风道的入风口到出风口的方向。其中，至少部分凸台可以设置于第一分布区中第10个取电单元114和第11个取电单元114之间的对应位置、第二分布区中第5个取电单元114和第6个取电单元114之间的对应位置、第9个取电单元114和第10个取电单元114之间的对应位置以及第13个取电单元114和第14个取电单元114之间的对应位置。
电路板110包括两个靠近入风口设置第一芯片阵列和四个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。两个第一芯片阵列在第二方向上间隔设置，四个第二芯片阵列在第二方向上间隔设置，且相邻两个第一芯片阵列之间的距离以及相邻两个第二芯片阵列之间的距离均大于芯片111的行间距。
在图9的示例中，其中一个第一芯片阵列包括呈10行3列排布的30个芯片111，另外一个第一芯片阵列包括呈11行3列排布的33个芯片111。各第一芯片阵列内芯片111的行间距相等，且各行中的三个芯片111的中心在一条直线上。沿第二方向，第一个第二芯片阵列、第三个第二芯片阵列和第四个第二芯片阵列分别包括呈5行3列排布的15个芯片111，第二个第二芯片阵列包括呈4行3列排布的12个芯片111。各第二芯片阵列内芯片111的行间距相等，各行中的三个芯片111的中心在一条直线上。 其中，第二个第二芯片阵列和第三个第二芯片阵列之间的间隙为第一间隙。两个第一芯片阵列之间的间隙与第一间隙在同一条直线上。
电路板110上设置有呈阵列排布的120个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第11行缺失，后3列芯片111的第6行、第11行和第17行缺失。前3列芯片111的数量为63个，后3列芯片111的数量为57个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十
图10示出根据本申请实施例十的电路板110的结构示意图。如图10所示，电路板110包括一个靠近入风口设置第一芯片阵列和三个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。三个第二芯片阵列在第二方向上间隔设置，且相邻两个第二芯片阵列之间的距离大于芯片111的行间距。
在图10的示例中，第一芯片阵列包括呈20行3列排布的60个芯片111。第一芯片阵列内芯片111的行间距相等，且各行中的三个芯片111的中心在一条直线上。沿第二方向，第一个第二芯片阵列和第三个第二芯片阵列分别包括呈7行3列排布的21个芯片111，第二个第二芯片阵列包括呈5行3列排布的15个芯片111。各第二芯片阵列内芯片111的行间距相等，各行中的三个芯片111的中心在一条直线上。沿第二方向，第一芯片阵列一端的3个芯片111与对应的第二芯片阵列端部的3个芯片111的中心不在一条直线上，第一芯片阵列另一端的3个芯片111与对应的第二芯片阵列端部的3个芯片111的中心在一条直线上。
电路板110上设置有呈阵列排布的117个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第1行缺失，后3列芯片111的第8行和第14行缺失。前3列芯片111的数量为60个，后3列芯片111的数量为57个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十一
图11示出根据本申请实施例十一的电路板110的结构示意图。如图11所示，电路板110包括一个靠近入风口设置第一芯片阵列和三个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。三个第二芯片阵列在第二方向上间隔设置，且相邻两个第二芯片阵列之间的距离大于芯片111的行间距。
在图11的示例中，第一芯片阵列包括呈19行3列排布的57个芯片111。第一芯片阵列内芯片111的行间距相等，且各行中的三个芯片111的中心在一条直线上。沿第二方向，第一个第二芯片阵列和第三个第二芯片阵列分别包括呈7行3列排布的21个芯片111，第二个第二芯片阵列包括呈5行3列排布的15个芯片111。各第二芯片阵列内芯片111的行间距相等，各行中的三个芯片111的中心在一条直线上。第一芯片阵列端部的3个芯片111与对应的第二芯片阵列端部的3个芯片111的中心不在一条直线上。
电路板110上设置有呈阵列排布的114个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第1行和第22行缺失，后3列芯片111的第8行和第14行缺失。前3列芯片111的数量为57个，后3列芯片111的数量为57个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十二
图12示出根据本申请实施例十二的电路板110的结构示意图。如图12所示，电路板110包括三个靠近入风口设置第一芯片阵列和三个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。三个第一芯片阵列在第二方向上间隔设置，三个第二芯片阵列在第二方向上间隔设置，且相邻两个第一芯片阵列之间的距离以及相邻两个第二芯片阵列之间的距离均大于芯片111的行间距。
在图12的示例中，沿第二方向，位于端部的各第一芯片阵列包括呈7行3列排布的21个芯片111，位于中部的第一芯片阵列包括呈5行3列排布的15个芯片111。各第一芯片阵列内芯片111的行间距相等，且各行中的三个芯片111的中心在一条直线上。沿第二方向，位于端部的各第二芯片阵列包括呈7行3列排布的21个芯片111，位于中部的第二芯片阵列包括呈5行3列排布的15个芯片111。各第二芯片阵列内芯 片111的行间距相等，各行中的三个芯片111的中心在一条直线上。其中，相邻两个第一芯片阵列之间的间隙与相邻两个第二芯片阵列之间的间隙位于同一条直线上。
电路板110上设置有呈阵列排布的114个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第8行和第14行缺失，后3列芯片111的第8行和第14行缺失。前3列芯片111的数量为57个，后3列芯片111的数量为57个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十三
图13示出根据本申请实施例十三的电路板110的结构示意图。如图13所示，电路板110包括三个靠近入风口设置第一芯片阵列和三个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。三个第一芯片阵列在第二方向上间隔设置，三个第二芯片阵列在第二方向上间隔设置，且相邻两个第一芯片阵列之间的距离以及相邻两个第二芯片阵列之间的距离均大于芯片111的行间距。
在图13的示例中，沿第二方向，位于端部的各第一芯片阵列包括呈6行3列排布的18个芯片111，位于中部的第一芯片阵列包括呈7行3列排布的21个芯片111。各第一芯片阵列内芯片111的行间距相等，且各行中的三个芯片111的中心在一条直线上。沿第二方向，位于端部的各第二芯片阵列包括呈7行3列排布的21个芯片111，位于中部的第二芯片阵列包括呈5行3列排布的15个芯片111。各第二芯片阵列内芯片111的行间距相等，各行中的三个芯片111的中心在一条直线上。其中，相邻两个第一芯片阵列之间的间隙与相邻两个第二芯片阵列之间的间隙错开布置。
电路板110上设置有呈阵列排布的114个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第7行和第15行缺失，后3列芯片111的第8行和第14行缺失。前3列芯片111的数量为57个，后3列芯片111的数量为57个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十四
图14示出根据本申请实施例十四的电路板110的结构示意图。如图14所示，电路板110包括三个靠近入风口设置第一芯片阵列和四个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。三个第一芯片阵列在第二方向上间隔设置，四个第二芯片阵列在第二方向上间隔设置，且相邻两个第一芯片阵列之间的距离以及相邻两个第二芯片阵列之间的距离均大于芯片111的行间距。
在图14的示例中，沿第二方向，位于端部的各第一芯片阵列包括呈7行3列排布的21个芯片111，位于中部的第一芯片阵列包括呈6行3列排布的18个芯片111。各第一芯片阵列内芯片111的行间距相等，且各行中的三个芯片111的中心在一条直线上。沿第二方向，第一个第二芯片阵列、第三个第二芯片阵列和第四个第二芯片阵列分别包括呈5行3列排布的15个芯片111，第二个第二芯片阵列包括呈4行3列排布的12个芯片111。各第二芯片阵列内芯片111的行间距相等，各行中的三个芯片111的中心在一条直线上。其中，相邻两个第一芯片阵列之间的间隙与相邻两个第二芯片阵列之间的间隙错开布置。
电路板110上设置有呈阵列排布的117个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第8行和第15行缺失，后3列芯片111的第6行、第11行和第17行缺失。前3列芯片111的数量为60个，后3列芯片111的数量为57个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十五
图15示出根据本申请实施例十五的电路板110的结构示意图。如图15所示，电路板110包括四个靠近入风口设置第一芯片阵列和五个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。四个第一芯片阵列在第二方向上间隔设置，五个第二芯片阵列在第二方向上间隔设置，且相邻两个第一芯片阵列之间的距离以及相邻两个第二芯片阵列之间的距离均大于芯片111的行间距。
在图15的示例中，沿第二方向，第一个第一芯片阵列和第四个第一芯片阵列分别包括呈5行3列排布的15个芯片111，第二个第一芯片阵列和第三个第一芯片阵列分别包括呈4行3列排布的12个芯片111。各第一芯片阵列内芯片111的行间距相等， 且各行中的三个芯片111的中心在一条直线上。沿第二方向，第一个第二芯片阵列包括呈2行3列排布的6个芯片111；第二个第二芯片阵列、第三个第二芯片阵列和第五个第二芯片阵列分别包括呈4行3列排布的12个芯片111，第四个第二芯片阵列包括呈3行3列排布的3个芯片111。各第二芯片阵列内芯片111的行间距相等，各行中的三个芯片111的中心在一条直线上。其中，相邻两个第一芯片阵列之间的间隙与相邻两个第二芯片阵列之间的间隙错开布置。
电路板110上设置有呈阵列排布的105个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第6行、第11行和第16行缺失，后3列芯片111的第3行、第8行、第13行和第17行缺失。前3列芯片111的数量为54个，后3列芯片111的数量为51个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十六
图16示出根据本申请实施例十六的电路板110的结构示意图。如图16所示，电路板110包括六个靠近入风口设置第一芯片阵列和六个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。六个第一芯片阵列在第二方向上间隔设置，六个第二芯片阵列在第二方向上间隔设置，且相邻两个第一芯片阵列之间的距离以及相邻两个第二芯片阵列之间的距离均大于芯片111的行间距。
在图16的示例中，沿第二方向，第一个至第五个第一芯片阵列分别包括呈3行3列排布的9个芯片111，第一个第一芯片阵列包括呈2行3列排布的9个芯片111，第六个第一芯片阵列包括呈1行3列排布的3个芯片111。各第一芯片阵列内芯片111的行间距相等，且各行中的三个芯片111的中心在一条直线上。沿第二方向，第一个第一芯片阵列包括呈1行3列排布的3个芯片111，第二个至第六个第二芯片阵列分别包括呈3行3列排布的9个芯片111。各第二芯片阵列内芯片111的行间距相等，各行中的三个芯片111的中心在一条直线上。其中，相邻两个第一芯片阵列之间的间隙与相邻两个第二芯片阵列之间的间隙错开布置。
电路板110上设置有呈阵列排布的93个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，前3列芯片111的第一行、第4行、第8行、第12行、第16行和第20行缺失，后3列芯片111的第2行、第6行、第10 行、第14行和第18行缺失。前3列芯片111的数量为45个，后3列芯片111的数量为48个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十七
图17示出根据本申请实施例十七的电路板110的结构示意图。如图17所示，电路板110包括三个靠近入风口设置第一芯片阵列和一个靠近出风口设置的第二芯片阵列。第一芯片阵列和第二芯片阵列内的多个芯片111均呈行排布。两个第一芯片阵列在第二方向上间隔设置，且两个第一芯片阵列之间的距离大于芯片111的行间距。
在图17的示例中，沿第二方向，位于端部的各第一芯片阵列包括呈7行3列排布的21个芯片111，位于中部的第一芯片阵列包括呈5行3列排布的15个芯片111，各第一芯片阵列内芯片111的行间距相等。第二芯片阵列包括呈21行3列排布的63个芯片111，第二芯片阵列中芯片111的行间距相等，且各行中的多个芯片111的中心在一条直线上。沿第二方向，第一芯片阵列端部的3个芯片111与对应的第二芯片阵列端部的3个芯片111的中心在一条直线上。相邻两个第一芯片阵列之间的间隙分别与第二芯片阵列的第8行和第14行芯片111在第一方向上对应。
也就是说，电路板110上共设置呈21行6列排布的120个芯片111。各行芯片111的中心在一条直线上，各列芯片111的中心在一条直线上。其中，后3列芯片111的行间距相同，前3列芯片111的第8行和第14行缺失。前3列芯片111的数量为57个，后3列芯片111的数量为63个。
其中，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以大于各芯片阵列内相邻两列芯片111之间的距离；或者，沿第一方向，第一芯片阵列与第二芯片阵列之间的距离可以等于各芯片阵列内相邻两列芯片111之间的距离；又或者，沿第一方向，多列芯片111之间的距离可以逐渐增大或逐渐减小。
实施例十八
图18示出根据本申请实施例十八的电路板110的结构示意图。如图18所示，电路板110上共设置21行6列芯片111。其中，第六列芯片111的第10行、第11行和第12行缺失。前3列芯片111的数量为63个，后3列芯片111的数量为60个。其中，沿第一方向，相邻两列芯片111之间的距离可以逐渐增大；或者，沿第一方向，相邻 两列芯片111之间的距离可以逐渐减小；又或者，沿第一方向，第三列和第四列芯片111之间的距离大于其余相邻两列之间芯片111之间的距离；当然，不本申请不限于此，例如，还可以是沿第一方向，每相邻两列芯片111之间的距离相等，或者多个芯片111的列间距可以没有任何规律。
实施例十九
图19A示出根据本申请实施例十九的电路板110的结构示意图。如图19A所示，电路板110上共设置10列8行芯片111。芯片111的总数量为76个，第三列芯片111的第三至六行缺失。其中，沿第一方向即左右方向，相邻两列芯片111之间的距离可以逐渐增大；或者，沿第一方向，相邻两列芯片111之间的距离可以逐渐减小；又或者，沿第一方向，第三列和第四列芯片111之间的距离大于其余相邻两列之间芯片111之间的距离；当然，不本申请不限于此，例如，还可以是沿第一方向，每相邻两列芯片111之间的距离相等，或者多个芯片111的列间距可以没有任何规律。
图19B示出图19A所示的电路板110的电流图。如图19B所示，当散热方向为上下方向时，电路板110包括三个靠近入风口设置的第一芯片阵列和三个靠近出风口设置的第二芯片阵列。其中，位于第一方向边缘的第一芯片阵列包括10个芯片111组，位于第一方向中部的两个第二芯片阵列分别包括2个和7个芯片111组。位于第一方向边缘的第二芯片阵列包括10个芯片111组，位于第一方向中部的两个第二芯片阵列分别包括2个和7个芯片111组。每个芯片111组由并联的2个芯片111构成取电单元114。其中，沿各芯片111组的串联方向，相邻芯片阵列之间的电连接线长度大于相邻芯片111组之间的电连接线长度，且相邻芯片阵列之间的信号线116的长度大于相邻芯片111组之间的信号线116长度。
当散热方向为左右方向时，第一行和第二行芯片构成一个芯片阵列，第三行和第四行芯片被空缺位113划分为两个芯片阵列，第五行和第六行芯片被空缺位113划分为两个芯片阵列，第七行和第八行芯片构成一个芯片阵列。此时，芯片的并联方向与散热方向垂直，空缺位113处于芯片阵列中靠近出风口的位置。
实施例二十
图20示出根据本申请实施例二十的电路板110的结构示意图。如图20所示，电路板110上共设置11行12列芯片111。芯片111的总数量为129个，第一行芯片111的第十至十二列缺失。其中，沿第一方向即上下方向，相邻两列芯片111之间的距离可以逐渐增大；或者，沿第一方向，相邻两列芯片111之间的距离可以逐渐减小；又或者，沿第一方向，第三列和第四列芯片111之间的距离大于其余相邻两列之间芯片 111之间的距离；当然，不本申请不限于此，例如，还可以是沿第一方向，每相邻两列芯片111之间的距离相等，或者多个芯片111的列间距可以没有任何规律。
实施例二十一
图21A示出根据本申请实施例二十一的电路板110的结构示意图。如图21A所示，电路板110上芯片111的总数量为100个，第六行芯片111缺失。
图21B示出图21A所示的电路板110的电流图。如图21B所示，电路板110包括一个靠近入风口设置的第一芯片阵列和一个靠近出风口设置的第二芯片阵列。其中，第一芯片阵列和第二芯片阵列分别包括5个芯片111组。每个芯片111组由并联的10个芯片111构成取电单元114。其中，沿各芯片111组的串联方向，第一芯片阵列和第二芯片阵列之间的电连接线长度大于各芯片阵列中相邻芯片111组之间的电连接线长度，且相邻芯片阵列之间的信号线116的长度大于各芯片阵列中相邻芯片111组之间的信号线116长度。
上述实施例的电路板110和工作组件2100的其他构成可以采用于本领域普通技术人员现在和未来知悉的各种技术方案，这里不再详细描述。
在本说明书的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者多个该特征。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接，还可以是通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上 面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度小于第二特征。
上文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，上文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (142)

  1. 一种电路板，其特征在于，所述电路板上设置有芯片阵列，所述芯片阵列包括多个取电单元，所述取电单元包括至少一个芯片，其中，至少部分相邻取电单元之间的距离不相等。
  2. 根据权利要求1所述的电路板，其特征在于，所述芯片阵列中的芯片尺寸相同，所述芯片阵列中的芯片总数大于等于20个或50个。
  3. 根据权利要求1所述的电路板，其特征在于，至少部分相邻取电单元之间的距离大于或等于容纳一个芯片所需的间距。
  4. 根据权利要求1所述的电路板，其特征在于，沿散热方向，相邻取电单元之间的距离增加，和/或相邻芯片之间的距离增加。
  5. 根据权利要求1所述的电路板，其特征在于，所述取电单元包括多个芯片，所述取电单元的各芯片并联连接。
  6. 根据权利要求1所述的电路板，其特征在于，多个所述取电单元串联连接。
  7. 根据权利要求5所述的电路板，其特征在于，沿垂直于并联方向的方向，至少部分相邻取电单元之间的距离大于其他相邻取电单元之间的距离。
  8. 根据权利要求5所述的电路板，其特征在于，沿垂直于并联方向的方向，至少部分相邻取电单元之间的电连接线长度长于其他相邻取电单元之间的电连接线长度。
  9. 根据权利要求5所述的电路板，其特征在于，相邻所述取电单元之间设置有金属件，沿垂直于并联方向的方向，至少部分相邻取电单元之间的金属件长度长于其他相邻取电单元。
  10. 根据权利要求6所述的电路板，其特征在于，沿串联方向，至少部分相邻取电单元之间的距离大于其他相邻取电单元之间的距离。
  11. 根据权利要求6所述的电路板，其特征在于，沿串联方向，至少部分相邻取电单元之间的电连接线长度长于其他相邻取电单元之间的电连接线长度。
  12. 根据权利要求6所述电路板，其特征在于，相邻所述取电单元之间设置有金属件，沿串联方向，至少部分相邻取电单元之间的金属件长度长于其他相邻取电单元。
  13. 根据权利要求7至12任一项所述的电路板，其特征在于，所述其他相邻取电单元为同一行或同一列的相邻取电单元。
  14. 根据权利要求7至12任一项所述的电路板，其特征在于，所述其他相邻取电单元为所述芯片阵列中非边缘的取电单元。
  15. 根据权利要求1所述的电路板，其特征在于，在散热方向上，所述芯片阵列 所占电路板的矩形区域划分为多个分布区，至少两个所述分布区内的取电单元数量不相等。
  16. 根据权利要求15所述的电路板，其特征在于，当芯片行方向为所述散热方向时，各所述分布区的芯片列数相同；当芯片列方向为所述散热方向时，各所述分布区的芯片行数相同。
  17. 根据权利要求15所述的电路板，其特征在于，沿所述散热方向，多个分布区内的取电单元数量减小。
  18. 根据权利要求1所述的电路板，其特征在于，在垂直于散热方向上，所述芯片阵列所占电路板的矩形区域划分为多个子区域，至少部分相邻两个所述子区域的间距，与任一所述子区域内相邻取电单元的间距不相等。
  19. 根据权利要求18所述的电路板，其特征在于，至少部分相邻两个所述子区域的间距大于或等于容纳一个芯片所需的间距。
  20. 根据权利要求18所述的电路板，其特征在于，当芯片行方向为所述散热方向时，各子区域的芯片列数相同；当芯片列方向为所述散热方向时，各子区域的芯片行数相同。
  21. 根据权利要求18所述的电路板，其特征在于，至少两个所述子区域的取电单元数量不相等。
  22. 根据权利要求18所述的电路板，其特征在于，所述多个子区域包括两个端部区域和一个中间区域，所述端部区域的取电单元数量大于或等于所述中间区域的取电单元数量。
  23. 根据权利要求22所述的电路板，其特征在于，由所述中间区域向所述端部区域，所述取电单元的数量增加。
  24. 根据权利要求22所述的电路板，其特征在于，两个所述端部区域包括第一端部区域和第二端部区域，所述第一端部区域的取电单元数量小于所述第二端部区域的取电单元数量，其中，在所述电路板的垂直放置状态下，所述第一端部区域靠近所述电路板的顶部，所述第二端部区域靠近所述电路板的底部。
  25. 根据权利要求18所述的电路板，其特征在于，所述多个子区域包括两个端部区域和一个中间区域，所述端部区域的芯片数量大于或等于所述中间区域芯片数量。
  26. 根据权利要求18所述的电路板，其特征在于，所述多个子区域包括两个端部区域和一个中间区域，所述端部区域的平均芯片间距小于所述中间区域的平均芯片间距。
  27. 根据权利要求1所述的电路板，其特征在于，所述芯片阵列的行方向为所述取电单元的多个芯片并联方向。
  28. 根据权利要求1所述的电路板，其特征在于，所述芯片阵列的行方向为散热方向。
  29. 根据权利要求1所述的电路板，其特征在于，所述取电单元的多个芯片并联方向为散热方向。
  30. 根据权利要求1所述的电路板，其特征在于，所述芯片阵列的各芯片之间的工作温差范围为0～10℃。
  31. 根据权利要求1所述的电路板，其特征在于，每行所述芯片或每列所述芯片的中心在同一直线上。
  32. 一种电路板，其特征在于，所述电路板设置有芯片阵列，所述芯片阵列包括多个芯片及至少一个空缺位。
  33. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列中的芯片尺寸相同，所述芯片阵列中芯片总数大于等于20个或50个。
  34. 根据权利要求32所述的电路板，其特征在于，所述空缺位的尺寸大于或等于所述芯片阵列中的单颗芯片尺寸。
  35. 根据权利要求32所述的电路板，其特征在于，所述空缺位对应的空间可以容纳至少一个芯片。
  36. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列中至少部分相邻芯片间距不相等。
  37. 根据权利要求36所述的电路板，其特征在于，所述芯片阵列中至少部分相邻芯片间距不相等包括：
    至少一个所述空缺位设置于所述芯片阵列的行方向上，使所述芯片阵列中至少一行芯片中存在不相等的相邻芯片间距；和/或，
    至少一个所述空缺位设置于所述芯片阵列的列方向上，使所述芯片阵列中至少一列芯片中存在不相等的相邻芯片间距。
  38. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列包括多个取电单元，所述取电单元包括至少一个芯片。
  39. 根据权利要求38所述的电路板，其特征在于，所述取电单元包括多个芯片，所述取电单元内的芯片连接方式为并联。
  40. 根据权利要求38所述的电路板，其特征在于，多个所述取电单元串联连接。
  41. 根据权利要求38所述的电路板，所述空缺位的总数量是一个所述取电单元中所包含芯片数量的整数倍。
  42. 根据权利要求39所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，与所述空缺位前后相邻的两个所述取电单元之间的电连接线长度，长于其他相邻取电单元间的电连接线长度，其中，长度方向垂直于所述芯片阵列的芯片并联方向或平行于所述芯片阵列的芯片串联方向。
  43. 根据权利要求42所述的电路板，其特征在于，所述其他相邻取电单元位于相同行或相同列。
  44. 根据权利要求42所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述其他相邻取电单元为所述芯片阵列中非边缘的取电单元。
  45. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列设置为X*Y，所述芯片阵列的列方向上，列芯片数最大的数值为所述X，所述芯片阵列的行方向上，行芯片数最大的数值为所述Y。
  46. 根据权利要求45所述的电路板，其特征在于，所述芯片阵列中芯片数量及所述空缺位数量的总数为X*Y个。
  47. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列划分为至少两个部分，每个部分的芯片总数不完全相等。
  48. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列划分为至少两个部分，沿散热方向，每个部分的芯片总数减少。
  49. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列划分为至少两个部分，每个部分的行或列的数量不完全相等和/或每个部分芯片布局非对称。
  50. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列等分为两个部分，沿散热方向，前半部分的列平均间距小于后半部分的列平均间距。
  51. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列等分为两个部分，沿散热方向，前半部分与后半部分的芯片行数和/或芯片数量和/或空缺位数量不相等。
  52. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列等分为两个部分，沿散热方向，前半部分大于后半部分的芯片行数和/或芯片数量。
  53. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列等分为两个部分，沿散热方向，前半部分等于后半部分的芯片行数和/或芯片数量。
  54. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列等分为两个部分，沿散热方向，前半部分小于或等于后半部分的空缺位数量。
  55. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列等分为两个部分，沿散热方向，前半部分与后半部分至少部分行空缺位在同一直线上。
  56. 根据权利要求45所述的电路板，其特征在于，还包括：
    所述行芯片数最大的数值Y将所述芯片阵列等分为两个部分，沿散热方向，前半部分与后半部分至少部分行空缺位不在同一直线上。
  57. 根据权利要求32所述的电路板，其特征在于，还包括：
    沿散热方向，所述空缺位位于所述芯片阵列的上边缘和/或下边缘。
  58. 根据权利要求32所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于散热方向上或垂直所述芯片阵列的芯片并联方向上，所述芯片阵列所占电路板区域划分为多个子区域，至少部分相邻两个所述子区域之间存在所述空缺位。
  59. 根据权利要求58所述的电路板，其特征在于，所述多个子区域包括两个端部区域和一个中间区域。
  60. 根据权利要求59所述的电路板，其特征在于，所述端部区域的芯片数量大于或等于所述中间区域芯片数量。
  61. 根据权利要求59所述的电路板，其特征在于，所述端部区域的平均芯片间距小于所述中间区域的平均芯片间距。
  62. 根据权利要求59所述的电路板，其特征在于，所述芯片阵列的列芯片数最大的数值为X，基于X将所述芯片阵列所占电路板区域分为两个端部区域和一个中间区域。
  63. 根据权利要求59所述的电路板，其特征在于，所述芯片阵列所占电路板区域在垂直散热方向上的高度为H；基于H将所述芯片阵列所占电路板区域分为两个端部区域和一个中间区域。
  64. 根据权利要求59所述的电路板，其特征在于，两个所述端部区域包括第一端部区域和第二端部区域，所述第一端部区域的芯片数量小于所述第二端部区域的芯片数量，其中，在所述电路板的垂直放置状态下，所述第一端部区域靠近所述电路板的顶部，所述第二端部区域靠近所述电路板的底部。
  65. 根据权利要求58所述的电路板，其特征在于，各所述子区域内对应芯片的行数相同或列数相同。
  66. 根据权利要求58所述的电路板，其特征在于，至少两个所述子区域对应的芯片数量不相等。
  67. 根据权利要求58所述的电路板，其特征在于，各所述子区域的芯片数量由中间向两端区域增加。
  68. 根据权利要求32所述的电路板，其特征在于，所述电路板上，每个所述空缺位分别对应一个焊接盘。
  69. 根据权利要求32所述的电路板，其特征在于，所述空缺位对应设置导电金属件。
  70. 根据权利要求69所述的电路板，其特征在于，多个连续的所述空缺位上不能共用同一个导电金属件。
  71. 根据权利要求69所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，与所述空缺位前后相邻的两个芯片之间的金属件长度，长于未间隔空缺位的相邻芯片间设置的金属件长度，其中，长方向与所述并联方向垂直。
  72. 根据权利要求71所述的电路板，其特征在于，所述未间隔空缺位的相邻芯片为同一行或同一列。
  73. 根据权利要求71所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述未间隔空缺位的相邻芯片，为所述芯片阵列中非边缘的芯片。
  74. 根据权利要求32所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，与所述空缺位前后相邻的两个芯片之间的信号线长度，长于未间隔空缺位的相邻芯片间的信号线长度；和/或，与所述空缺位相邻的两个芯片之间的电源线长度，长于未间隔空缺位的相邻芯片间的电源线长度；其中，长度方向垂直于所述芯片阵列的芯片并联方向或平行于所述芯片阵列的芯片串联方向。
  75. 根据权利要求74所述的电路板，其特征在于，所述未间隔空缺位的相邻芯片为同一行或同一列。
  76. 根据权利要求74所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述未间隔空缺位的相邻芯片，为所述芯片阵列中非边缘的芯片。
  77. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列的各芯片之间的工作温差范围为0～10℃。
  78. 根据权利要求32所述的电路板，其特征在于，所述空缺位为3个及以上。
  79. 根据权利要求32所述的电路板，其特征在于，沿散热方向，至少部分相邻空缺位之间的距离不相等或相邻空缺位间距增大。
  80. 根据权利要求32所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述空缺位为所述芯片阵列中非边缘的芯片。
  81. 根据权利要求32所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，空缺位前后相邻的芯片以外的其他非空缺位相邻芯片间距相等。
  82. 根据权利要求32所述的电路板，其特征在于，在所述芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，在所述空缺位补齐芯片后的前后相邻芯片间距大于或等于其他非空缺位相邻芯片间距。
  83. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列中的芯片呈行列排布，每行或每列芯片的中心在同一直线上。
  84. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列中的芯片呈行列排布，每一个所述空缺位的中心与行或列在同一直线上。
  85. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列中的芯片呈行列排布，每一个空缺位，均设置在所述芯片阵列行列的交叉点上。
  86. 根据权利要求32所述的电路板，其特征在于，沿散热方向，所述芯片阵列中，所述电路板上远离散热源的区域，所述空缺位的数量增多。
  87. 根据权利要求32所述的电路板，其特征在于，沿散热方向，所述芯片阵列中，越远离散热源，在垂直散热方向上的芯片数量减少。
  88. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列中，环境温度高低与所述空缺位的数量多少呈正比，所述电路板上，环境温度越高的区域，设置的所 述空缺位的数量越多。
  89. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列中，所述空缺位的数量多少与所述空缺位所处区域的芯片密度负相关。
  90. 根据权利要求32所述的电路板，其特征在于，所述电路板上对应的所述空缺位所占区域内，不设置芯片。
  91. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列的行方向为芯片的散热方向。
  92. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列的列方向为垂直芯片的散热方向。
  93. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列的行方向为芯片并联方向。
  94. 根据权利要求32所述的电路板，其特征在于，所述芯片阵列的芯片并联方向为芯片的散热方向。
  95. 一种电路板，其特征在于，所述电路板上设置有多个芯片组，各所述芯片组包括至少一行芯片和/或至少一列芯片，至少部分相邻所述芯片组的间距，与任一所述芯片组内相邻所述芯片的间距不相等。
  96. 根据权利要求95所述的电路板，其特征在于，至少部分相邻所述芯片组的间距大于或等于容纳一个芯片所需的间距。
  97. 根据权利要求95所述的电路板，其特征在于，所述芯片组由至少一个取电单元组成，所述取电单元包括至少一个芯片。
  98. 根据权利要求97所述的电路板，其特征在于，所述取电单元包括多个芯片，所述取电单元中的芯片并联连接。
  99. 根据权利要求98所述的电路板，其特征在于，各所述芯片组的芯片并联方向相同，沿垂直所述芯片并联方向的方向，至少部分相邻所述芯片组的间距，与任一所述芯片组内相邻所述取电单元的间距不相等。
  100. 根据权利要求97所述的电路板，其特征在于，所述芯片组包括多个取电单元，多个所述取电单元串联连接。
  101. 根据权利要求100所述的电路板，其特征在于，各所述芯片组的芯片串联方向相同，沿所述芯片串联方向，至少部分相邻所述芯片组的间距，与任一所述芯片组内相邻所述取电单元的间距不相等。
  102. 根据权利要求97所述的电路板，其特征在于，所述取电单元中的芯片呈行 或呈列排列。
  103. 根据权利要求95所述的电路板，其特征在于，
    沿散热方向，所述多个芯片组划分至少一个芯片组集合。
  104. 根据权利要求103所述的电路板，其特征在于，
    沿散热方向，多个所述芯片组集合的芯片数量减少，和/或相邻芯片之间的距离增加。
  105. 根据权利要求103所述的电路板，其特征在于，所述芯片组集合内的芯片串联电流方向相同。
  106. 根据权利要求103所述的电路板，其特征在于，
    所述多个芯片组划分为第一芯片组集合和第二芯片组集合。
  107. 根据权利要求106所述的电路板，其特征在于，所述第一芯片组集合和第二芯片组集合中的芯片数量相等。
  108. 根据权利要求106所述的电路板，其特征在于，所述第一芯片组集合小于第二芯片组集合中的芯片数量。
  109. 根据权利要求106所述的电路板，其特征在于，所述第一芯片组集合大于第二芯片组集合中的芯片数量。
  110. 根据权利要求106所述的电路板，其特征在于，所述第一芯片组集合的平均芯片间距，小于第二芯片组集合的平均芯片间距。
  111. 根据权利要求106所述的电路板，其特征在于，
    所述第一芯片组集合中，包括1个芯片组；在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述第一芯片组集合中芯片组内相邻芯片间的芯片间距相等。
  112. 根据权利要求106所述的电路板，其特征在于，
    所述第一芯片组集合中，包括多个芯片组；在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述第一芯片组集合中各相邻芯片组之间的组间距大于各芯片组内相邻芯片间的芯片间距。
  113. 根据权利要求106所述的电路板，其特征在于，
    所述第二芯片组集合中，包括1个芯片组；在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述第二芯片组集合中芯片组内相邻芯片间的芯片间距相等。
  114. 根据权利要求106所述的电路板，其特征在于，
    所述第二芯片组集合中，包括多个芯片组；在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述第二芯片组集合中各相邻芯片组之间的组间距大于各芯片组内相邻芯片间的芯片间距。
  115. 根据权利要求106所述的电路板，其特征在于，
    所述第一芯片组集合和第二芯片组集合的芯片列数相同，且所述第一芯片组集合的芯片数量大于第二芯片组集合的芯片数量。
  116. 根据权利要求106所述的电路板，其特征在于，
    所述第一芯片组集合和第二芯片组集合的芯片列数相同，且所述第一芯片组集合的芯片数量小于第二芯片组集合的芯片数量。
  117. 根据权利要求106所述的电路板，其特征在于，
    所述第一芯片组集合和第二芯片组集合的芯片列数相同，且所述第一芯片组集合的芯片数量等于第二芯片组集合的芯片数量。
  118. 根据权利要求106所述的电路板，其特征在于，垂直所述芯片的并联方向上，
    所述第一芯片组集合中的多对相邻芯片组之间形成多个第一间隙；
    所述第二芯片组集合中的多对相邻芯片组之间形成多个第二间隙。
  119. 根据权利要求118所述的电路板，其特征在于，所述多个第一间隙和所述多个第二间隙一一对应，且至少部分相互对应的第一间隙和第二间隙共线。
  120. 根据权利要求118所述的电路板，其特征在于，对于至少一个所述第一间隙，所述第二芯片组集合中不存在共线的第二间隙。
  121. 根据权利要求118所述的电路板，其特征在于，所述多个第一间隙的数量小于所述多个第二间隙的数量。
  122. 根据权利要求106所述的电路板，其特征在于，在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述第一芯片组集合中至少一列芯片的数量大于所述第二芯片组集合中至少一列芯片的数量。
  123. 根据权利要求106所述的电路板，其特征在于，在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，所述第一芯片组集合中至少一列芯片的首芯片至尾芯片的距离小于所述第二芯片组集合中至少一列芯片的首芯片至尾芯片的距离。
  124. 根据权利要求106所述的电路板，其特征在于，
    所述第一芯片组集合中芯片组的数量小于所述第二芯片组集合中芯片组的数量。
  125. 根据权利要求106所述的电路板，其特征在于，在芯片阵列的芯片串联方向 或垂直于所述芯片阵列的芯片并联方向上，所述第二芯片组集合包括两个端部芯片组和一个中部芯片组，其中，各所述端部芯片组的芯片数量大于所述中部芯片组的芯片数量。
  126. 根据权利要求125所述的电路板，其特征在于，所述两个端部芯片组包括第一端部芯片组和第二端部芯片组，所述第一端部芯片组的芯片数量小于所述第二端部芯片组的芯片数量，其中，在所述电路板的垂直放置状态下，所述第一端部芯片组靠接所述电路板的顶部，所述第二端部芯片组靠近所述电路板的底部。
  127. 根据权利要求125所述的电路板，其特征在于，各所述端部芯片组中芯片间的平均间距小于所述中部芯片组中芯片间的平均间距。
  128. 根据权利要求106所述的电路板，其特征在于，沿散热方向，所述第一芯片组集合中平均芯片间距小于所述第二芯片组集合中平均芯片间距。
  129. 根据权利要求95所述的电路板，其特征在于，在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，至少部分相邻芯片组之间的电连接线长度大于芯片组内相邻芯片之间的电连接线长度。
  130. 根据权利要求129所述的电路板，其特征在于，所述电连接线包括电源线和/或信号线。
  131. 根据权利要求95所述的电路板，其特征在于，在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，至少部分相邻芯片组之间设置有金属件。
  132. 根据权利要求131所述的电路板，其特征在于，在芯片阵列的芯片串联方向或垂直于所述芯片阵列的芯片并联方向上，至少部分相邻芯片组之间的金属件长度大于芯片组内相邻芯片之间的金属件长度。
  133. 根据权利要求95所述的电路板，其特征在于，各所述芯片组包括多行芯片，且至少存在两个芯片组的芯片行数不同。
  134. 根据权利要求95所述的电路板，其特征在于，各所述芯片组包括多列芯片，且各所述芯片组的芯片列数相同。
  135. 根据权利要求95所述的电路板，其特征在于，多个所述芯片组之间串联供电连接，且各所述芯片组的各行或各列芯片之间串联供电连接。
  136. 根据权利要求135所述的电路板，其特征在于，各所述芯片组的各行或各列芯片内的芯片之间并联供电连接。
  137. 根据权利要求95所述的电路板，其特征在于，芯片阵列的列方向垂直于所述芯片阵列的芯片并联方向。
  138. 根据权利要求95所述的电路板，其特征在于，芯片阵列的行方向平行于所述芯片阵列的芯片并联方向。
  139. 一种工作组件，其特征在于，包括：
    电路板，如权利要求1至138任一项所述；
    散热器，所述散热器包括散热主体和散热鳍片，所述散热主体包括相对的第一面和第二面，所述第一面与所述散热鳍片连接。
  140. 根据权利要求139所述的工作组件，其特征在于，所述第二面设置有多个凸台，各所述凸台与各行芯片或各列芯片对应设置。
  141. 根据权利要求139所述的工作组件，其特征在于，所述第二面设置有多个凸台，至少部分凸台设置于至少部分相邻芯片组之间或至少部分相邻取电单元之间或至少部分空缺位的对应位置。
  142. 根据权利要求139所述的工作组件，其特征在于，所述工作组件适于工作在散热风道中，所述散热风道包括入风口和出风口，散热方向为从所述入风口到所述出风口。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115915717A (zh) * 2022-10-20 2023-04-04 北京嘉楠捷思信息技术有限公司 工作组件和电子设备
WO2024083231A1 (zh) * 2022-10-20 2024-04-25 北京嘉楠捷思信息技术有限公司 电子设备
CN118471921A (zh) * 2024-07-09 2024-08-09 合肥阿基米德电子科技有限公司 一种多并联芯片散热结构及多并联芯片散热方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180040779A1 (en) * 2014-12-30 2018-02-08 Semicon Light Co., Ltd. Semiconductor light emitting device and method for manufacturing same
CN108646890A (zh) * 2018-05-31 2018-10-12 北京比特大陆科技有限公司 一种散热装置、计算设备及挖矿机
CN109643705A (zh) * 2018-10-31 2019-04-16 北京比特大陆科技有限公司 电路板及芯片布局方法、计算设备
US20190229038A1 (en) * 2015-09-30 2019-07-25 Microfabrica Inc. Micro Heat Transfer Arrays, Micro Cold Plates, and Thermal Management Systems for Cooling Semiconductor Devices, and Methods for Using and Making Such Arrays, Plates, and Systems
CN111867338A (zh) * 2020-08-07 2020-10-30 深圳比特微电子科技有限公司 电子设备的均温散热装置
CN216488024U (zh) * 2021-04-08 2022-05-10 北京比特大陆科技有限公司 电路板组件和服务器
CN115768050A (zh) * 2022-10-20 2023-03-07 北京嘉楠捷思信息技术有限公司 电路板和工作组件

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374906B1 (en) * 2000-04-11 2002-04-23 Hewlett-Packard Company Heat sink having a captive handle
JP3884640B2 (ja) * 2001-11-02 2007-02-21 古河電気工業株式会社 ヒートシンク及び発熱体の冷却構造
CN100379330C (zh) * 2004-10-18 2008-04-02 台达电子工业股份有限公司 散热片固定装置
TWI326578B (en) * 2005-10-20 2010-06-21 Asustek Comp Inc Pcb with heat sink by through holes
CN101146418B (zh) * 2006-09-11 2010-05-12 台达电子工业股份有限公司 散热器固定结构及其组装方法
JP4578457B2 (ja) * 2006-11-02 2010-11-10 三菱電機株式会社 パワーモジュール装置
US7695161B2 (en) * 2007-11-08 2010-04-13 Fu Zhun Precision Industry (Shen Zhen) Co., Ltd. Heat dissipation device for light emitting diode module
JP5434914B2 (ja) * 2008-06-12 2014-03-05 株式会社安川電機 パワーモジュールおよびその制御方法
US9532485B2 (en) * 2014-02-21 2016-12-27 Lenovo (Beijing) Co., Ltd. Heat dissipating device and electronic apparatus
US11009301B2 (en) * 2014-06-27 2021-05-18 Delta Electronics, Inc. Heat dissipating fin assembly
CN109168288B (zh) * 2014-09-26 2020-07-14 华为技术有限公司 散热器及电子产品
JP2016178208A (ja) * 2015-03-20 2016-10-06 日本電気株式会社 ヒートシンク、放熱構造、冷却構造及び装置
CN104932175B (zh) * 2015-07-08 2018-01-02 北京旷视科技有限公司 摄像机
CN206226914U (zh) * 2016-11-18 2017-06-06 浙江亿邦通信科技股份有限公司 一种带有散热装置的设备
CN114071966A (zh) * 2017-05-18 2022-02-18 北京嘉楠捷思信息技术有限公司 一种电路板、散热器、工作组件和电子设备
CN108323114B (zh) * 2018-02-14 2024-06-25 北京比特大陆科技有限公司 具有对称散热结构的电路板及计算设备
CN209402836U (zh) * 2018-10-31 2019-09-17 北京比特大陆科技有限公司 电路板及计算设备
CN209608932U (zh) * 2018-11-20 2019-11-08 北京大豪科技股份有限公司 电路板散热器和电子装置
CN210008133U (zh) * 2019-03-27 2020-01-31 广州慧睿思通信息科技有限公司 散热装置及通信设备
KR102285259B1 (ko) * 2019-06-28 2021-08-03 주식회사 케이엠더블유 안테나 장치
CN113133261B (zh) * 2019-12-30 2022-07-22 华为数字能源技术有限公司 一种散热装置、电路板组件及电子设备
CN212906116U (zh) * 2020-08-10 2021-04-06 北京硅基远航科技有限公司 服务器
CN214639883U (zh) * 2020-12-29 2021-11-09 大连长丰实业总公司 一种螺旋弹簧圈剪切装置
US20220330414A1 (en) * 2021-04-08 2022-10-13 International Business Machines Corporation Heat sinks with beyond-board fins
CN215073588U (zh) * 2021-04-29 2021-12-07 西安易朴通讯技术有限公司 散热结构及电子产品
CN113099707B (zh) * 2021-05-21 2023-05-30 苏州格曼斯温控科技有限公司 散热装置及设备
CN216491209U (zh) * 2021-11-10 2022-05-10 广州视琨电子科技有限公司 电路板组件及电子设备
CN114071974A (zh) * 2021-11-24 2022-02-18 珠海格力节能环保制冷技术研究中心有限公司 散热器清洁机构、散热器、电器设备及控制方法
CN114388237A (zh) * 2022-01-17 2022-04-22 华为数字能源技术有限公司 电子器件、电源模块及电子设备
CN217240571U (zh) * 2022-02-28 2022-08-19 北京合康新能变频技术有限公司 变频器功率单元
CN217426061U (zh) * 2022-04-02 2022-09-13 北京嘉楠捷思信息技术有限公司 散热装置和计算设备
CN115088981A (zh) * 2022-07-11 2022-09-23 广东甜秘密寝具有限公司 弹簧、弹簧床垫及弹簧测试方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180040779A1 (en) * 2014-12-30 2018-02-08 Semicon Light Co., Ltd. Semiconductor light emitting device and method for manufacturing same
US20190229038A1 (en) * 2015-09-30 2019-07-25 Microfabrica Inc. Micro Heat Transfer Arrays, Micro Cold Plates, and Thermal Management Systems for Cooling Semiconductor Devices, and Methods for Using and Making Such Arrays, Plates, and Systems
CN108646890A (zh) * 2018-05-31 2018-10-12 北京比特大陆科技有限公司 一种散热装置、计算设备及挖矿机
CN109643705A (zh) * 2018-10-31 2019-04-16 北京比特大陆科技有限公司 电路板及芯片布局方法、计算设备
CN111867338A (zh) * 2020-08-07 2020-10-30 深圳比特微电子科技有限公司 电子设备的均温散热装置
CN216488024U (zh) * 2021-04-08 2022-05-10 北京比特大陆科技有限公司 电路板组件和服务器
CN115768050A (zh) * 2022-10-20 2023-03-07 北京嘉楠捷思信息技术有限公司 电路板和工作组件

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