WO2024077728A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2024077728A1
WO2024077728A1 PCT/CN2022/134121 CN2022134121W WO2024077728A1 WO 2024077728 A1 WO2024077728 A1 WO 2024077728A1 CN 2022134121 W CN2022134121 W CN 2022134121W WO 2024077728 A1 WO2024077728 A1 WO 2024077728A1
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mask
mask layer
layer
substrate
semiconductor structure
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PCT/CN2022/134121
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English (en)
French (fr)
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曹新满
吴耆贤
黄炜
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长鑫存储技术有限公司
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Publication of WO2024077728A1 publication Critical patent/WO2024077728A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a method for manufacturing a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • the characteristic size of semiconductor memory continues to shrink, the structural layout is more compact, and the aspect ratio of the contact holes formed in the process of semiconductor memory is getting larger and larger.
  • the present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:
  • the substrate comprising a plurality of active regions arranged at intervals and an isolation structure disposed between adjacent active regions;
  • each of the mask structures comprises a first mask layer, a second mask layer and a third mask layer sequentially stacked on the substrate, wherein in a cross section perpendicular to the top surface of the substrate, the second mask layer is recessed inwardly relative to the first mask layer and the third mask layer, and a groove is formed between the first mask layer and the third mask layer;
  • Etching the substrate based on the multiple mask structures removing the portion of the active area exposed by the multiple mask structures, forming a contact hole in the middle region of each active area, and forming a protection layer in the groove during etching the substrate, the protection layer covering the portion of the first mask layer exposed by the second mask layer;
  • a first material is filled in each of the contact holes.
  • a second aspect of the present disclosure provides a semiconductor structure, which is manufactured according to the method for manufacturing the semiconductor structure provided by the first aspect of the present disclosure.
  • FIG. 1 is a flow chart showing a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a schematic diagram of a substrate according to an exemplary embodiment.
  • FIG. 3 is a top view of a substrate according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram showing a method of forming a stacked structure according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram showing etching of a third mask material layer and a second mask material layer according to an exemplary embodiment.
  • FIG. 6 is a schematic diagram showing a process of forming an initial mask structure according to an exemplary embodiment.
  • FIG. 7 is a top view showing a process of forming an initial mask structure according to an exemplary embodiment.
  • FIG. 8 is a schematic diagram showing a method of forming a mask structure according to an exemplary embodiment.
  • FIG. 9 is a top view showing a process of forming a mask structure according to an exemplary embodiment.
  • FIG. 10 is a schematic diagram showing etching an isolation layer according to a mask structure according to an exemplary embodiment.
  • FIG. 11 is a schematic diagram showing a mask structure according to an exemplary embodiment.
  • FIG. 12 is a schematic diagram showing the growth of a polymer toward a first mask layer according to an exemplary embodiment.
  • FIG. 13 is a schematic diagram showing the growth of a polymer toward a first mask layer according to an exemplary embodiment.
  • FIG. 14 is a schematic diagram showing a polymer forming a protection layer in a groove according to an exemplary embodiment.
  • FIG. 15 is a schematic diagram showing the formation of a contact hole and a protection layer according to an exemplary embodiment.
  • FIG. 16 is a top view showing a contact hole according to an exemplary embodiment.
  • FIG. 17 is a schematic diagram showing removal of the third mask layer and the protection layer according to an exemplary embodiment.
  • FIG. 18 is a schematic structural diagram showing a method of forming a first material layer according to an exemplary embodiment.
  • FIG. 19 is a top view showing a process of forming a first material layer according to an exemplary embodiment.
  • FIG. 20 is a schematic diagram showing a method of forming a contact structure according to an exemplary embodiment.
  • FIG. 21 is a top view showing a process of forming a contact structure according to an exemplary embodiment.
  • the width of the contact holes is usually defined as small. In this way, the depth-to-width ratio of the contact holes formed is large.
  • the conductive materials cannot fill the contact holes due to the depth-to-width ratio of the contact holes.
  • the width of the contact holes is increased, the etching process is very likely to damage the structures or devices near the contact holes, causing the entire semiconductor memory to be scrapped.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, wherein a groove is formed on the periphery of the mask structure and is recessed from the periphery of the mask structure toward the center.
  • the etching product forms a protective layer in the groove.
  • the protective layer is used to protect the mask structure to prevent the mask structure from being damaged by etching, thereby ensuring that the size of the mask structure does not change during the etching process, and that the size of the contact hole formed according to the mask structure is consistent with the size of the contact hole to be formed defined by the mask structure, thereby preventing the size of the contact hole from increasing due to over-etching.
  • FIG. 1 shows a flow chart of the method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure
  • Figures 2 to 21 are schematic diagrams of various stages of the method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure is introduced below in conjunction with Figures 2 to 21.
  • the present embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto.
  • DRAM dynamic random access memory
  • the semiconductor structure in the present embodiment may also be other structures.
  • a method for manufacturing a semiconductor structure includes the following steps:
  • Step S110 providing a substrate, wherein the substrate includes a plurality of active regions arranged at intervals and an isolation structure disposed between adjacent active regions.
  • FIG. 2 is a schematic diagram of a substrate shown in the present exemplary embodiment
  • FIG. 3 is a top view of the substrate shown in the present exemplary embodiment
  • FIG. 2 is a cross-sectional view of the A-A section of FIG. 3 .
  • the substrate 100 includes a plurality of independently arranged active regions 110, and the active regions 110 extend along a first direction D1.
  • Each active region 110 includes a source region 111, an intermediate region 113, and a drain region 112 arranged in sequence along the first direction D1.
  • the source region 111 of any active region 110 and the drain region 112 of the adjacent active region 110 are alternately arranged along the first direction D1.
  • the material of the active region 110 includes a semiconductor material, and the semiconductor material may include one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.
  • Adjacent active regions 110 are separated by an isolation structure 120, and the material of the isolation structure 120 may be a low-k dielectric material, for example, the material of the isolation structure 120 may be silicon dioxide.
  • Step S120 forming a plurality of mask structures, wherein the plurality of mask structures are arranged on the substrate to expose the middle region of each active region, wherein each mask structure comprises a first mask layer, a second mask layer and a third mask layer sequentially stacked on the substrate, wherein in a cross section perpendicular to the top surface of the substrate, the second mask layer is recessed inwardly relative to the first mask layer and the third mask layer, forming a groove between the first mask layer and the third mask layer.
  • FIG8 is a schematic diagram showing a plurality of mask structures shown in this exemplary embodiment
  • FIG9 is a top view showing a plurality of mask structures shown in this exemplary embodiment
  • FIG8 is a cross-sectional view of the A-A section of FIG9 .
  • each mask structure 200 covers a portion of the top surface of two adjacent active areas 110 and a portion of the top surface of the isolation structure 120 located between the two adjacent active areas 110, and the multiple mask structures 200 define the pattern of the contact holes 130 to be formed on the substrate 100 (refer to Figures 15 and 16).
  • multiple mask structures 200 cover the source region 111 and the drain region 112 of each active region 110 and the top surface of a portion of the isolation structure 120, exposing the middle region 113 of each active region 110 and the top surface of another portion of the isolation structure 120.
  • the middle region 113 and the top surface of the isolation structure 120 exposed by the multiple mask structures 200 are the areas defined by the multiple mask structures 200 for forming contact holes 130 (refer to Figures 15 and 16).
  • each mask structure 200 includes a first mask layer 210, a second mask layer 220 and a third mask layer 230 stacked in sequence on the substrate 100, the width of the second mask layer 220 is smaller than the width of the first mask layer 210, and the width of the second mask layer 220 is smaller than the width of the third mask layer 230, the second mask layer 220 of each mask structure 200 is recessed inward relative to the first mask layer 210 and the third mask layer 230, forming a groove 240 recessed from the circumference of the mask structure 200 toward the center, and the projection of each mask structure 200 on the cross section perpendicular to the top surface of the substrate 100 is in the shape of an "I".
  • the second mask layer 220 of each mask structure 200 exposes a portion of the top surface of the first mask layer 210 and a portion of the bottom surface of the third mask layer 230.
  • the exposed top surface of the first mask layer 210, the exposed bottom surface of the third mask layer 230, and the sidewalls of the second mask layer 220 form a groove 240 between the first mask layer 210 and the third mask layer 230 of each mask structure 200.
  • Step S130 etching the substrate based on multiple mask structures, removing portions of the active areas exposed by the multiple mask structures, forming contact holes in the middle of each active area, and at the same time, forming a protective layer in the groove during etching the substrate, the protective layer covering the first mask layer exposed by the second mask layer.
  • FIG15 is a schematic diagram showing the formation of a contact hole according to the present exemplary embodiment
  • FIG16 is a top view showing the formation of a contact hole according to the present exemplary embodiment
  • FIG15 is a cross-sectional view of the A-A section of FIG16 .
  • the substrate 100 exposed by the multiple mask structures 200 is etched through an etching process to remove at least a portion of the structure of the middle region 113 of each active area 110, and a contact hole 130 is formed in the middle region 113 of each active area 110.
  • the reaction products formed during the etching process of the present embodiment are deposited in the groove 240 to form a protective layer 250, and the protective layer 250 covers the first mask layer 210 exposed by the second mask layer 220.
  • the protective layer 250 is used to protect the first mask layer 210 to prevent the first mask layer 210 from being damaged by etching, and ensure that after the contact hole 130 is formed, the size of the first mask layer 210 remains unchanged relative to the size of the first mask layer 210 before etching the active area 110, so as to avoid the first mask layer 210 being etched away during the etching process, and the size of the active area 110 exposed by the mask structure 200 is increased, resulting in the problem that the size of the formed contact hole 130 is larger than the size of the contact hole 130 to be formed defined by multiple mask structures 200; and to avoid the source area 111 and the drain area 112 of the active area 110 covered by the first mask layer 210 from being etched away.
  • the size of the contact hole 130 etched in the substrate 100 in this embodiment is completely consistent with the size of the contact hole 130 to be formed defined by the mask structure 200, and the contact hole 130 formed has a high-precision shape and size.
  • the etching process selected in this embodiment can be dry etching.
  • the size of the contact hole 130 formed in the substrate 100 according to the multiple mask structures 200 and the size of the contact hole 130 to be formed defined by the multiple mask structures 200 arranged on the substrate 100 are completely consistent. Therefore, under the premise of ensuring that the mask structure 200 covers the source region 111 and the drain region 112 of each active region 110, when forming the mask structure 200, the size of the contact hole 130 to be formed defined by the mask structure 200 can be set to the maximum to increase the width of the contact hole 130 formed and reduce the aspect ratio of the contact hole 130 formed in the middle area 113.
  • Step S140 Fill each contact hole with a first material.
  • Figure 20 shows a schematic diagram of forming a contact structure shown in this exemplary embodiment
  • Figure 21 shows a top view of forming a contact structure in each contact hole shown in this exemplary embodiment
  • Figure 20 is a cross-sectional view of the A-A section of Figure 21.
  • any deposition process among chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering can be selected to deposit the first material to fill the contact hole 130, and the first material fills the contact hole 130 to form a contact structure 300 in the contact hole 130.
  • the first material can be single crystal silicon or polycrystalline silicon, and the first material can be doped with conductive ions.
  • the contact hole 130 formed in the present embodiment has a large width and a small aspect ratio.
  • the first material is less adversely affected by the aspect ratio of the contact hole 130.
  • the first material can completely fill the contact hole 130, ensuring that there are no unfilled gaps in the formed contact structure 300.
  • the formed contact structure 300 has better conductivity and a higher yield of the semiconductor structure.
  • a protective layer is formed to protect the first mask layer so that the size of the substrate covered by the first mask layer remains unchanged, ensuring that the size of the contact hole formed in the substrate is completely consistent with the size of the contact hole to be formed defined by the mask structure on the substrate, thereby reducing the aspect ratio of the contact hole formed, reducing the difficulty of filling the contact hole, and ensuring that the first material filled in the contact hole has no gaps.
  • each mask structure 200 covers the source region 111 or the drain region 112 of one of the two adjacent active regions 110, and the drain region 112 or the source region 111 of the other active region 110.
  • the width of each active area 110 in the second direction D2 is the first width L1
  • the width of the isolation structure 120 located between two adjacent active areas 110 in the second direction D2 is the second width L2
  • the width of the projection formed by each mask structure 200 on the substrate 100 in the second direction D2 is the third width L3
  • the first direction D1 and the second direction D1 intersect.
  • this embodiment is an explanation of the above embodiment.
  • a plurality of mask structures are formed in step S120, including the following steps:
  • Step S121 forming a stacked structure, the stacked structure covers the top surface of the substrate, and the stacked structure includes a first mask material layer, a second mask material layer, and a third mask material layer sequentially stacked on the substrate.
  • any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering processes may be selected to sequentially deposit a first mask material layer 211 , a second mask material layer 221 and a third mask material layer 231 to form a stacked structure 260 .
  • the material of the second mask material layer 221 has a high etching selectivity relative to the material of the first mask material layer 211 and the material of the third mask material layer 231.
  • the material of the first mask material layer 211 may include the first material; the material of the second mask material layer 221 may include an oxide, for example, the material of the second mask material layer 221 includes silicon oxide; the material of the third mask material layer 231 may include a nitride, for example, the material of the third mask material layer 231 includes silicon nitride or silicon oxynitride.
  • the first mask material layer 211, the second mask material layer 221, and the third mask material layer 231 may be made of other materials that satisfy the etching selectivity.
  • Step S122 etching and removing part of the third mask material layer, part of the second mask material layer and part of the first mask material layer in sequence, the retained first mask material layer forms a first mask layer, the retained second mask material layer forms a second initial mask layer, the retained third mask material layer forms a third mask layer, the projections of the first mask layer, the second initial mask layer and the third mask layer on the substrate overlap, forming multiple initial mask structures.
  • a photoresist pattern 280 is formed on the top surface of the third mask material layer 231 , and the photoresist pattern 280 defines the pattern of the contact hole 130 (refer to FIGS. 15 and 16 ) to be formed.
  • the third mask material layer 231 and the second mask material layer 221 are then etched layer by layer according to the photoresist pattern 280.
  • the third mask material layer 231 may be etched by a dry process, for example, a mixed gas of carbonyl sulfide (COS) and oxygen (O 2 ) may be used as an etching gas to etch the third mask material layer 231, and the third mask material layer 231 exposed by the photoresist pattern 280 is removed, and the third mask material layer 231 that is retained forms the third mask layer 230.
  • COS carbonyl sulfide
  • O 2 oxygen
  • the second mask material layer 221 may be etched by a dry process.
  • a mixture of perfluorobutadiene (C 4 F 6 ), octafluorocyclobutane (C 4 F 8 ) and O 2 may be used as an etching gas to etch away the second mask material layer 221 exposed by the third mask layer 230 .
  • the retained second mask material layer 221 forms a second initial mask layer 222 .
  • the first mask material layer 211 is then etched according to the second initial mask layer 222 and the third mask layer 230.
  • the first mask material layer 211 may be etched by a dry process, for example, a mixed gas of hydrogen bromide (HBr), chlorine ( Cl2 ) and O2 may be used as an etching gas to etch away the first mask material layer 211 exposed by the second initial mask layer 222 and the third mask layer 230, and the retained first mask material layer 211 forms the first mask layer 210.
  • a mixed gas of hydrogen bromide (HBr), chlorine ( Cl2 ) and O2 may be used as an etching gas to etch away the first mask material layer 211 exposed by the second initial mask layer 222 and the third mask layer 230, and the retained first mask material layer 211 forms the first mask layer 210.
  • each initial mask structure 270 includes a first mask layer 210, a second initial mask layer 222 and a third mask layer 230 stacked in sequence on the substrate 100, and in a cross section perpendicular to the top surface of the substrate 100, the initial mask structure 270 has the same width from top to bottom.
  • FIG6 is a schematic diagram showing the formation of multiple initial mask structures shown in this exemplary embodiment
  • FIG7 is a top view showing the formation of multiple initial mask structures shown in this exemplary embodiment
  • FIG6 is a cross-sectional view of the A-A section of FIG7.
  • the multiple initial mask structures 270 formed in this embodiment are independently arranged, and the outer peripheral surface of each initial mask structure 270 is exposed in the process space, so that the peripheral surface of the initial mask structure 270 can be processed in subsequent steps, and a groove 240 is formed between the first mask layer 210 and the third mask layer 230 (which will be described in detail later).
  • Step S123 Etch each initial mask structure, remove part of the second initial mask layer from the outer peripheral surface of the second initial mask layer toward the center direction, and form a groove between the first mask layer and the third mask layer, the groove exposes the peripheral area of the top surface of the first mask layer, and the groove exposes the peripheral area of the bottom surface of the third mask layer, the retained initial mask structure forms a mask structure, and the retained second initial mask layer forms a second mask layer.
  • a portion of the second initial mask layer 222 is etched away from the outer peripheral surface of the second initial mask layer 222 toward the center direction, and as shown in FIG11 , the peripheral area 210a of the top surface of the first mask layer 210 and the peripheral area 230a of the bottom surface of the third mask layer 230 are exposed, and the retained second initial mask layer 222 forms the second mask layer 220, and the peripheral surface of the second mask layer 220, the peripheral area 210a of the top surface of the first mask layer 210, and the peripheral area 230a of the bottom surface of the third mask layer 230 form a groove 240 between the first mask layer 210 and the third mask layer 230.
  • each initial mask structure 270 forms a mask structure 200
  • each mask structure 200 includes a first mask layer 210, a second mask layer 220 and a third mask layer 230 stacked in sequence on the substrate 100
  • the width of the second mask layer 220 is smaller than the width of the first mask layer 210
  • the projection formed by the second mask layer 220 on the substrate 100 falls within the projection formed by the first mask layer 210 on the substrate 100.
  • an etching process having a high etching selectivity ratio for the second initial mask layer 222 relative to etching the first mask layer 210 and the third mask layer 230 is selected, and the etching rate of the first mask layer 210 is 0 in the etching process, so as to avoid the first mask layer 210 being removed, causing etching damage to the source region 111 and the drain region 112 of the active region 110, and to avoid over-etching causing the size of the contact hole 130 (refer to Figures 15 and 16) to increase.
  • etching each initial mask structure 270 can be carried out in the following manner: placing the semiconductor structure in an inductively coupled plasma spectrometer (ICP), which is the main light source for atomic emission spectroscopy, adjusting the pressure of the inductively coupled plasma spectrometer to 60mtorr ⁇ 100mtorr, setting the voltage to 600W ⁇ 1000W, setting the RF power to 200W ⁇ 400W, and setting the temperature to 30°C ⁇ 50°C. Then, HBr gas is introduced into the inductively coupled plasma spectrometer, and the flow rate of HBr is 200 sccm to 400 sccm.
  • ICP inductively coupled plasma spectrometer
  • O2 or an inert gas such as helium (He) is introduced into the inductively coupled plasma spectrometer.
  • the HBr gas and O2 are ionized into bromine plasma and bromide ions respectively by the inductively coupled plasma spectrometer, and a portion of the second initial mask layer 222 is removed by plasma etching from the outer peripheral surface of the second initial mask layer 222 toward the center.
  • the manufacturing method of the semiconductor structure of the present embodiment etches the stacked structure into a plurality of independently arranged initial mask structures to expose the outer peripheral surface of each initial mask structure, and then etches the initial mask structure into a mask structure with a groove.
  • the area of the substrate covered by the first mask layer of the mask structure remains unchanged, and the size of the area for forming the contact hole defined by the plurality of mask structures in the middle area of each active area remains unchanged, which can improve the accuracy of the formed contact holes so that the size of the contact holes formed in the middle area is more in line with expectations.
  • this embodiment is an explanation of the above embodiment.
  • an isolation layer 140 is deposited on the top surface of the substrate 100.
  • the isolation layer 140 covers the top surface of the substrate 100 to prevent the active area 110 from being exposed to oxidation pollution in the process environment.
  • the material of the isolation layer 140 may include silicon nitride.
  • Step S130 of this embodiment etches the substrate based on multiple mask structures.
  • a protective layer is formed in the groove, including the following steps:
  • the isolation layer 140 is etched based on the multiple mask structures 200 to remove the isolation layer 140 exposed by the multiple mask structures 200.
  • wet etching can be used to remove the isolation layer 140 exposed by the multiple mask structures 200.
  • a hydrofluoric acid solution with a concentration of 1:200 can be used to dissolve and remove the isolation layer 140 exposed by the multiple mask structures 200, exposing the middle region 113 of each active region 110 and the top surface of the isolation structure 120 near the middle region 113 of the active region 110.
  • the semiconductor structure is then placed in a reaction chamber, and an etching gas is introduced into the reaction chamber.
  • the etching gas dissociates in the reaction chamber to generate multiple plasmas, and the multiple plasmas impact the middle region 113, remove the portion of the active region 110 exposed by the mask structure 200 and the portion of the isolation structure 120 near the middle region 113, and form a contact hole 130 in the middle region 113.
  • part of the multiple plasmas react to generate polymers, and the polymers are attached to the peripheral region 230a of the bottom surface of the third mask layer 230, and grow from the peripheral region 230a of the bottom surface of the third mask layer 230 toward the first mask layer 210.
  • the polymer fills the groove 240 to form a protective layer 250, and the protective layer 250 covers the peripheral region 210a of the top surface of the first mask layer 210.
  • the reaction chamber can be an inductively coupled plasma spectrometer.
  • the multiple plasmas generated by the dissociation of the etching gas in the reaction chamber include at least carbon plasma and oxygen plasma, so that the plasma generated by the ionization of the etching gas reacts in the reaction chamber to generate polymers.
  • a carbon source gas and an oxygen source gas are introduced into the reaction chamber, and the carbon source gas may include at least one of an organic gas and an inorganic gas.
  • carbon dioxide (CO 2 ) and O 2 are introduced into the reaction chamber, and the carbon-containing gas and the oxygen-containing gas are ionized into carbon plasma and oxygen plasma in the reaction chamber, and the carbon plasma and the oxygen plasma etch and remove the portion of the active area 110 exposed by the mask structure 200.
  • the carbon plasma and the oxygen plasma undergo a polymerization reaction to generate a polymer, and the polymer grows in the peripheral area 230a of the bottom surface of the third mask layer 230 and fills the groove 240 to form a protective layer 250.
  • the multiple plasmas generated by the dissociation of the etching gas in the reaction chamber also include fluorine plasma and chlorine plasma. While the carbon source gas and the oxygen source gas are introduced into the reaction chamber, the fluorine source gas and the chlorine source gas are introduced into the reaction chamber.
  • At least one of carbon tetrafluoride (CF 4 ) or trifluoromethane (CHF 3 ) is introduced into the reaction chamber, and at the same time, O 2 and Cl 2 are introduced into the reaction chamber, and the C element content in the etching gas is greater than the Cl element content and the F element content.
  • the etching gas is ionized to generate carbon plasma, oxygen plasma, fluorine plasma, and chlorine plasma, and the multiple plasmas impact the exposed active area 110.
  • the carbon plasma, oxygen plasma, fluorine plasma, and chlorine plasma generate polymers, and the polymers cover the peripheral area 230 a of the bottom surface of the third mask layer 230 , and gradually grow from the peripheral area 230 a of the bottom surface of the third mask layer 230 toward the peripheral area 210 a of the top surface of the first mask layer 210 until the groove 240 is filled, and a protective layer 250 is formed in the groove 240. Since the peripheral area 230a of the bottom surface of the third mask layer 230 is less affected by the etching gas, the protection layer 250 can be formed on the peripheral area 230a first, so that the protection layer 250 covers the second mask layer 220, thereby protecting the first mask layer 220 from being etched.
  • the molecular formula of the polymer generated by the polymerization reaction of multiple plasmas is CxOyFzCl ⁇ , wherein x, y, z, ⁇ are the atomic numbers corresponding to each element, and 1 ⁇ x, y, z, ⁇ 6.
  • the etching parameters and etching conditions are controlled to control the impact speeds of various plasmas and the speeds at which polymers are generated by various plasma reactions, so that the speed at which the polymer is formed on the side wall of the third mask layer 230 is the same as the speed at which the polymer is removed by plasma impact, thereby ensuring that the polymer does not grow on the side wall of the third mask layer 230 and avoiding affecting the size of the contact hole 130 formed by etching.
  • the multiple plasmas undergo polymerization reactions in the reaction chamber to generate polymers, which are attached to the exposed surface of the third mask layer 230, that is, the polymers are not only attached to the peripheral area 230a of the bottom surface of the third mask layer 230, but may also be attached to the sidewalls and top surface of the third mask layer 230. If the polymers attached to the sidewalls of the third mask layer 230 are not removed in time, the width of the mask structure 200 will increase, resulting in a reduction in the size of the contact hole 130 subsequently formed by etching according to the mask structure 200.
  • the speed of forming the polymers on the sidewalls of the third mask layer 230 is the same as the speed of removing the polymers by plasma impact, so as to avoid the polymers from being attached to the sidewalls of the third mask layer 230 and to avoid affecting the size of the contact hole 130 formed.
  • a bias is applied to the plurality of plasmas from the peripheral surface of the second mask layer 220 toward the center direction, and under the action of the bias, the plurality of plasmas simultaneously reach the peripheral area 230a of the bottom surface of the third mask layer 230, and the plurality of plasmas undergo polymerization reaction in the peripheral area 230a of the bottom surface of the third mask layer 230 to generate polymers.
  • the polymer grows on the peripheral area 230a of the bottom surface of the third mask layer 230, and grows from the peripheral area 230a of the bottom surface of the third mask layer 230 toward the top surface of the first mask layer 210, avoiding the protection layer 250 from extending into the area between two adjacent mask structures 200, ensuring that the size of the mask structure 200 does not change during the etching process, ensuring that the size of the formed contact hole 130 (refer to Figures 15 and 16) is completely consistent with the size of the contact hole 130 to be formed defined by multiple mask structures 200 on the substrate 100, and the morphology and size of the contact hole 130 formed according to the mask structure 200 have high precision.
  • step S140 the first material is filled in the contact hole, including the following steps:
  • Step S141 removing the third mask layer and the protective layer.
  • an etching process having a high etching selectivity ratio to the second mask layer 220 and the first mask layer 210 is selected to etch the mask structure 200 and the protective layer 250 .
  • the third mask layer and the protective layer are removed, and the following implementation methods may be used:
  • the components of the etching gas introduced into the reaction chamber are adjusted, and only O 2 is introduced into the reaction chamber.
  • O 2 is ionized into oxygen plasma in the reaction chamber.
  • the oxygen plasma collides with the third mask layer 230 and the protective layer 250 to remove the third mask layer 230 and the protective layer 250 .
  • the third mask layer 230 and the protective layer 250 are removed, which increases the process window for subsequently depositing the first material into the contact hole 130, reduces the difficulty of filling the contact hole 130 with the first material, ensures that the first material can completely fill the contact hole 130, and avoids the presence of gaps in the first material filled in the contact hole 130.
  • Step S142 depositing a first material to form a first material layer, wherein the first material layer fills the contact hole and covers the first mask layer and the second mask layer.
  • FIG18 is a schematic diagram showing the formation of the first material layer according to the present exemplary embodiment
  • FIG19 is a top view showing the formation of the first material layer according to the present exemplary embodiment
  • FIG18 is a cross-sectional view of the A-A section of FIG19 .
  • the first material is deposited by any one of the deposition processes including chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering to form a first material layer 301, and the first material layer 301 fills each contact hole 130, covers the exposed top surface of the substrate 100, and covers the first mask layer 210 and the second mask layer 220.
  • the first mask layer 210 includes a first material. As shown in FIGS. 18 and 19 , the first material layer 301 is connected to the first mask layer 210 .
  • Step S143 etching back the first material layer and removing the second mask layer, so that the first material layer retained in each contact hole forms a contact structure.
  • a portion of the first material layer 301, a portion of the first mask layer 210, and the entire second mask layer 220 may be removed by etching, and the retained first material layer 301 is connected to the retained first mask layer 210.
  • the first material layer 301 in the contact hole 130 is retained to form a contact structure 300, and the retained first material layer 301 and the retained first mask layer 210 on the top surface of the substrate 100 may form other devices in subsequent processes.
  • the contact hole 130 formed in this exemplary embodiment is used as a bit line contact hole for illustration, as shown in FIG. 20 and FIG. 21 , the first material layer 301 in the contact hole 130 is retained to form a contact structure 300, and the first material layer 301 retained on the top surface of the substrate 100 and the first mask layer 210 retained form a plurality of independently arranged bit line contact layers 310, and the bit line contact layers 310 extend along the third direction D3.
  • the third direction D3 and the first direction D1 are obliquely intersected, and the third direction D3 is perpendicular to the second direction D2, and each bit line contact layer 310 is connected to a row of contact structures 300 arranged along the third direction D3, and in the subsequent process, a bit line (not shown in the figure) can be formed on the bit line contact layer 310.
  • the first material layer 301 located on the top surface of the substrate 100 can be etched away and the entire first mask layer 210 and the entire second mask layer 220 can be removed to expose the top surface of the substrate 100, leaving only the first material layer 301 located in the contact hole 130 to form the contact structure 300, and there is no gap in the contact structure 300.
  • the contact structure 300 formed in this embodiment has no filled gaps, and the contact structure 300 has low resistance and good electrical performance.
  • Other devices (such as bit lines) formed on the contact structure 300 are more solid and have good anti-tilting properties, and the semiconductor structure has a higher yield.
  • a semiconductor structure is provided in this embodiment, and the semiconductor structure provided in this exemplary embodiment is manufactured according to the manufacturing method of the semiconductor structure in the above-mentioned embodiment.
  • the aspect ratio of the contact hole 130 is small, and there is no gap in the contact structure 300 in the contact hole 130, so that the quality of the semiconductor structure is better and the yield is higher.
  • the semiconductor structure of this embodiment can be applied to dynamic random access memory (DRAM). However, it can also be applied to static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PRAM), etc.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • FRAM ferroelectric random access memory
  • MRAM magnetic random access memory
  • PRAM phase change random access memory
  • first, second, etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.
  • a groove is formed on the periphery of the mask structure, which is recessed from the periphery of the mask structure toward the center.
  • the etching product forms a protective layer in the groove.
  • the protective layer is used to prevent the mask structure from being damaged by etching, ensure that the size of the mask structure does not change during the etching process, thereby avoiding over-etching and causing the size of the contact hole to increase.

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Abstract

本公开提供一种半导体结构的制作方法及半导体结构，涉及半导体技术领域，半导体结构的制作方法包括：提供衬底，衬底包括多个有源区；形成多个掩膜结构，暴露出每个有源区的中间区域，每个掩膜结构包括第一掩膜层、第二掩膜层和第三掩膜层，第二掩膜层相对于第一掩膜层、第三掩膜层向内凹陷形成凹槽；基于多个掩膜结构刻蚀有源区，在有源区的中间区域形成接触孔，同时，在凹槽中形成保护层，保护层覆盖被第二掩膜层暴露出的第一掩膜层；于接触孔中填充第一材料。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202211242601.4、申请日为2022年10月11日、申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
随着半导体存储器技术的不断发展，半导体存储器的特征尺寸不断缩小，结构布局更加紧凑，半导体存储器的制程中形成的接触孔的深宽比越来越大，在接触孔中形成的接触结构的内部可能存在缝隙，缝隙造成接触结构的电阻增加，影响半导体结构的品质，降低半导体结构的电性能和良率。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供了一种半导体结构的制作方法，所述半导体结构的制作方法包括：
提供衬底，所述衬底包括间隔排列的多个有源区以及设置在相邻的所述有源区之间的隔离结构；
形成多个掩膜结构，多个所述掩膜结构排列在所述衬底上，暴露出每个所述有源区的中间区域，每个所述掩膜结构包括依次叠置在所述衬底上的第一掩膜层、第二掩膜层和第三掩膜层，在垂直于所述衬底的顶面的截面上，所述第二掩膜层相对于所述第一掩膜层、所述第三掩膜层向内凹陷，在所述第一掩膜层和所述第三掩膜层之间形成凹槽；
基于多个所述掩膜结构刻蚀所述衬底，去除被多个所述掩膜结构暴露出的部分所述有源区，在每个所述有源区的所述中间区域形成接触孔，同时，在刻蚀所述衬底的过程中，在所述凹槽中形成保护层，所述保护层覆盖被所述第二掩膜层暴露出的所述第一掩膜层；
于每个所述接触孔中填充第一材料。
本公开的第二方面提供了一种半导体结构，所述半导体结构根据本公开的第一方面提供的半导体结构的制作方法制作得到。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的衬底的示意图。
图3是根据一示例性实施例示出的衬底的俯视图。
图4是根据一示例性实施例示出的形成叠层结构的示意图。
图5是根据一示例性实施例示出的刻蚀第三掩膜材料层和第二掩膜材料层的示意 图。
图6是根据一示例性实施例示出的形成初始掩膜结构的示意图。
图7是根据一示例性实施例示出的形成初始掩膜结构的俯视图。
图8是根据一示例性实施例示出的形成掩膜结构的示意图。
图9是根据一示例性实施例示出的形成掩膜结构的俯视图。
图10是根据一示例性实施例示出的根据掩膜结构刻蚀隔离层的示意图。
图11是根据一示例性实施例示出的掩膜结构的示意图。
图12是根据一示例性实施例示出的聚合物向第一掩膜层方向生长的示意图。
图13是根据一示例性实施例示出的聚合物向第一掩膜层方向生长的示意图。
图14是根据一示例性实施例示出的聚合物在凹槽中形成保护层的示意图。
图15是根据一示例性实施例示出的形成接触孔和保护层的示意图。
图16是根据一示例性实施例示出的接触孔的俯视图。
图17是根据一示例性实施例示出的去除第三掩膜层和保护层的示意图。
图18是根据一示例性实施例示出的形成第一材料层的结构示意图。
图19是根据一示例性实施例示出的形成第一材料层的俯视图。
图20是根据一示例性实施例示出的形成接触结构的示意图。
图21是根据一示例性实施例示出的形成接触结构的俯视图。
附图标记：
100、衬底；110、有源区；111、源区；112、漏区；113、中间区域；120、隔离结构；130、接触孔；140、隔离层；200、掩膜结构；210、第一掩膜层；210a、第一掩膜层的顶面的周边区域；211、第一掩膜材料层；220、第二掩膜层；221、第二掩膜材料层；222、第二初始掩膜层；230、第三掩膜层；230a、第三掩膜层的底面的周边区域；231、第三掩膜材料层；240、凹槽；250、保护层；260、叠层结构；270、初始掩膜结构；280、光刻胶图案；300、接触结构；301、第一材料层；310、位线接触层；
D1、第一方向；D2、第二方向；D3、第三方向。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
随着半导体存储器的尺寸不断减小，半导体存储器中半导体器件的间距减小，在半导体存储器的制程中，涉及到刻蚀形成接触孔的步骤时，为了避免刻蚀损伤接触孔附近的器件，通常将接触孔的宽度定义的较小，如此，形成的接触孔的深宽比大，沉积导电材料填充接触孔形成接触插塞的制程中，受到接触孔的深宽比的影响，导电材料无法填满接触孔，沉积形成的接触插塞的内部总是存在未填充的空气隙，空气隙的存在增大接触插塞的电阻、降低半导体结构的电性能和良率。但是，如果增大接触孔的宽度，刻蚀过程又极易损伤接触孔附近的结构或器件，造成整个半导体存储器报废。
本公开示例性实施例提供了一种半导体结构的制作方法，在掩膜结构的外周形成自掩膜结构的周面向中心方向凹陷的凹槽，在刻蚀形成接触孔的过程中，刻蚀产物在凹槽中形成保护层，保护层用于保护掩膜结构避免掩膜结构被刻蚀损伤，确保刻蚀过程中掩膜结构的尺寸不发生变化，根据掩膜结构形成的接触孔的尺寸和掩膜结构定义的待形成的接触孔的尺寸保持一致，避免过刻蚀导致接触孔的尺寸增大。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图2-图21为半导体结构的制作方法的各个阶段的示意图，下面结合图2-图21对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其它的结构。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S110：提供衬底，衬底包括间隔排列的多个有源区以及设置在相邻的有源区之间的隔离结构。
如图2示出了本示例性实施例示出的衬底的示意图，图3示出了本示例性实施例示出的衬底的俯视图，图2是图3的A-A截面的剖面图。
如图2、图3所示，衬底100包括多个独立设置的有源区110，有源区110沿第一方向D1延伸。每个有源区110包括沿第一方向D1依次排列的源区111、中间区域113和漏区112，沿第一方向D1排列的一列有源区110中，任一有源区110的的源区111和相邻的有源区110的漏区112沿第一方向D1交替排列。有源区110的材料包括半导体材料，半导体材料可以包括硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。相邻的有源区110通过隔离结构120隔开，隔离结构120的材料可以为低k介质材料，例如，隔离结构120的材料可以为二氧化硅。
步骤S120：形成多个掩膜结构，多个掩膜结构排列在衬底上，暴露出每个有源区的中间区域，每个掩膜结构包括依次叠置在衬底上的第一掩膜层、第二掩膜层和第三掩膜层，在垂直于衬底的顶面的截面上，第二掩膜层相对于第一掩膜层、第三掩膜层向内凹陷，在第一掩膜层和第三掩膜层之间形成凹槽。
如图8示出了本示例性实施例示出的多个掩膜结构的示意图，如图9示出了本示例性实施例示出的多个掩膜结构的俯视图，图8是图9的A-A截面的剖面图。
如图8、图9所示，参照图2、图3，多个掩膜结构200独立设置在衬底100上，每个掩膜结构200覆盖相邻的两个有源区110的部分顶面以及位于相邻的两个有源区110之间的隔离结构120的部分顶面，多个掩膜结构200在衬底100上定义出了待形成的接触孔130(参照图15、图16)的图案。
如图8、图9所示，多个掩膜结构200覆盖每个有源区110的源区111和漏区112以及部分隔离结构120的顶面，暴露出每个有源区110的中间区域113以及另一部分隔离结构120的顶面，多个掩膜结构200暴露出的中间区域113和隔离结构120的顶面即为多个掩膜结构200定义出的用于形成接触孔130(参照图15、图16)的区域。
如图8、图11所示，每个掩膜结构200包括依次叠置在衬底100上的第一掩膜层210、第二掩膜层220和第三掩膜层230，在第二掩膜层220的宽度小于第一掩膜层210的宽度，且第二掩膜层220的宽度小于第三掩膜层230的宽度，每个掩膜结构200的第二掩膜层220相对于第一掩膜层210、第三掩膜层230向内凹陷，形成自掩膜结构200的周面向中心方向凹陷的凹槽240，每个掩膜结构200在垂直于衬底100的顶面的截面上形成的投影呈“工”形。每个掩膜结构200的第二掩膜层220暴露出第一掩膜层210的部分顶面以及第三掩膜层230的部分底面，第一掩膜层210暴露出的顶面、第三掩膜层230暴露出的底面以及第二掩膜层220的侧壁在每个掩膜结构200的第一掩膜层210和第三掩膜层230之间形成凹槽240。
步骤S130：基于多个掩膜结构刻蚀衬底，去除被多个掩膜结构暴露出的部分有源区，在每个有源区的中间区域形成接触孔，同时，在刻蚀衬底的过程中，在凹槽中形成保护层，保护层覆盖被第二掩膜层暴露出的第一掩膜层。
如图15示出了本示例性实施例示出的形成接触孔的示意图，如图16示出了本示例性实施例示出的形成接触孔的俯视图，图15是图16的A-A截面的剖面图。
如图15、图16所示，参照图8、图9，通过刻蚀工艺刻蚀被多个掩膜结构200暴露出的衬底100，至少去除每个有源区110的中间区域113的部分结构，在每个有源区110的中间区域113形成接触孔130。
如图15、图16所示，参照图8、图9，在本实施例的刻蚀过程中形成的反应产物沉积在凹槽240中形成保护层250，保护层250覆盖被第二掩膜层220暴露出的第一掩膜层210，保护层250用于保护第一掩膜层210避免第一掩膜层210被刻蚀损伤，确保形成接触孔130后，第一掩膜层210的尺寸相对于刻蚀有源区110之前的第一掩膜层210尺寸保持不变，以避免第一掩膜层210在刻蚀过程中被刻蚀去除，掩膜结构200暴露出的有源区110的尺寸增大，导致形成的接触孔130的尺寸大于多个掩膜结构200定义出的待形成的接触孔130的尺寸的问题；且避免第一掩膜层210覆盖的有源区110的源区111和漏区112被刻蚀去除。
本实施例在衬底100中刻蚀形成的接触孔130的尺寸和掩膜结构200定义的待形成的接触孔130的尺寸完全一致，形成的接触孔130具的形貌和尺寸有高精度。其中，本实施例中选用的刻蚀工艺可以为干法刻蚀。
本实施例中，根据多个掩膜结构200在衬底100中形成的接触孔130的尺寸和多个掩膜结构200排列在衬底100上定义出待形成的接触孔130的尺寸完全一致，因此，在确保掩膜结构200覆盖每个有源区110的源区111和漏区112的前提下，在形成掩膜结构200时，可将掩膜结构200定义出的待形成的接触孔130的尺寸设置为最大，以增大形成的接触孔130的宽度，减小在中间区域113形成的接触孔130的深宽比。
步骤S140：于每个接触孔中填充第一材料。
如图20示出了本示例性实施例示出的形成接触结构的示意图，如图21示出了本示例性实施例示出的于每个接触孔中形成接触结构的俯视图，图20是图21的A-A截面的剖面图。
如图20、图21所示，参照图15、图16，可以选用化学气相沉积工艺(Chemical Vapor Deposition，CVD)、物理气相沉积工艺(Physical Vapor Deposition，PVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)或溅镀(sputtering)中的任一种沉积工艺沉积第一材料填充接触孔130，第一材料填充接触孔130，在接触孔130中形成接触结构300。其中，第一材料可以为单晶硅或多晶硅，第一材料中可以掺杂有导电离子。
参照图20、图21所示，本实施例中形成的接触孔130的宽度尺寸大，接触孔130的深宽比小，第一材料在填充接触孔130的过程中，受到接触孔130的深宽比的不良影响小，第一材料能够完全填满接触孔130，确保形成的接触结构300中没有未被填充的缝隙存在，如此，形成的接触结构300的导电性更好、半导体结构的良率更高。
本实施例的半导体结构的制作方法，在刻蚀过程中，形成保护层保护第一掩膜层，以使第一掩膜层覆盖的衬底的尺寸不变，确保在衬底中形成的接触孔的尺寸和掩膜结构在衬底上定义出待形成的接触孔的尺寸完全一致，降低形成的接触孔的深宽比，降低接触孔的填充难度，在接触孔中填充的第一材料没有缝隙。
根据一个示例性实施例，本实施例是对上述实施例的说明，在本实施例中，如图8、图9所示，每个掩膜结构200覆盖相邻的两个有源区110之一有源区110的源区111或漏区112，以及另一有源区110的漏区112或源区111。
如图2、图3所示，每个有源区110在第二方向D2上的宽度为第一宽度L1，位于相邻的两个有源区110之间的隔离结构120在第二方向D2上的宽度为第二宽度L2，每个掩膜结构200在衬底100上形成的投影在第二方向D2上的宽度为第三宽度L3，第一方向D1和第二方向D1相交。
如图8、图9所示，参照图2、图3，本实施例中，2L1+L2＜L3＜2L1+3L2，掩膜结构200的尺寸在此范围内时，既能确保多个掩膜结构200覆盖每个有源区110的源区111和漏区112，避免有源区110的源区111和漏区112被刻蚀损伤，同时在衬底100上形成的掩膜结构200的数量最少，掩膜结构200在衬底100上定义出的待形成的接触孔130的尺寸最大，根据此尺寸范围的掩膜结构200形成的接触孔130的深宽比更小，有利于提高半导体结构的电性能和良率。
根据一个示例性实施例，本实施例是对上述实施例的说明，在本实施例在步骤S120形成多个掩膜结构，包括以下步骤：
步骤S121：形成叠层结构，叠层结构覆盖衬底的顶面，叠层结构包括依次堆叠在衬底上的第一掩膜材料层、第二掩膜材料层和第三掩膜材料层。
如图4所示，参照图2，可以选用化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺或溅镀中的任一种沉积工艺依次沉积第一掩膜材料层211、第二掩膜材料层221和第三掩膜材料层231形成叠层结构260。
参照图4所示，第二掩膜材料层221的材料相对于第一掩膜材料层211的材料和第三掩膜材料层231的材料具有高刻蚀选择比。示例性的，第一掩膜材料层211的材料可以包括第一材料；第二掩膜材料层221的材料可以包括氧化物，比如，第二掩膜材料层221的材料包括氧化硅；第三掩膜材料层231的材料可以包括氮化物，比如，第三掩膜材料层231的材料包括氮化硅或氮氧化硅。在其它实施例中，第一掩膜材料层211、第二掩膜材料层221和第三掩膜材料层231可以选用满足刻蚀选择比的其它材料。
步骤S122：依次刻蚀去除部分第三掩膜材料层、部分第二掩膜材料层和部分第一掩膜材料层，被保留的第一掩膜材料层形成第一掩膜层、被保留的第二掩膜材料层形成第二初始掩膜层、被保留的第三掩膜材料层形成第三掩膜层，第一掩膜层、第二初始掩膜层和第三掩膜层在衬底上形成的投影重合，形成多个初始掩膜结构。
参照图4所示，首先，在第三掩膜材料层231的顶面上形成光刻胶图案280，光刻胶图案280定义有待形成的接触孔130(参照图15、图16)的图案。
如图5所示，然后，根据光刻胶图案280逐层刻蚀第三掩膜材料层231和第二掩膜材料层221。在本实施例中，可以通过干法工艺刻蚀第三掩膜材料层231，比如，可以采用硫化羰(COS)和氧气(O 2)的混合气作为刻蚀气体刻蚀第三掩膜材料层231，去除被光刻胶图案280暴露出的第三掩膜材料层231，被保留的第三掩膜材料层231形成第三掩膜层230。
接着，可以通过干法工艺刻蚀第二掩膜材料层221，比如，可以采用全氟丁二烯(C 4F 6)、八氟环丁烷(C 4F 8)和O 2的混合气作为刻蚀气体，刻蚀去除被第三掩膜层230暴露出的第二掩膜材料层221，被保留的第二掩膜材料层221形成第二初始掩膜层222。
如图6所示，接着，根据第二初始掩膜层222和第三掩膜层230刻蚀第一掩膜材料层211。可以通过干法工艺刻蚀第一掩膜材料层211，比如，可以采用溴化氢(HBr)、氯气(Cl 2)和O 2的混合气作为刻蚀气体，刻蚀去除被第二初始掩膜层222和第三掩膜层230暴露出的第一掩膜材料层211，被保留的第一掩膜材料层211形成第一掩膜层210。
如图6所示，参照图5，被保留的叠层结构260形成多个初始掩膜结构270，每个初始掩膜结构270包括依次堆叠在衬底100上的第一掩膜层210、第二初始掩膜层222和第三掩膜层230，在垂直于衬底100的顶面的截面上，初始掩膜结构270上下等宽。
如图6示出了本示例性实施例示出的形成多个初始掩膜结构的示意图，如图7示出了本示例性实施例示出的形成多个初始掩膜结构的俯视图，图6是图7的A-A截面的剖面图。如图6、图7所示，本实施例形成的多个初始掩膜结构270独立设置，每个初始掩膜结构270的外周面暴露在制程空间中，以使后续步骤中可以处理初始掩膜结构270的周面，在第一掩膜层210和第三掩膜层230之间形成凹槽240(后续会进行详细说明)。
步骤S123：刻蚀每个初始掩膜结构，自第二初始掩膜层的外周面向中心方向，去除部分第二初始掩膜层，在第一掩膜层和第三掩膜层之间形成凹槽，凹槽暴露出第一掩膜层的顶面的周边区域，且凹槽暴露出第三掩膜层的底面的周边区域，被保留的初始掩膜结构形成掩膜结构，被保留的第二初始掩膜层形成第二掩膜层。
如图6所示，自第二初始掩膜层222的外周面向中心方向，刻蚀去除部分第二初始掩膜层222，如图11所示，暴露出第一掩膜层210的顶面的周边区域210a以及第三掩膜层230的底面的周边区域230a，被保留的第二初始掩膜层222形成第二掩膜层220，第二掩膜层220的周面、第一掩膜层210的顶面的周边区域210a以及第三掩膜层230的底面的周边区域230a在第一掩膜层210和第三掩膜层230之间围成凹槽240。
如图8、图9所示，参照图6，每个初始掩膜结构270被保留的部分形成掩膜结构200，每个掩膜结构200包括依次堆叠在衬底100上的第一掩膜层210、第二掩膜层220和第三掩膜层230，第二掩膜层220的宽度小于第一掩膜层210的宽度，第二掩膜层220在衬底100上形成的投影落在第一掩膜层210在衬底100上形成的投影中。
本实施例中，刻蚀第二初始掩膜层222的过程中，选用第二初始掩膜层222相对于刻蚀第一掩膜层210和第三掩膜层230具有高刻蚀选择比的刻蚀工艺，刻蚀工艺刻蚀第一掩膜层210的刻蚀速率为0，避免第一掩膜层210被去除导致有源区110的源区111和漏区112受到刻蚀损伤，避免过刻蚀导致接触孔130(参照图15、图16)的尺寸增大。
示例性的，参照图6、图8、图11所示，刻蚀每个初始掩膜结构270，可以采用以下实施方式：将半导体结构置于电感耦合等离子光谱发生仪(Inductive Coupled Plasma Emission Spectrometer，ICP)中，电感耦合等离子光谱是用于原子发射光谱的主要光源，将电感耦合等离子光谱发生仪的压力调节为60mtorr～100mtorr，电压设置为600W～1000W，射频功率设置为200W～400W，温度设置为30℃～50℃。然后，向电感耦合等离子光谱发生仪通入HBr气体，HBr的流量为200sccm～400sccm，同时，向电感耦合等离子光谱发生仪中通入O 2，或者，通入惰性气体，比如氦气(He)，通过电感耦合等离子光谱发生仪将HBr气体和O 2分别电离成溴等离子体和溴离子体，自第二初始掩膜层222的外周面向中心方向，通过等离子体刻蚀去除部分第二初始掩膜层222。
参照图6、图8、图11所示，本实施例仅去除了部分第二初始掩膜层222，第一掩膜层210没有受到刻蚀影响，掩膜结构200覆盖的衬底100的面积相对于初始掩膜结构270覆盖的衬底100的面积没有发生变化，掩膜结构200定义的待形成的接触孔130的尺寸不变。
本实施例的半导体结构的制作方法，将叠层结构刻蚀成多个独立设置的初始掩膜结构，以暴露出每个初始掩膜结构的外周面，然后将初始掩膜结构刻蚀成具有凹槽的掩膜结构，掩膜结构的第一掩膜层覆盖的衬底的面积不变，多个掩膜结构在每个有源区的中间区域定义出的用于形成接触孔的区域的尺寸不变，能够提高形成的接触孔的精度，以使在中间区域形成的接触孔的尺寸更符合预期。
根据一个示例性实施例，本实施例是对上述实施例的说明，在本实施例中，参照图2所示，提供衬底100后，在衬底100的顶面上沉积形成隔离层140，隔离层140覆盖衬底100的顶面上，用于防止有源区110暴露在制程环境中被氧化污染，隔离层140的材料可以包括氮化硅。本实施例的步骤S130基于多个掩膜结构刻蚀衬底，同时，在刻蚀衬底的过程中，在凹槽中形成保护层，包括以下步骤：
如图10所示，参照图8，首先，基于多个掩膜结构200刻蚀隔离层140，去除被多个掩膜结构200暴露出的隔离层140。本实施例中，可以采用湿法刻蚀去除被多个掩膜结构200暴露出的隔离层140，比如，可以采用浓度为1:200的氢氟酸溶液溶解去除被多个掩膜结构200暴露出的隔离层140，暴露出每个有源区110的中间区域113以及有源区110的中间区域113附近的隔离结构120的顶面。
参照图11、图12、图13、图14、图15所示，参照图8，然后，将半导体结构置于反应腔中，于反应腔中通入刻蚀气体，刻蚀气体在反应腔中解离产生多种等离子体，多种等离子体撞击中间区域113，去除被掩膜结构200暴露出的部分有源区110以及中间区域113附近的部分隔离结构120，在中间区域113形成接触孔130，同时，部分多种等离子体反应生成聚合物，聚合物附着在第三掩膜层230的底面的周边区域230a，自第三掩膜层230的底面的周边区域230a向第一掩膜层210的方向生长，聚合物填充凹槽240形成保护层250，保护层250覆盖第一掩膜层210的顶面的周边区域210a。在本实施例中，反应腔可以为电感耦合等离子光谱发生仪。
本实施例中的刻蚀气体在反应腔中解离产生的多种等离子体至少包括碳等离子体和氧等离子体，以使刻蚀气体被电离产生的等离子体在反应腔中反应生成聚合物。
在一些示例中，向反应腔中通入碳源气体和氧源气体，碳源气体可以包括有机气体和无机气体中的至少一种。比如，向反应腔中通入二氧化碳(CO 2)和O 2，含碳气体和含氧气体在反应腔中被电离成碳等离子体和氧等离子体，碳等离子体和氧等离子体刻蚀去除被掩膜结构200暴露出的部分有源区110，同时，碳等离子体和氧等离子体发生聚合反应生成聚合物，聚合物生长在第三掩膜层230的底面的周边区域230a并填充凹槽240形成保护层250。
在一些实施例中，刻蚀气体在反应腔中解离产生的多种等离子体还包括氟等离子体和氯等离子体。向反应腔中通入碳源气体和氧源气体的同时，向反应腔中通入氟源气体和氯源气体。
比如，在一个示例中，参照图11、图12、图13、图14所示，向反应腔中通入四氟化碳(CF 4)或三氟甲烷(CHF 3)中的至少一种，同时向反应腔中通入O 2、Cl 2，刻蚀气体中C元素含量大于Cl元素的含量和F元素的含量，在电场力的作用下，刻蚀气体被电离产生碳等离子体、氧等离子体、氟等离子体和氯等离子体，多种等离子体撞击被暴露出的有源区110，同时，碳等离子体、氧等离子体、氟等离子体和氯等离子体生成聚合物，聚合物覆盖第三掩膜层230的底面的周边区域230a，并自第三掩膜层230的底面的周边区域230a逐渐向第一掩膜层210的顶面的周边区域210a的方向生长，直至填满凹槽240，在凹槽240中形成保护层250。由于第三掩膜层230的底面的周边区域230a受到刻蚀气体的影响较小，由此可以先在周边区域230a上形成保护层250，进而使得保护层250覆盖第二掩膜层220，进而保护第一掩膜层220不被刻蚀。
本实施例中，多种等离子体发生聚合反应生成的聚合物的分子式为CxOyFzClα，其中x，y，z，α分别为每种元素对应的原子数，1≤x，y，z，α≤6。
参照图11、图12、图13、图14所示，本实施例中，在刻蚀形成接触孔130的过程中，通过控制刻蚀参数和刻蚀条件，控制多种等离子体的撞击速度以及多种等离子体反应生成聚合物的速度，以使在第三掩膜层230的侧壁上形成聚合物的速度和等离子体撞击去除聚合物的速度相同，确保聚合物不会在第三掩膜层230的侧壁上生长，避免影响刻蚀形成的接触孔130的尺寸。
多种等离子体撞击沉积的同时，多种等离子体在反应腔中发生聚合反应生成聚合物，聚合物附着在第三掩膜层230暴露出的表面上，也即，聚合物不仅附着在第三掩膜层230的底面的周边区域230a，还可能会附着在第三掩膜层230的侧壁和顶面上，附着在第三掩膜层230的侧壁的聚合物如果不能及时被去除，会造成掩膜结构200的宽度增加，导致后续根据掩膜结构200刻蚀形成的接触孔130的尺寸缩小。本实施例中，在第三掩膜层230的侧壁上形成聚合物的速度和等离子体撞击去除聚合物的速度相同，避免聚合物附着在第三掩膜层230的侧壁上，避免影响形成的接触孔130的尺寸。
参照图11、图12、图13、图14所示，本实施例中，自第二掩膜层220的外周面向中心方向，向多种等离子体施加偏压，在偏压作用下多种等离子体同时到达第三掩膜层 230的底面的周边区域230a，多种等离子体在第三掩膜层230的底面的周边区域230a发生聚合反应生成聚合物。以使聚合物生长在第三掩膜层230的底面的周边区域230a上，自第三掩膜层230的底面的周边区域230a向第一掩膜层210的顶面的方向生长，避免保护层250延伸到相邻的两个掩膜结构200之间的区域中，保证掩膜结构200的尺寸在刻蚀过程中不发生变化，保证形成的接触孔130的(参照图15、图16)尺寸和多个掩膜结构200在衬底100上定义出的待形成的接触孔130的尺寸完全一致，根据掩膜结构200形成的接触孔130的的形貌和尺寸具有高精度。
根据一个示例性实施例，本实施例是对上述实施例的说明，在本实施例在步骤S140于接触孔中填充第一材料，包括以下步骤：
步骤S141：去除第三掩膜层和保护层。
如图17所示，参照图15，选用对第二掩膜层220和第一掩膜层210具有高刻蚀选择比的刻蚀工艺刻蚀掩膜结构200和保护层250，比如，在一些实施例中，去除第三掩膜层和保护层，可以采用以下实施方式：
调整向反应腔中通入的刻蚀气体的组分，仅向反应腔中通入O 2，O 2在反应腔中被电离成氧等离子体，氧等离子体撞击第三掩膜层230和保护层250，去除第三掩膜层230和保护层250。
如图17所示，去除第三掩膜层230和保护层250，增大了后续向接触孔130中沉积第一材料的工艺窗口，减小了第一材料填充接触孔130的难度，确保第一材料能将接触孔130完全填充，避免在接触孔130中填充的第一材料存在缝隙。
步骤S142：沉积第一材料形成第一材料层，第一材料层填充接触孔并覆盖第一掩膜层和第二掩膜层。
如图18示出了本示例性实施例示出的形成第一材料层的示意图，图19示出了本示例性实施例示出的形成第一材料层的俯视图，图18是图19的A-A截面的剖面图。
如图18、图19所示，参照图17，通过化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺或溅镀中的任一种沉积工艺沉积第一材料形成第一材料层301，第一材料层301填充每个接触孔130、覆盖衬底100被暴露出的顶面、覆盖第一掩膜层210和第二掩膜层220。
本实施例中，第一掩膜层210包括第一材料，如图18、图19所示，第一材料层301和第一掩膜层210相连。
步骤S143：回刻第一材料层，并去除第二掩膜层，每个接触孔中被保留的第一材料层形成接触结构。
如图20、图21所示，参照图18、图19，在一些实施例中，可以刻蚀去除部分第一材料层301、去除部分第一掩膜层210并去除全部的第二掩膜层220，被保留的第一材料层301和被保留的第一掩膜层210相连。如图21所示，接触孔130中的第一材料层301被保留形成接触结构300，位于衬底100的顶面上的被保留的第一材料层301和被保留的第一掩膜层210可以在后续制程中形成其它器件。
以本示例性实施例中形成的接触孔130为位线接触孔进行说明，如图20、图21所示，接触孔130中的第一材料层301被保留形成接触结构300，衬底100顶面上被保留的第一材料层301和被保留的第一掩膜层210形成多条独立设置的位线接触层310，位线接触层310沿第三方向D3延伸。第三方向D3和第一方向D1倾斜相交，第三方向D3和第二方向D2垂直，每条位线接触层310连接沿第三方向D3排列的一列接触结构300，在后续制程中，可以在位线接触层310上形成位线(图中未示出)。
可以理解的是，在其它实施例中，可以刻蚀去除位于衬底100顶面上的第一材料层301并去除全部的第一掩膜层210和全部的第二掩膜层220，暴露出衬底100的顶面，仅保留位于接触孔130中的第一材料层301形成接触结构300，接触结构300中 没有缝隙。
本实施例形成的接触结构300中没有填充缝隙，接触结构300的电阻小、电性能好，在接触结构300上形成其它器件(比如位线)更加牢固，抗倾倒性好，半导体结构良率更高。
根据一示例性实施例，本实施例提供了一种半导体结构，本示例性实施例提供的半导体结构根据上述实施例中的半导体结构的制作方法制作得到。本实施例的半导体结构，接触孔130的深宽比小，接触孔130中的接触结构300中没有缝隙，半导体结构的品质更好、良率更高。
本实施例的半导体结构可以应用于动态随机存储器(DRAM)中。然而，也可以应用于静态随机存取存储器(Static Random Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存取存储器(Magnetic Random Access Memory，MRAM)、相变随机存储器(Phase change Random Access Memory，PRAM)等。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开提供的半导体结构的制作方法及半导体结构中，在掩膜结构的外周形成自掩膜结构的周面向中心方向凹陷的凹槽，在刻蚀形成接触孔的过程中，刻蚀产物在凹槽中形成保护层，保护层用于避免掩膜结构被刻蚀损伤，确保刻蚀过程中掩膜结构的尺寸不发生变化，从而避免过刻蚀导致接触孔尺寸增大。

Claims (15)

  1. 一种半导体结构的制作方法，所述半导体结构的制作方法包括：
    提供衬底，所述衬底包括间隔排列的多个有源区以及设置在相邻的所述有源区之间的隔离结构；
    形成多个掩膜结构，多个所述掩膜结构排列在所述衬底上，暴露出每个所述有源区的中间区域，每个所述掩膜结构包括依次叠置在所述衬底上的第一掩膜层、第二掩膜层和第三掩膜层，在垂直于所述衬底的顶面的截面上，所述第二掩膜层相对于所述第一掩膜层、所述第三掩膜层向内凹陷，在所述第一掩膜层和所述第三掩膜层之间形成凹槽；
    基于多个所述掩膜结构刻蚀所述衬底，去除被多个所述掩膜结构暴露出的部分所述有源区，在每个所述有源区的所述中间区域形成接触孔，同时，在刻蚀所述衬底的过程中，在所述凹槽中形成保护层，所述保护层覆盖被所述第二掩膜层暴露出的所述第一掩膜层；
    于每个所述接触孔中填充第一材料。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，形成多个掩膜结构，包括：
    形成叠层结构，所述叠层结构覆盖所述衬底的顶面，所述叠层结构包括依次堆叠在所述衬底上的第一掩膜材料层、第二掩膜材料层和第三掩膜材料层；
    依次刻蚀去除部分所述第三掩膜材料层、部分所述第二掩膜材料层和部分第一掩膜材料层，被保留的所述第一掩膜材料层形成所述第一掩膜层、被保留的所述第二掩膜材料层形成第二初始掩膜层、被保留的所述第三掩膜材料层形成所述第三掩膜层，所述第一掩膜层、所述第二初始掩膜层和所述第三掩膜层在所述衬底上形成的投影重合，形成多个初始掩膜结构；
    刻蚀每个所述初始掩膜结构，自所述第二初始掩膜层的外周面向中心方向，去除部分所述第二初始掩膜层，在所述第一掩膜层和所述第三掩膜层之间形成所述凹槽，所述凹槽暴露出所述第一掩膜层的顶面的周边区域，且所述凹槽暴露出所述第三掩膜层的底面的周边区域，被保留的所述初始掩膜结构形成所述掩膜结构，被保留的所述第二初始掩膜层形成所述第二掩膜层。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，刻蚀每个所述初始掩膜结构的过程中，所述第二初始掩膜层相对于所述第一掩膜层和所述第三掩膜层具有高刻蚀选择比。
  4. 根据权利要求1所述的半导体结构的制作方法，其中，基于多个所述掩膜结构刻蚀所述衬底，同时，在刻蚀所述衬底的过程中，在所述凹槽中形成保护层，包括：
    于反应腔中通入刻蚀气体，所述刻蚀气体在所述反应腔中解离产生多种等离子体，多种所述等离子体撞击所述中间区域，去除被所述掩膜结构暴露出的部分所述有源区，在所述中间区域形成所述接触孔，同时，部分多种所述等离子体反应生成聚合物，所述聚合物附着在所述第三掩膜层的底面的周边区域，自所述第三掩膜层的底面的周边区域向所述第一掩膜层的方向生长，所述聚合物填充所述凹槽形成所述保护层，所述保护层覆盖所述第一掩膜层的顶面的周边区域。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，基于多个所述掩膜结构刻蚀所述衬底，同时，在刻蚀所述衬底的过程中，在所述凹槽中形成保护层，还包括：
    控制多种所述等离子体的撞击速度以及多种所述等离子体反应生成所述聚合物的速度，以使在所述第三掩膜层的侧壁上形成所述聚合物的速度和所述等离子体撞击去除所述聚合物的速度相同。
  6. 根据权利要求4所述的半导体结构的制作方法，其中，基于多个所述掩膜结构刻蚀所述衬底，同时，在刻蚀所述衬底的过程中，在所述凹槽中形成保护层，还包括：
    自所述第二掩膜层的外周面向中心方向，向多种所述等离子体施加偏压，在偏压作用下多种所述等离子体同时到达所述第三掩膜层的底面的周边区域，反应生成所述聚合物。
  7. 根据权利要求4所述的半导体结构的制作方法，其中，多种所述等离子体至少包括碳等离子体和氧等离子体。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，多种所述等离子体还包括氟等离子体和氯等离子体。
  9. 根据权利要求8所述的半导体结构的制作方法，其特征在于，所述聚合物的分子式为CxOyFzClα，其中x，y，z，α分别为每种元素对应的原子数，1≤x，y，z，α≤6。
  10. 根据权利要求1所述的半导体结构的制作方法，其中，于所述接触孔中填充第一材料，包括：
    去除所述第三掩膜层和所述保护层；
    沉积所述第一材料形成第一材料层，所述第一材料层填充所述接触孔并覆盖所述第一掩膜层和所述第二掩膜层；
    回刻所述第一材料层，并去除所述第二掩膜层，每个所述接触孔中被保留的所述第一材料层形成接触结构。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述第一掩膜层包括所述第一材料，所述第一材料层和所述第一掩膜层相连。
  12. 根据权利要求1所述的半导体结构的制作方法，其中，每个所述掩膜结构覆盖相邻的两个所述有源区的部分顶面以及位于相邻的两个所述有源区之间的所述隔离结构的部分顶面。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，每个所述有源区包括沿第一方向依次排列的源区、所述中间区域和漏区，每个所述掩膜结构覆盖相邻的两个所述有源区之一所述有源区的所述源区或漏区，以及另一所述有源区的所述漏区或所述源区。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，每个所述有源区在第二方向上的宽度为第一宽度，位于相邻的两个所述有源区之间的所述隔离结构在所述第二方向上的宽度为第二宽度，每个所述掩膜结构在所述衬底上形成的投影在所述第二方向上的宽度为第三宽度，所述第一方向和所述第二方向相交；
    2L1+L2＜L3＜2L1+3L2
    其中，L1为所述第一宽度，L2为所述第二宽度，L3为所述第三宽度。
  15. 一种半导体结构，所述半导体结构根据上述权利要求1～14中任一项所述的半导体结构的制作方法制作得到。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103400762A (zh) * 2013-08-26 2013-11-20 中微半导体设备(上海)有限公司 半导体结构的形成方法
CN112289805A (zh) * 2020-10-29 2021-01-29 长江存储科技有限责任公司 凹槽结构的制作方法、三维nand存储器及其制作方法
US20210066090A1 (en) * 2019-09-02 2021-03-04 Kioxia Corporation Manufacturing method of semiconductor device
CN112447726A (zh) * 2019-08-29 2021-03-05 三星电子株式会社 半导体装置及其制造方法
CN112673459A (zh) * 2018-09-11 2021-04-16 铠侠股份有限公司 半导体装置的制造方法和蚀刻气体
CN113517233A (zh) * 2021-07-13 2021-10-19 长鑫存储技术有限公司 半导体结构及其制备方法
CN115148673A (zh) * 2021-03-30 2022-10-04 长鑫存储技术有限公司 半导体结构的制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103400762A (zh) * 2013-08-26 2013-11-20 中微半导体设备(上海)有限公司 半导体结构的形成方法
CN112673459A (zh) * 2018-09-11 2021-04-16 铠侠股份有限公司 半导体装置的制造方法和蚀刻气体
CN112447726A (zh) * 2019-08-29 2021-03-05 三星电子株式会社 半导体装置及其制造方法
US20210066090A1 (en) * 2019-09-02 2021-03-04 Kioxia Corporation Manufacturing method of semiconductor device
CN112289805A (zh) * 2020-10-29 2021-01-29 长江存储科技有限责任公司 凹槽结构的制作方法、三维nand存储器及其制作方法
CN115148673A (zh) * 2021-03-30 2022-10-04 长鑫存储技术有限公司 半导体结构的制造方法
CN113517233A (zh) * 2021-07-13 2021-10-19 长鑫存储技术有限公司 半导体结构及其制备方法

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