WO2024060434A1 - 半导体器件及其制造方法、电子设备 - Google Patents

半导体器件及其制造方法、电子设备 Download PDF

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Publication number
WO2024060434A1
WO2024060434A1 PCT/CN2022/140173 CN2022140173W WO2024060434A1 WO 2024060434 A1 WO2024060434 A1 WO 2024060434A1 CN 2022140173 W CN2022140173 W CN 2022140173W WO 2024060434 A1 WO2024060434 A1 WO 2024060434A1
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layer
substrate
semiconductor
region
capacitor
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English (en)
French (fr)
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王祥升
王桂磊
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present application relates to but is not limited to the field of semiconductor devices, and in particular, to a semiconductor device, a manufacturing method thereof, and electronic equipment.
  • DRAM Dynamic Random Access Memory
  • An embodiment of the present application provides a semiconductor device, including a first chip, where the first chip includes:
  • Each of the memory cells includes a transistor and a capacitor.
  • the transistor includes a semiconductor layer and a gate electrode.
  • the semiconductor layer extends in a direction parallel to the first substrate into a strip-shaped structure.
  • the strip-shaped structure has side surfaces.
  • the wall and both ends, and the sidewalls in a direction parallel to the first substrate include a source region, a channel region and a drain region in sequence, the drain region includes a capacitor region;
  • the gate surrounds The sidewalls of the channel region, and a gate insulation layer is provided between the gate electrode and the channel region;
  • the capacitor is disposed on a side wall of the capacitance region of the drain region;
  • a first internal supporting layer wherein the first internal supporting layer is disposed between capacitor regions of drain regions of two adjacent semiconductor layers in a direction perpendicular to the first substrate, the first internal supporting layer being configured to provide support for the capacitor and the two adjacent semiconductor layers, and the capacitor is separated into a grid-type capacitor by the first internal supporting layer.
  • the first chip further includes: a plurality of word lines, each of which extends on a plane parallel to the first substrate and perpendicular to the extension direction of the semiconductor layer. , wherein a memory cell column is provided in the extending direction of the word line, and each of the word lines is formed by a gate of a transistor of a memory cell in the memory cell column; or, in the word line A plurality of memory cell columns are provided in an extending direction, and each word line is formed by connecting together the gates of transistors of a plurality of memory cells of the plurality of memory cell columns arranged along the extending direction of the word line.
  • the first internal support layer may also be disposed between the capacitance regions of the drain regions of two adjacent semiconductor layers along the extension direction of the word line and along a direction perpendicular to the first extends in the direction of a substrate.
  • the first chip further includes: a plurality of bit lines, each of the bit lines extending in a direction perpendicular to the first substrate and parallel to the extending direction of the semiconductor layer. In the direction, the source regions of the transistors of multiple memory cells in two adjacent memory cell columns are connected to a common bit line.
  • the capacitor may surround the sidewall of the capacitance region of the drain region.
  • the capacitor may include a first electrode plate, a second electrode plate, and a dielectric layer disposed between the first electrode plate and the second electrode plate.
  • the first electrode The plate, the dielectric layer and the second electrode plate are sequentially surrounding the sidewalls of the capacitive region of the drain region.
  • the semiconductor device may further include a second chip, the second chip and the first chip are stacked together, and the second chip and the memory cell column are respectively located on the first chip. On both sides of a substrate, the circuit of the second chip is electrically connected to the circuit of the first chip;
  • the second chip includes a peripheral circuit, a metal contact layer and a metal interconnection layer which are arranged on the second substrate in sequence, and the metal contact layer is arranged on a side of the peripheral circuit away from the second substrate, so
  • the metal interconnection layer is provided on a side of the metal contact layer away from the second substrate and on a side of the first substrate away from the memory cell column, and a metal contact is provided in the metal contact layer. Pillar, a metal line is provided in the metal interconnection layer, one end of the metal line is electrically connected to the bit line, word line or capacitor of the first chip, and the other end of the metal line passes through the metal contact pillar electrically connected to the peripheral circuit.
  • a plurality of word lines at different layers arranged at intervals along a direction perpendicular to the first substrate may be in a stepped shape.
  • the material of the semiconductor layer may be selected from any one or more semiconductor materials formed of Group IVA elements, and the material of the word line may be selected from conductor materials formed of Group IVA elements. any one or more.
  • the material of the semiconductor layer may be single crystal silicon; the material of the word line may be selected from any one or more of polycrystalline silicon and polycrystalline silicon germanium.
  • the memory cell column may further include an interlayer isolation layer, and the interlayer isolation layer is disposed between the gates of the transistors of two adjacent memory cells in the memory cell column, so The interlayer isolation layer is configured to isolate the gates of the transistors of two adjacent memory cells.
  • the semiconductor device may further include one or more memory cell isolation pillars extending in a direction perpendicular to the first substrate, with every two memory cell isolation pillars being spaced in the extending direction of the semiconductor layer.
  • the unit column is provided with one of the storage unit isolation columns.
  • the semiconductor device may further include a second internal support layer, the second internal support layer being disposed between two adjacent semiconductor layers in a direction perpendicular to the first substrate. And located in the non-capacitive region, the second inner support layer is configured to provide support for the semiconductor layer.
  • the first electrode plate may be an internal electrode plate, and the second electrode plate may be an external electrode plate; the drain region may be connected to the first electrode plate.
  • An embodiment of the present application also provides a method for manufacturing a semiconductor device, including:
  • a plurality of composite layers composed of the first sacrificial layer and the semiconductor layer are stacked on one side of the first substrate in the order of the first sacrificial layer and the semiconductor layer in a direction perpendicular to the first substrate;
  • the remaining semiconductor layer extends in a direction parallel to the first substrate and sequentially includes a source region, a channel region and a drain region, the drain region includes a capacitor region;
  • the semiconductor layer and the gate electrode constitute a transistor
  • the second sacrificial layer on the sidewall of the capacitor region of the drain region of the semiconductor layer is removed, and capacitors are sequentially formed on the sidewalls of the capacitor region of the drain region of the semiconductor layer to obtain the first chip.
  • the manufacturing method of the semiconductor device may further include: forming a plurality of word lines extending on a plane parallel to the first substrate and perpendicular to the extension direction of the semiconductor layer;
  • a semiconductor layer is provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that the gate electrode on the semiconductor layer serves as a word line; or, on a plane parallel to the A plurality of semiconductor layers are disposed on the plane of the first substrate and along an extending direction perpendicular to the semiconductor layer, so that gate electrodes on the plurality of semiconductor layers are connected together to form a word line.
  • the manufacturing method of the semiconductor device may further include: forming a plurality of bit lines extending in a direction perpendicular to the first substrate;
  • bit lines includes:
  • bit line groove is etched in the plurality of composite layers along a direction perpendicular to the first substrate, and an isolation material is filled in the bit line groove;
  • the isolation material in the bit line trench is removed, the bit line trench is filled with bit line material to form a bit line, and the bit line and a plurality of semiconductors in contact with the bit line are The source regions of the plurality of semiconductor layers are connected such that the source regions of the plurality of semiconductor layers share a bit line.
  • the manufacturing method of the semiconductor device may further include:
  • a peripheral circuit, a metal contact layer with metal contact posts, and a metal interconnection layer with metal lines are sequentially arranged on one side of the second substrate, and one end of the metal line is connected to the metal contact post through the metal contact post.
  • the peripheral circuits are electrically connected to obtain a second chip;
  • the first chip and the second chip are stacked together, and the circuit of the second chip is electrically connected to the circuit of the first chip.
  • Forming the first inner support layer may include:
  • the trenches are etched sideways, and first internal support grooves are formed in the first sacrificial layer of each composite layer.
  • the first internal support grooves are filled with support material to form a vertical axis along the The first internal support layer between the capacitance regions of the drain regions of two adjacent semiconductor layers in the direction of the first substrate; or,
  • sequentially forming capacitors on the sidewalls of the capacitive region of the drain region of the semiconductor layer may include: sequentially forming capacitors on the sidewalls of the capacitive region of the drain region of the semiconductor layer.
  • the first electrode plate, the dielectric layer and the second electrode plate surrounding the side walls of the capacitor region constitute the capacitor.
  • An embodiment of the present application also provides an electronic device, including the semiconductor device provided in the above embodiment of the present application.
  • FIG. 1A is a schematic front cross-sectional structural diagram of a semiconductor device according to an exemplary embodiment of the present application
  • FIG. 1B is a schematic cross-sectional structural view of the semiconductor device shown in FIG. 1A;
  • FIG. 1C is an enlarged view of the transistor of the semiconductor device shown in FIG. 1A;
  • FIG. 1D is an enlarged view of the capacitor of the semiconductor device shown in FIG. 1A;
  • FIG. 2A is a schematic front cross-sectional structural diagram of another semiconductor device according to an exemplary embodiment of the present application.
  • Figure 2B is a schematic top view structural diagram of the conductor device shown in Figure 2A;
  • FIG. 3 is a distribution state diagram in a side view direction of a plurality of word lines spaced apart in a direction perpendicular to the first substrate of the semiconductor device according to an exemplary embodiment of the present application;
  • 4A is a schematic front cross-sectional structural view of the second chip of the semiconductor device according to an exemplary embodiment of the present application.
  • FIG. 4B is a schematic top structural view of the second chip of the semiconductor device shown in FIG. 3A;
  • Figure 5 is a process flow diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.
  • 6A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 6B is a schematic top structural view of the intermediate product shown in Figure 6A;
  • FIG. 7A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 7B is a schematic top structural view of the intermediate product shown in Figure 7A;
  • FIG. 8A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 8B is a schematic top structural view of the intermediate product shown in Figure 8A;
  • 9A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.
  • Figure 9B is a schematic top structural view of the intermediate product shown in Figure 9A;
  • 10A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 10B is a schematic top structural view of the intermediate product shown in Figure 10A;
  • 11A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • FIG. 11B is a schematic top structural view of the intermediate product shown in FIG. 11A.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • set and “connection” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • film and “layer” may be interchanged.
  • dielectric layer may sometimes be replaced by “dielectric film”.
  • An embodiment of the present application provides a semiconductor device.
  • the semiconductor device includes a first chip.
  • the first chip includes:
  • Each of the memory cells includes a transistor and a capacitor.
  • the transistor includes a semiconductor layer and a gate electrode.
  • the semiconductor layer extends in a direction parallel to the first substrate into a strip-shaped structure.
  • the strip-shaped structure has side surfaces.
  • the wall and both ends, and the sidewalls in a direction parallel to the first substrate include a source region, a channel region and a drain region in sequence, the drain region includes a capacitor region;
  • the gate surrounds The sidewalls of the channel region, and a gate insulating layer is provided between the gate and the channel region; the capacitor is provided on the sidewalls of the capacitance region of the drain region;
  • a first internal support layer is disposed between the capacitor regions of the drain regions of two adjacent semiconductor layers in a direction perpendicular to the first substrate, the first internal support layer A layer is configured to provide support for the capacitor and two adjacent semiconductor layers, the capacitor being spaced by the first inner support layer as a grid of capacitors.
  • the first chip may further include: a plurality of word lines, each of which extends on a plane parallel to the first substrate and perpendicular to the extension of the semiconductor layer. direction, wherein a memory cell column is provided in the extending direction of the word line, and each of the word lines is formed by a gate of a transistor of a memory cell in the memory cell column; or, in the word line A plurality of memory cell columns are provided in the extending direction, and each word line is formed by connecting together the gates of the transistors of a plurality of memory cells of the plurality of memory cell columns arranged along the extending direction of the word line.
  • the first internal support layer may also be disposed between the capacitance regions of the drain regions of two adjacent semiconductor layers along the extension direction of the word line and along a direction perpendicular to the first extends in the direction of a substrate.
  • the first chip may further include: a plurality of bit lines, each of the bit lines extending in a direction perpendicular to the first substrate and in the extending direction of the semiconductor layer. In a parallel direction, the source regions of the transistors of multiple memory cells in two adjacent memory cell columns are connected to a common bit line.
  • the capacitor may surround the sidewall of the capacitance region of the drain region.
  • the semiconductor device provided by the embodiment of the present application can be applied in the field of DRAM, for example, can be applied to DRAM with 3D memory cells formed by a superlattice structure.
  • a multi-layer superlattice on a substrate can be used to form multi-layer memory cells.
  • Each layer of memory cells can be array-distributed memory cells.
  • the memory cells at the same position in each layer in the two-dimensional plane form a vertical direction.
  • a column of storage units is referred to as a storage unit column.
  • Figure 1A is a schematic front cross-sectional structural view of a semiconductor device according to an exemplary embodiment of the present application
  • Figure 1B is a schematic top cross-sectional structural view of the semiconductor device shown in Figure 1A
  • Figure 1C is a schematic diagram of a transistor of the semiconductor device shown in Figure 1A Magnified view
  • FIG. 1D is an enlarged view of the capacitor of the semiconductor device shown in FIG. 1A.
  • the semiconductor device may include: a first chip 1000.
  • the first chip 1000 includes: a first substrate 100, a plurality of memory cell columns 200, and a plurality of bit lines 300. , BL), a plurality of word lines 400 (Word Line, WL) and a first internal support layer 501.
  • Each memory cell column 200 is perpendicular to the first substrate 100 and is formed by a plurality of memory cells 1 stacked on one side of the first substrate 100 .
  • Each memory cell 1 includes a transistor 10 and a capacitor 20.
  • the transistor 10 includes a semiconductor layer 11 and a gate electrode 12.
  • the semiconductor layer 11 extends in a direction parallel to the first substrate 100 into a strip-shaped structure having side surfaces. Walls and both ends, the cross-section of the strip structure can be rectangular, circular, elliptical, etc., and the sidewalls in the direction parallel to the first substrate include a source region 111 and a channel region in sequence 112 and the drain region 113, the drain region 113 includes a capacitor region; the gate 12 surrounds the sidewall of the channel region 112, and a gate insulating layer is provided between the gate 12 and the channel region 112 (not shown in the figure) ).
  • the capacitor 20 is disposed on the sidewall of the capacitance region of the drain region 113 , that is, the capacitor 20 is disposed between two adjacent semiconductor layers.
  • the capacitor 20 is surrounded by the sidewalls of the capacitive region of the drain region 113 , that is, the capacitor 20 is set on the sidewalls around the capacitive region of the drain region 113 .
  • the capacitor 20 may be disposed on sidewalls on opposite sides of the capacitance region of the drain region 113 .
  • the capacitor 20 includes a first electrode plate 21, a second electrode plate 22, and a dielectric layer 23 disposed between the first electrode plate 21 and the second electrode plate 22,
  • the first electrode plate 21 , the dielectric layer 23 and the second electrode plate 22 are sequentially surrounding the sidewalls of the capacitor region of the drain region 113 .
  • Each bit line 300 extends in a direction perpendicular to the first substrate 100, and in a direction parallel to the extension direction of the semiconductor layer 11, the source regions 111 of the transistors 10 of the multiple memory cells 1 of two adjacent memory cell columns 200 are connected to a common bit line 300.
  • bit line 300 For example, two adjacent memory cells 1 along the extension direction of the semiconductor layer are distributed in a mirror image, and the source regions 111 of the transistors 10 of the two adjacent memory cells 1 are connected to a common bit line 300.
  • Every two adjacent memory cells along the extension direction of the semiconductor layer are regarded as a repeating unit as a whole.
  • each repeating unit includes two memory cells that are mirror-symmetrical in structure.
  • two transistors are arranged adjacent to each other, and capacitors located on a semiconductor layer are located at both ends.
  • a bit line 300 distributed along a direction perpendicular to the substrate is arranged between the two adjacent transistors, and the transistors and capacitors in the two memory cells are distributed mirror-symmetrically about the bit line 300.
  • Each word line 400 extends on a plane parallel to the first substrate 100 and perpendicular to the extension direction of the semiconductor layer 11 , wherein a memory cell column 200 is provided in the extension direction of the word line 400 , and each word line 400 is formed by the gate electrode 12 of the transistor 10 of one memory cell 1 in each layer of the one memory cell column 200; alternatively, multiple memory cell columns 200 are provided in the extending direction of the word line 400, and each word line 400 is formed by The gate electrodes 12 of the transistors 10 of the plurality of memory cells 1 arranged along the extending direction of the word line 400 in the plurality of memory cell columns 200 and located in the same layer are connected together to form.
  • the first inner support layer 501 is disposed between the capacitor regions of the drain regions 113 of two adjacent semiconductor layers 11 in a direction perpendicular to the first substrate 100 , and is configured to provide support to the capacitor 20 and Two adjacent semiconductor layers 11 provide support, and the capacitor 20 is separated by the first inner support layer 501 to form a mesh capacitor.
  • bit lines 300 there are three bit lines 300 in the semiconductor device shown in Figures 1A and 1B; the semiconductor device shown in Figures 1A and 1B is a three-layer supercrystalline There are three layers of memory cells formed by a grid, and each layer of memory cells corresponds to two word lines 400. There are a total of six word lines 400 in the semiconductor device shown in FIG. 1A and FIG. 1B.
  • each memory cell column is formed by a plurality of memory cells arranged on one side of the first substrate along a stack perpendicular to the first substrate; this application refers to one or more memory cells belonging to the same layer.
  • the group of memory cells are stacked in a direction perpendicular to the first substrate, and memory cell groups of different stacks form columns extending in a direction perpendicular to the first substrate.
  • the plurality of groups form an array, that is to say, the memory cell groups of each layer form an array, or multiple columns of stacked memory cell groups form an array, for example, different memory cell columns 200 are arranged on the first substrate 100 along the extending direction of the semiconductor layer and the extending direction of the word lines to form an array.
  • the semiconductor device of the embodiment of the present application adopts a lateral semiconductor layer (that is, a semiconductor layer extending in a direction parallel to the first substrate) and a lateral capacitor (that is, the capacitor is arranged between the semiconductor layers of the transistor instead of being arranged between The left and right sides of the transistor), so that the transistors and capacitors can form a three-dimensional stacked structure, and the memory cells formed by the transistors and capacitors can be stacked together in a direction perpendicular to the first substrate, increasing the storage density of the semiconductor device; in addition, the third The design of an internal support layer enables the capacitor to have a grid capacitance structure, which can support the longer lateral capacitor and prevent the longer lateral capacitor from collapsing during selective etching.
  • the sources of the transistors of multiple memory cells in two adjacent memory cell columns can share a bit line, which can reduce the size of the semiconductor device, Further increasing the storage density of semiconductor devices, thereby reducing the production cost per Gb, provides a new technology research and development direction under the shrinkage bottleneck of DRAM.
  • the first internal support layer 501 may also be disposed between the capacitive regions of the drain regions of two adjacent semiconductor layers 11 along the extension direction of the word line 400 and along the extension direction of the word line 400 . Extends perpendicular to the direction of the first substrate 100 .
  • a memory cell column may be formed by 2 to 100 memory cells stacked in a direction perpendicular to the first substrate.
  • it may be formed by 2, 3, 4, or 5 memory cells. 10, 13, 15, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 storage units are formed.
  • the plurality of memory cell columns are arranged on the first substrate along the extension direction of the semiconductor layer and the extension direction of the word line to form an array; here, it can be understood that each layer A group of memory cells forms an array, or multiple columns formed by multiple stacked memory cell groups form an array.
  • 2 to 1000 memory cell columns may be provided along the extending direction of the semiconductor layer.
  • 2, 4, 6, 8, 10, or 12 memory cell columns may be provided.
  • 1 to 100 memory cell columns can be provided along the extending direction of the word line, for example, 1 or 2 can be provided , 3, 4, 5, 12, 14, 16, 18, 20, 30, 40, 50, 60, 70, 80, 90, 100 storage units List.
  • the structure of the mesh capacitor may refer to the structure of the mesh capacitor of the 1z technology node.
  • the number of the first internal support layers can be set according to the length of the capacitor, so that the capacitor has a grid structure.
  • a first inner support layer can be provided every 200nm to 300nm; the length of the capacitor at the current 1z technology node is approximately 1000nm, in which two first inner support layers can be provided.
  • FIG. 2A is a schematic front cross-sectional structural view of another semiconductor device according to an exemplary embodiment of the present application
  • FIG. 2B is a schematic top structural view of the semiconductor device shown in FIG. 2A
  • the semiconductor device may further include a second chip 2000.
  • the second chip 2000 and the first chip 1000 are stacked together and the second chip 2000 and the storage device 1000 are stacked together.
  • the unit columns 200 are respectively located on both sides of the first substrate 100, and the circuit of the second chip 2000 is electrically connected to the circuit of the first chip 1000;
  • the second chip 2000 includes a peripheral circuit 600, a metal contact layer 700 and a metal interconnection layer 800 which are arranged in sequence on the second substrate 3000.
  • the metal contact layer 700 is arranged on the side of the peripheral circuit 600 away from the second substrate 3000.
  • the interconnection layer 800 is disposed on a side of the metal contact layer 700 away from the second substrate 3000 and on a side of the first substrate 100 away from the memory cell column 200.
  • the metal contact layer 700 includes a metal contact pillar 701 and an insulating dielectric.
  • the connecting layer 800 includes a metal wire 801 and an insulating medium.
  • One end of the metal wire 801 is electrically connected to the bit line 300, the word line 400 of the first chip 1000, or the second electrode plate of the capacitor 20 (which can be determined according to the specific circuit).
  • the other end of 801 is electrically connected to the peripheral circuit 600 through the metal contact post 701 .
  • the memory units and peripheral circuits are respectively arranged on the substrates of different chips, and the CuA (CMOS under Array) structure is used to set the peripheral circuits below the memory unit columns, so the peripheral circuits do not occupy
  • the area of the first substrate of the first chip where the memory unit is located can be provided with memory units on the entire first substrate, so that more memory units can be provided on the limited first substrate area, thereby improving the semiconductor memory storage density.
  • the first substrate may be a semiconductor substrate, for example, a single crystal silicon substrate, or a semiconductor on insulator (SOI) substrate, for example, silicon on sapphire. (Silicon On Sapphire, SOS) substrate, Silicon On Glass (SOG) substrate, silicon epitaxial layer based on the base semiconductor or other semiconductor or optoelectronic materials, such as silicon-germanium (Si 1-x Ge x , where x can be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN) or indium phosphide (InP).
  • the first substrate may be doped or undoped; the second substrate may be a doped or undoped single crystal silicon substrate.
  • the material of the bit line may be selected from any one or more of tungsten, molybdenum, cobalt and other metal materials with similar properties.
  • FIG. 3 is a distribution state diagram in a side view direction of a plurality of word lines spaced apart in a direction perpendicular to the first substrate of the semiconductor device according to an exemplary embodiment of the present application.
  • the lengths of the multiple word lines 400 located at different layers and spaced apart along the direction perpendicular to the first substrate 100 may be different, so that the lengths of the word lines 400 arranged along the direction perpendicular to the first substrate 100 may be different.
  • the plurality of word lines 400 located at different layers arranged in the direction of the substrate 100 may be in a ladder shape.
  • the material of the semiconductor layer may be selected from any one or more types of semiconductor materials formed of Group IVA elements.
  • the material of the semiconductor layer may be single crystal silicon.
  • the material of the word line may be a material compatible with the semiconductor layer.
  • the material of the word line may be selected from any one or more conductor materials formed of Group IVA elements.
  • the material of the word line may be selected from any one or more of polysilicon, polysilicon germanium, and the like.
  • Semiconductor materials formed of Group IVA elements and conductor materials formed of Group IVA elements are both formed of Group IVA elements, and they can be better compatible with each other.
  • the height of the semiconductor layer in the direction perpendicular to the first substrate can be set according to actual electrical requirements, for example, it can be 10 nm to 50 nm.
  • the first electrode plate may be an inner electrode plate
  • the second electrode plate may be an outer electrode plate.
  • the drain region 113 may be connected to the first electrode plate 21 (ie, the internal electrode plate).
  • the second electrode plates 22 of a plurality of capacitors 20 arranged in a direction parallel to the extending direction of the word line can be connected together, but their first electrode plates 21 are separated.
  • one transistor 10 may correspond to one capacitor 20 , that is, the storage unit 1 may be a 1T1C structure.
  • two adjacent capacitors in a direction perpendicular to the first substrate may share an external electrode plate.
  • the materials of the first electrode plate and the second electrode plate can be independently selected from titanium nitride (for example, TiN), aluminum-titanium-based alloy (for example, TiAl), tantalum nitride (For example, TaN) and other other metallic materials with similar properties.
  • the thickness of the first electrode plate may be 5 nm to 15 nm, and the thickness of the second electrode plate may be 5 nm to 15 nm.
  • the material of the dielectric layer may be a high dielectric constant (K) material, for example, may be selected from any one or more of hafnium oxide (e.g., HfO 2 ), aluminum oxide (e.g., Al 2 O 3 ), zirconium oxide (e.g., ZrO) and strontium titanate (e.g., SrTiO 3 , STO).
  • K dielectric constant
  • the thickness of the dielectric layer may be 5 nm to 15 nm.
  • the memory cell column 200 may also include an interlayer isolation layer 2 , and the interlayer isolation layer 2 is provided between two adjacent memory cells 1 in the memory cell column 200 . Between the gate electrodes 12 of the transistors 10, the gate electrodes 12 of the transistors 10 of two adjacent memory cells 1 are isolated.
  • the material of the interlayer isolation layer may be silicon oxide, for example, SiO 2 .
  • the semiconductor device may further include one or more memory cell isolation pillars 3 extending in a direction perpendicular to the first substrate.
  • one memory cell isolation pillar 3 may be provided every two memory cell columns 200 in the extending direction of the semiconductor layer.
  • the material of the memory cell isolation pillar may be silicon oxide, for example, it may be selected from spin-on deposition (SOD) silicon oxide film, high density plasma (HDP) ) silicon oxide film and high aspect ratio process (High Aspect Ratio Process, HARP) silicon oxide film any one or more.
  • SOD spin-on deposition
  • HDP high density plasma
  • HARP High Aspect Ratio Process
  • the material of the gate insulating layer may be selected from silicon oxide (for example, SiO 2 ), hafnium oxide (for example, HfO 2 ), zirconium oxide (for example, ZrO) and aluminum oxide (for example, Al 2 O 3 ) any one or more.
  • the gate insulating layer may be a single layer or multiple layers.
  • it may include a two-layer structure formed of silicon oxide and hafnium oxide, where the silicon oxide layer is in contact with the channel region and the hafnium oxide layer is in contact with the channel region. layer in contact with the gate.
  • the thickness of the gate insulating layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.
  • the semiconductor device may further include a second inner support layer 502 , and the second inner support layer 502 is disposed adjacent to the first substrate in a direction perpendicular to the first substrate. Between the two semiconductor layers 11 and located in the non-capacitive region, the second inner support layer 502 is configured to provide support to the semiconductor layer 11 .
  • the second inner support layer 502 may be located on both sides of the bit line 300 , or may be located on both sides of the bit line 300 and both sides of the memory cell isolation pillar 3 .
  • the second inner support layer 502 is provided on both sides of the bit line 300 and the memory cell isolation pillar 3 , a stronger support can be provided to the semiconductor layer 11 .
  • the material of the first inner support layer and the second inner support layer may be a thin film material with a supporting function, for example, it may be silicon nitride (eg, SiN).
  • the semiconductor device may further include a second sacrificial layer 902 , which is disposed in the blank space of the first chip 1000 and covers the semiconductor layer. 11.
  • the material of the second sacrificial layer may be a dielectric material, for example, it may be any one or more of other materials with similar properties such as silicon oxide (eg, SiO 2 ).
  • the second chip may adopt a commonly used peripheral circuit chip structure.
  • the peripheral circuit may be a CMOS transistor.
  • FIG. 4A is a schematic front cross-sectional structural view of the second chip of the semiconductor device according to an exemplary embodiment of the present application
  • FIG. 4B is a schematic top structural view of the second chip of the semiconductor device shown in FIG. 3A
  • the peripheral circuit 600 may include a first transistor 601 and a second transistor 602.
  • the first transistor 601 and the second transistor 602 may be arranged side by side on the second substrate 3000.
  • a first type well 603 may be disposed between the first transistor 601 and the second substrate 3000, and a second type well 604 may be disposed between the second transistor 602 and the second substrate 3000;
  • a transistor 601 may include a first source electrode 6011, a first drain electrode 6012, a first channel 6013 disposed between the first source electrode 6011 and the first drain electrode 6012, and a first channel 6013 disposed on one side of the first channel 6013.
  • the materials of a gate 6014, the first source 6011 and the first drain 6012 can be the same, for example, they can all be N-type semiconductor material or P-type semiconductor material, the material of the first channel 6013 and the first type well 603
  • the materials are the same, which can be P-type semiconductor materials or N-type semiconductor materials, but the materials of the first source electrode 6011, the first drain electrode 6012, the first channel 6013, and the first type well 603 are different; the materials of the first channel 6013 and A first gate insulation layer (or gate oxide layer, not shown in the figure) may also be provided between the first gate electrodes 6014;
  • the second transistor 602 includes a second source electrode 6021, a second drain electrode 6022, and is disposed on The second channel 6023 between the second source electrode 6021 and the second drain electrode 6022, the second gate electrode 6024 provided on one side of the second channel 6023, the second source electrode 6021 and the second drain electrode 6022 are made of the same material , both can be P-type semiconductor material or N-type
  • the second drain electrode 6022 is made of different materials from the second channel 6023 and the second type well 604; a second gate insulating layer (or gate oxide layer) can also be provided between the second channel 6023 and the second gate electrode 6024. , not shown in the figure).
  • the first transistor 601 and the second transistor 602 may be arranged side by side on the same plane.
  • the first transistor and the second transistor may be connected to different metal contact pillars, and the other end of the metal contact pillar is connected to the bit line and word line of the first chip through the metal line. or capacitor electrical connection.
  • the first transistor and the second transistor may be gate transistors.
  • the peripheral circuit may further include a third transistor, and the third transistor may be disposed on the same plane as the first transistor and the second transistor.
  • the material of the metal wire can be selected from any one or more of copper and aluminum, for example, it can be copper; the material of the metal contact column can be selected from any one or more of tungsten and molybdenum, for example, it can be tungsten.
  • the semiconductor device may be a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • An embodiment of the present application also provides a method for manufacturing a semiconductor device. As described above, the semiconductor device provided by the embodiment of the present application can be obtained by this manufacturing method.
  • FIG. 5 is a process flow diagram of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application. As shown in Figure 5, the manufacturing method may include:
  • S10 Stack a first sacrificial layer and a semiconductor layer in order on one side of the first substrate in a direction perpendicular to the first substrate to form a plurality of composites composed of the first sacrificial layer and the semiconductor layer. layer;
  • S20 Etch trenches in a plurality of composite layers in a direction perpendicular to the first substrate, and perform side etching on the trenches to form a plurality of trenches perpendicular to the first substrate. spacing grooves and forming first internal support grooves in the first sacrificial layer of each composite layer, the spacing grooves spacing a plurality of the composite layers into a plurality of composite walls perpendicular to the first substrate , the first internal support groove separates the first sacrificial layer into a grid structure, and the first internal support groove is filled with support material to form a first internal support layer;
  • S40 Form a second sacrificial layer on the first substrate so that the second sacrificial layer covers the semiconductor layer;
  • S50 Remove the second sacrificial layer on the sidewalls of the channel region of the semiconductor layer, and sequentially form a gate insulating layer and a gate electrode surrounding the channel region on the sidewalls of the channel region of the semiconductor layer,
  • the semiconductor layer and the gate electrode constitute a transistor
  • the manufacturing method of a semiconductor device may further include: forming a plurality of bit lines extending in a direction perpendicular to the first substrate;
  • bit lines includes:
  • Step S20 When etching the trenches in the plurality of composite layers, etching bit line trenches in the plurality of composite layers in a direction perpendicular to the first substrate, and etching the bit line grooves in the plurality of composite layers. Fill the groove with isolation material;
  • S70 remove the isolation material in the bit line slot, fill the bit line slot with bit line material to form a bit line, and contact the bit line with the bit line
  • the source regions of the plurality of semiconductor layers are connected such that the source regions of the plurality of semiconductor layers share a bit line.
  • step S50 may further include forming a plurality of word lines extending on a plane parallel to the first substrate and perpendicular to the extension direction of the semiconductor layer;
  • a semiconductor layer is provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that the gate electrode on the semiconductor layer serves as a word line; or, on a plane parallel to the A plurality of semiconductor layers are disposed on the plane of the first substrate and along an extending direction perpendicular to the semiconductor layer, so that gate electrodes on the plurality of semiconductor layers are connected together to form a word line.
  • the manufacturing method of the semiconductor device may include:
  • S10 Stack a first sacrificial layer and a semiconductor layer in order on one side of the first substrate in a direction perpendicular to the first substrate to form a plurality of composites composed of the first sacrificial layer and the semiconductor layer. layer;
  • S20 etching a bit line groove and a trench in the plurality of composite layers along a direction perpendicular to the first substrate, and performing side etching on the trench to form a plurality of spacing grooves perpendicular to the first substrate and forming a first internal supporting groove in the first sacrificial layer of each composite layer, wherein the spacing grooves separate the plurality of composite layers into a plurality of composite walls perpendicular to the first substrate, and the first internal supporting grooves separate the first sacrificial layers into a grid structure, filling the first internal supporting grooves with a supporting material to form a first internal supporting layer, and filling the bit line grooves with an isolation material;
  • S30 Remove the remaining first sacrificial layer.
  • the remaining semiconductor layer extends in a direction parallel to the first substrate and sequentially includes a source region, a channel region and a drain region, and the drain region includes a capacitor region;
  • S40 Form a second sacrificial layer on the first substrate so that the second sacrificial layer covers the semiconductor layer;
  • S50 Remove the second sacrificial layer on the sidewalls of the channel region of the semiconductor layer, and sequentially form a gate insulating layer and a gate electrode surrounding the channel region on the sidewalls of the channel region of the semiconductor layer,
  • the semiconductor layer and the gate constitute a transistor; and, a semiconductor layer is provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, such that the one semiconductor layer
  • the gate electrode serves as a word line; or, a plurality of semiconductor layers are provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that the gate electrodes on the plurality of semiconductor layers connected together to form word lines;
  • S60 Remove the second sacrificial layer on the sidewalls of the capacitive region of the drain region of the semiconductor layer, and sequentially form a first electrode surrounding the capacitive region on the sidewalls of the capacitive region of the drain region of the semiconductor layer. plate, a dielectric layer and a second electrode plate, the first electrode plate, the dielectric layer and the second electrode plate forming a capacitor;
  • S70 removing the isolation material in the bit line groove, filling the bit line groove with bit line material to form a bit line, connecting the bit line and the source regions of the multiple semiconductor layers in contact with the bit line, so that the source regions of the multiple semiconductor layers share one bit line, and obtaining a first chip.
  • step S20 may include:
  • Bit line grooves and trenches are etched in the multiple composite layers in a direction perpendicular to the first substrate, and side etching is performed on the trenches to form a plurality of bit line trenches perpendicular to the first substrate.
  • spacing grooves of the substrate and forming first internal support grooves in the first sacrificial layer of each composite layer the spacing grooves spacing a plurality of the composite layers into a plurality of perpendicular to the first substrate A composite wall, the first internal support grooves space the first sacrificial layer into a grid structure, the first internal support grooves are filled with support material, and are formed in a direction perpendicular to the first substrate.
  • a first internal support layer between the capacitance regions of the drain regions of two adjacent semiconductor layers, and filling the bit line trench with an isolation material; or,
  • Bit line grooves and trenches are etched in the plurality of composite layers in a direction perpendicular to the first substrate, and support materials are filled in the trenches to form a groove arranged along the extending direction of the word line.
  • a first internal support layer between the capacitance regions of the drain regions of two adjacent semiconductor layers and extending in a direction perpendicular to the first substrate; perform side etching on the trench to form multiple a spacing groove perpendicular to the first substrate and forming a first internal support groove in the first sacrificial layer of each composite wall, the spacing groove spacing a plurality of the composite layers into a plurality of composite layers perpendicular to The composite wall of the first substrate, the first internal support grooves space the first sacrificial layer into a grid structure, the first internal support grooves are filled with support material, and are formed along the edge perpendicular to the a first internal support layer between the capacitance region of the drain region of two adjacent semiconductor layers in the direction of the first substrate, and an isolation material
  • step S20 may include:
  • S21 Etch memory cell isolation trenches, bit line trenches and trenches in the plurality of composite layers in a direction perpendicular to the first substrate;
  • S22 Fill the trench with a support material to form a capacitor region between the drain regions of two adjacent semiconductor layers along the extension direction of the word line and perpendicular to the first substrate.
  • a first internal support layer extending in the direction; performing side etching on the trench to form a plurality of spaced trenches perpendicular to the first substrate and forming a first sacrificial layer in each composite layer First internal support grooves, the spacing grooves space the plurality of composite layers into a plurality of composite walls perpendicular to the first substrate, the first internal support grooves space the first sacrificial layer into meshes
  • a lattice structure is filled with support material in the first internal support groove to form a first capacitor region disposed between the drain regions of two adjacent semiconductor layers in a direction perpendicular to the first substrate.
  • S23 Perform side etching on the memory cell isolation trench, so that a second internal support trench is formed in the first sacrificial layer of each composite wall, where the second internal support trench is located in the first sacrificial layer of each composite wall.
  • fill the second internal support groove with support material, and the support material in the second internal support groove forms a second internal support layer;
  • S24 Perform side etching on the bit line trenches to form a second internal support trench in the first sacrificial layer of each composite wall, where the second internal support trench is located on the bit line. On both sides of the groove, support material is filled in the second internal support groove, and the support material in the second internal support groove forms a second internal support layer;
  • S25 Fill the memory cell isolation trench with memory cell isolation pillars and fill the bit line trench with isolation material.
  • Step S20 may include:
  • S21 Etch memory cell isolation trenches, bit line trenches and trenches in the plurality of composite layers in a direction perpendicular to the first substrate;
  • S22 Fill the trench with a support material to form a capacitor region between the drain regions of two adjacent semiconductor layers along the extension direction of the word line and perpendicular to the first substrate.
  • a first internal support layer extending in the direction; performing side etching on the trench to form a plurality of spaced trenches perpendicular to the first substrate and forming a first sacrificial layer in each composite layer First internal support grooves, the spacing grooves space the plurality of composite layers into a plurality of composite walls perpendicular to the first substrate, the first internal support grooves space the first sacrificial layer into meshes
  • a lattice structure is filled with support material in the first internal support groove to form a first capacitor region disposed between the drain regions of two adjacent semiconductor layers in a direction perpendicular to the first substrate.
  • S23 Perform side etching on the memory cell isolation trench to form a second internal support trench in the first sacrificial layer of each composite wall, where the second internal support trench is located in the memory cell isolation trench.
  • the second inner support groove is filled with support material, and the support material in the second inner support groove forms a second inner support layer;
  • S25 Fill the memory cell isolation trench with memory cell isolation pillars and fill the bit line trench with isolation material.
  • step S20 may include:
  • S21 Etch memory cell isolation trenches, bit line trenches and trenches in the plurality of composite layers in a direction perpendicular to the first substrate;
  • S22 Fill the trench with a support material to form a capacitor region between the drain regions of two adjacent semiconductor layers along the extension direction of the word line and perpendicular to the first substrate.
  • a first internal support layer extending in the direction; performing side etching on the trench to form a plurality of spaced trenches perpendicular to the first substrate and forming a first sacrificial layer in each composite layer First internal support grooves, the spacing grooves space the plurality of composite layers into a plurality of composite walls perpendicular to the first substrate, the first internal support grooves space the first sacrificial layer into meshes
  • a lattice structure is filled with support material in the first internal support groove to form a first capacitor region disposed between the drain regions of two adjacent semiconductor layers in a direction perpendicular to the first substrate.
  • S24 Perform side etching on the bit line trench, and form a second internal support trench in the first sacrificial layer of each composite wall, where the second internal support trench is located on both sides of the bit line trench, filling the second inner support groove with support material, the support material in the second inner support groove forming a second inner support layer;
  • S25 Fill the memory cell isolation trench with memory cell isolation pillars and fill the bit line trench with isolation material.
  • step S20 may include:
  • S21 Etch memory cell isolation trenches, bit line trenches and trenches in the plurality of composite layers in a direction perpendicular to the first substrate;
  • S22 Fill the trench with a support material to form a capacitor region between the drain regions of two adjacent semiconductor layers along the extension direction of the word line and perpendicular to the first substrate.
  • a first internal support layer extending in the direction; performing side etching on the trench to form a plurality of spaced trenches perpendicular to the first substrate and forming a first sacrificial layer in each composite layer First internal support grooves, the spacing grooves space the plurality of composite layers into a plurality of composite walls perpendicular to the first substrate, the first internal support grooves space the first sacrificial layer into meshes
  • a lattice structure is filled with support material in the first internal support groove to form a first capacitor region disposed between the drain regions of two adjacent semiconductor layers in a direction perpendicular to the first substrate.
  • S23 Perform side etching on the memory cell isolation trench to form a second internal support trench in the first sacrificial layer of each composite wall, where the second internal support trench is located in the memory cell isolation trench.
  • the second inner support groove is filled with support material, and the support material in the second inner support groove forms a second inner support layer;
  • S25 filling the memory cell isolation trench with a memory cell isolation column and filling the bit line trench with an isolation material.
  • step S30 may include: removing the remaining first sacrificial layer.
  • the remaining semiconductor layer extends in a direction parallel to the first substrate and sequentially includes a source region, a channel region and a drain region.
  • the drain region includes a capacitor region.
  • step S50 may include:
  • S51 Remove the second sacrificial layer around the channel region of the semiconductor layer, and sequentially form a gate insulating layer and a gate electrode surrounding the channel region around the channel region of the semiconductor layer.
  • the semiconductor layer and The gate electrode constitutes a transistor; and, a semiconductor layer is provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that the gate electrode on the one semiconductor layer serves as a word lines; alternatively, a plurality of semiconductor layers are provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that gate electrodes on the plurality of semiconductor layers are connected together to form a word Wire;
  • S52 Set multiple word lines arranged in a direction perpendicular to the first substrate and located on different layers to different lengths, so that the word lines arranged in a direction perpendicular to the first substrate are located on different layers.
  • the multiple word lines of the layer appear in a ladder shape;
  • S53 Set an interlayer isolation layer between the gates of the transistors of the two adjacent memory cells in each memory cell column, so as to separate the transistors of the two adjacent memory cells in each memory cell column. gate isolating.
  • Step S50 may include:
  • S51 Remove the second sacrificial layer around the channel region of the semiconductor layer, and sequentially form a gate insulating layer and a gate electrode surrounding the channel region around the channel region of the semiconductor layer.
  • the semiconductor layer and The gate electrode constitutes a transistor; and, a semiconductor layer is provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that the gate electrode on the one semiconductor layer serves as a word lines; alternatively, multiple semiconductor layers are provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that gate electrodes on the multiple semiconductor layers are connected together to form a word Wire;
  • S52 Set multiple word lines located in different layers arranged in a direction perpendicular to the first substrate to different lengths, so that multiple word lines located in different layers arranged in a direction perpendicular to the first substrate The word lines show a staircase shape;
  • step S50 may include:
  • S51 Remove the second sacrificial layer around the channel region of the semiconductor layer, and sequentially form a gate insulating layer and a gate electrode surrounding the channel region around the channel region of the semiconductor layer.
  • the semiconductor layer and The gate electrode constitutes a transistor; and, a semiconductor layer is provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that the gate electrode on the one semiconductor layer serves as a word lines; alternatively, multiple semiconductor layers are provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that gate electrodes on the multiple semiconductor layers are connected together to form a word Wire;
  • S53 An interlayer isolation layer is provided between the gates of the transistors of the two adjacent memory cells in each memory cell column, thereby isolating the gates of the transistors of the two adjacent memory cells in each memory cell column. open;
  • step S50 may include:
  • S51 Remove the second sacrificial layer around the channel region of the semiconductor layer, and sequentially form a gate insulating layer and a gate electrode surrounding the channel region around the channel region of the semiconductor layer.
  • the semiconductor layer and The gate electrode constitutes a transistor; and, a semiconductor layer is provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that the gate electrode on the one semiconductor layer serves as a word lines; alternatively, multiple semiconductor layers are provided on a plane parallel to the first substrate and along an extension direction perpendicular to the semiconductor layer, so that gate electrodes on the multiple semiconductor layers are connected together to form a word Wire;
  • S52 Set multiple word lines located in different layers arranged in a direction perpendicular to the first substrate to different lengths, so that multiple word lines located in different layers arranged in a direction perpendicular to the first substrate The word lines show a staircase shape;
  • S53 An interlayer isolation layer is provided between the gates of the transistors of the two adjacent memory cells in each memory cell column, thereby isolating the gates of the transistors of the two adjacent memory cells in each memory cell column. open.
  • the manufacturing method may further include:
  • S80 Arrange peripheral circuits, metal contact layers with metal contact posts, and metal interconnection layers with metal lines in sequence on one side of the second substrate, connect one end of the metal line to the metal contact post through the metal contact posts.
  • the peripheral circuits are electrically connected to obtain a second chip;
  • S90 Stack the first chip and the second chip together, and electrically connect the circuit of the second chip to the circuit of the first chip.
  • step S80 may include:
  • S81 sequentially arranging a peripheral circuit, a metal contact layer with a metal contact column, and a metal interconnect layer with a metal wire on one side of the second substrate, wherein the peripheral circuit includes a first transistor and a second transistor.
  • step S90 may include: using X-Tracking technology to stack together the first substrate of the first chip and the metal interconnection layer of the second chip, and The connected metal lines are electrically connected to the bit lines, word lines or capacitors of the first chip.
  • Figure 6A is a schematic front cross-sectional structural view of an intermediate product obtained in an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application
  • Figure 6B is a schematic top view structural view of the intermediate product shown in Figure 6A
  • Figure 7A is an example of the present application
  • FIG. 7B is a schematic top view structural view of the intermediate product shown in FIG. 7A
  • FIG. 8A is a semiconductor device according to an exemplary embodiment of the present application.
  • Figure 8B is a schematic top structural view of the intermediate product shown in Figure 8A
  • Figure 9A is an intermediate step of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.
  • FIGS. 6A to 11B A schematic front cross-sectional structural view of the obtained intermediate product;
  • Figure 9B is a schematic top structural view of the intermediate product shown in Figure 9A;
  • Figure 10A is a main schematic view of the intermediate product obtained in the intermediate steps of the manufacturing method of the semiconductor device according to the exemplary embodiment of the present application.
  • Figure 10B is a schematic top view of the structure of the intermediate product shown in Figure 10A;
  • Figure 11A is a schematic cross-sectional view of the intermediate product obtained in the intermediate steps of the manufacturing method of a semiconductor device according to an exemplary embodiment of the present application;
  • Figure 11B is a schematic top structural view of the intermediate product shown in FIG. 11A.
  • the manufacturing method of the semiconductor device may include:
  • S22 Fill the trench 4 with support material to form a first internal support layer 501 extending in a direction perpendicular to the first substrate 100 (as shown in FIG. 8B ); perform side etching on the trench 4 to form multiple layers.
  • a spacing groove 6 perpendicular to the first substrate 100 and a first internal support groove 501' is formed in the first sacrificial layer 901 of each composite layer. The spacing groove 6 separates the plurality of composite layers into a plurality of composite layers perpendicular to the first sacrificial layer 901.
  • the first internal support grooves 501' space the first sacrificial layer 901 into a grid structure, and the first internal support grooves 501' are filled with support material to form a structure arranged along a direction perpendicular to the first substrate 100.
  • the first inner support layer 501 between two adjacent semiconductor layers 11 in the direction (as shown in FIG. 8A);
  • S23 Perform side etching on the memory cell isolation trench 3', so that a second internal support trench 502' is formed in the first sacrificial layer 901 of each composite wall, where the second internal support trench 502' is located in the memory cell isolation On both sides of the groove 3', support material is filled in the second inner support groove 502', and the support material in the second inner support groove 502' forms the second inner support layer 502;
  • S24 Perform side etching on the bit line trench 300', and form a second internal support trench 502' in the first sacrificial layer 901 of each composite wall.
  • the second internal support trench 502' here is located in the bit line trench 300'.
  • the second inner support groove 502' is filled with support material, and the support material in the second inner support groove 502' forms the second inner support layer 502;
  • S30 Remove the remaining first sacrificial layer 901, and the remaining semiconductor layer 11 extends in a direction parallel to the first substrate 100 into a strip-shaped structure.
  • the strip-shaped structure has side walls and two ends, and is perpendicular to the first substrate 100.
  • the sidewall in the direction of the substrate 1000 includes the source region 111, the channel region 112 and the drain region 113 in sequence.
  • the drain region 113 includes the capacitor region, resulting in the intermediate product as shown in Figure 9A and Figure 9B;
  • step S40 Form a second sacrificial layer 902 on the first substrate 100, so that the second sacrificial layer 902 covers the surface of the intermediate product obtained in step S30 (covers the semiconductor layer 11), and obtains the intermediate product as shown in Figure 10A and Figure 10B ;
  • S51 Remove the second sacrificial layer 902 on the sidewalls of the channel region 112 of the semiconductor layer 11, and sequentially form a gate insulating layer surrounding the channel region 112 and the gate electrode 12 on the sidewalls of the channel region 112 of the semiconductor layer 11.
  • the semiconductor layer 11 and the gate electrode 12 constitute the transistor 10; and, one semiconductor layer 11 is provided on a plane parallel to the first substrate 100 and along an extension direction perpendicular to the semiconductor layer 11, so that The gate 12 serves as the word line 400; alternatively, a plurality of semiconductor layers 11 are provided on a plane parallel to the first substrate 100 and along an extension direction perpendicular to the semiconductor layer 11, so that the gates on the plurality of semiconductor layers 11 poles 12 are connected together to form word line 400;
  • S52 Set multiple word lines 400 located in different layers arranged in a direction perpendicular to the first substrate 100 to different lengths, so that multiple word lines 400 located in different layers arranged in a direction perpendicular to the first substrate 100 Line 400 presents a staircase shape;
  • S53 Set the interlayer isolation layer 2 between the gate electrodes 12 of the transistors 10 of the two adjacent memory cells in each memory cell column, so as to separate the transistors 10 of the two adjacent memory cells in each memory cell column.
  • the gate 12 is isolated, and the intermediate product shown in Figure 11A and Figure 11B is obtained;
  • S70 Remove the isolation material 5 in the bit line trench 300', fill the bit line trench 300' with bit line material to form a bit line, and connect the bit line and the source regions of the plurality of semiconductor layers 11 in contact with the bit line. 111 connection, so that the source regions 111 of the plurality of semiconductor layers 11 share a bit line to obtain the first chip 1000 and the intermediate product as shown in Figure 1A and Figure 1B;
  • a peripheral circuit, a metal contact layer with metal contact pillars, and a metal interconnection layer with metal lines are sequentially provided on one side of the second substrate.
  • the peripheral circuit includes the first transistor 10 and the second transistor 10.
  • S90 Use X-Tracking technology to stack together the first substrate 100 of the first chip 1000 and the metal interconnection layer of the second chip, and connect the metal lines of the metal interconnection layer to the bit lines of the first chip 1000.
  • the word lines 400 or capacitors are electrically connected to obtain an intermediate product as shown in Figures 2A and 2B.
  • the steps S10 to S70 of forming the first chip and the step S80 of forming the second chip can be performed at the same time; or, steps S10 to S60 are performed first, and then step S80 is performed; or, step S80 is performed first, and then step S80 is performed. Proceed to steps S10 to S60.
  • the material of the first sacrificial layer may be a material with a greater etching selectivity than the material of the semiconductor layer.
  • the material of the first sacrificial layer may be a material with a greater etching selectivity than the material of the semiconductor layer.
  • the etching selectivity ratio between the materials can be ⁇ 50:1.
  • the material of the semiconductor layer can be single crystal silicon, and the material of the first sacrificial layer can be selected from other materials with similar properties such as SiGe. any one or more.
  • the thickness of the first sacrificial layer may be 30 nm to 50 nm, for example, it may be 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.
  • the material of the second sacrificial layer may be a material with a greater etching selectivity than the material of the semiconductor layer.
  • the material of the second sacrificial layer may be a material with a greater etching selectivity than the material of the semiconductor layer.
  • the etching selectivity ratio between materials can be ⁇ 50:1.
  • the material of the semiconductor layer may be single crystal silicon, and the material of the second sacrificial layer may be any one or more of SiO 2 and other materials with similar properties; the difference between SiO 2 and single crystal silicon The etching selectivity is relatively high, and the SiO 2 etching process is mature and the required etching time is short.
  • a super lattice thin film stack composed of a first sacrificial layer and a semiconductor layer can be grown on the first side of the first substrate through epitaxial equipment to obtain multiple layers.
  • the same layer of patterned photomask can be used to perform patterned etching through light exposure to form storage unit isolation grooves, bit line grooves and trenches.
  • the trench, the memory cell isolation trench or the bit line trench may be side etched by wet etching.
  • supporting materials can be filled in the first internal supporting layer groove, the second internal supporting groove and the groove by an ALD process.
  • SiN can be filled in the first internal supporting layer groove, the second internal supporting groove and the groove by an ALD process.
  • the memory cell isolation pillars can be filled in the memory cell isolation trenches and the bit line trenches can be filled with isolation materials through SOD, HDP or HARP processes.
  • SOD, HDP or HARP processes can be used.
  • the HARP process forms a silicon oxide film in the memory cell isolation trench and the bit line trench.
  • the first sacrificial layer in step S30, can be etched away while retaining the semiconductor layer by selecting an ultra-high first sacrificial layer/semiconductor layer etching ratio.
  • the etching method can be dry. Method etching or wet etching.
  • the second sacrificial layer can be formed through SOD, HDP or HARP process in step S40.
  • the SOD silicon oxide film, HDP silicon oxide film and HARP silicon oxide film can be formed through SOD, HDP or HARP process. Any one or more of them, as the second sacrificial layer.
  • the second sacrificial layer in step S50, can be etched away while retaining the semiconductor layer by using an etching method and selecting an ultra-high second sacrificial layer/semiconductor layer etching ratio.
  • the etching method can be dry etching or wet etching.
  • a staircase word line (staircase WL) can be obtained by trim etch.
  • the interlayer isolation layer may be provided by an ALD or chemical vapor deposition (CVD) process.
  • SiO 2 may be filled by an ALD or CVD process to form the interlayer isolation layer.
  • the peripheral circuit may be formed through a traditional CMOS process, and then a metal contact layer and a metal interconnection layer may be formed on the peripheral circuit.
  • the metal contact layer may be formed of a metal contact post and an insulating medium. A whole layer of insulating dielectric may be provided first, and then through holes are opened in the insulating medium and filled with metal to form the metal contact post.
  • the metal interconnection layer may be formed of a metal line and an insulating medium. A whole layer of insulating medium may be provided first, and then through holes are opened in the insulating medium and filled with metal to form the metal line.
  • X-Tracking technology can be used in step S90 to realize the combination and precise electrical connection of the first chip and the second chip.
  • it can include combining the first chip and the second chip together. Select as needed. Electrically connect the metal line to the bit line, word line or capacitor. For example, if you want the metal line to be electrically connected to the bit line, align the metal line to the bit line, and open a connection between the metal line and the bit line in the first substrate.
  • the through hole is filled with conductive metal to achieve precise electrical connection between the metal line and the bit line.
  • An embodiment of the present application also provides an electronic device, including the semiconductor device provided in the above embodiment of the present application.
  • the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

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Abstract

一种半导体器件及其制造方法、电子设备，半导体器件包括第一芯片(1000)，第一芯片(1000)包括设置在第一衬底(100)上的多个存储单元列(200)，每个存储单元列(200)均垂直于第一衬底(100)并且由堆叠设置的多个存储单元(1)形成，存储单元(1)包括晶体管(10)和电容器(20)，晶体管(10)包括半导体层(11)和栅极(12)，半导体层(11)沿平行于第一衬底(100)的方向延伸并且依次包括源极区(111)、沟道区(112)和漏极区(113)，漏极区(113)包括电容区；栅极(12)环绕在沟道区(112)的侧壁；电容器(20)设置在漏极区(113)的电容区的侧壁上；第一内部支撑层501，设置在沿垂直于第一衬底(100)的方向上相邻的两个半导体层(11)的漏极区(113)的电容区之间，电容器(20)为网格式电容器(20)。

Description

半导体器件及其制造方法、电子设备
本申请要求于2022年09月22日提交中国专利局、申请号为2022111604993、发明名称为“半导体器件及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请涉及但不限于半导体器件领域，尤指一种半导体器件及其制造方法、电子设备。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)是一种常见的系统内存，广泛应用在个人电脑、笔记本和消费电子产品中，每年的产值占整个半导体行业的30％左右。现在世界前三大DRAM公司正在进入1a技术节点，其栅极长度已经到达15nm(和逻辑的7nm接近)，难以再进一步微缩。
随着DRAM技术朝向更高密度和高容量发展，半导体结构的微缩遇到了瓶颈，很难再进一步微缩。而且电容器的数量提高、尺寸下降，导致电容器的制造需要更长的工艺时间以及更复杂的工艺流程。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制本申请的保护范围。
本申请实施例提供了一种半导体器件，包括第一芯片，所述第一芯片包括：
第一衬底；
设置在所述第一衬底上的多个存储单元列，每个所述存储单元列均垂直于所述第一衬底并且由堆叠设置在所述第一衬底一侧的多个存储单元形成；
每个所述存储单元均包括晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿平行于所述第一衬底的方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在平行于所述第一衬底的方向上的侧壁依次包括源极区、沟道区和漏极区，所述漏极区包括电容区；所述栅极环绕在所述沟道区的侧壁，并且所述栅极与所述沟道区之间设置有栅极绝缘层；
所述电容器设置在所述漏极区的电容区的侧壁上；
第一内部支撑层，所述第一内部支撑层设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间，所述第一内部支撑层配置为对所述电容器和相邻的两个半导体层提供支撑，所述电容器被所述第一内部支撑层间隔为网格式电容器。
在本申请实施例中，所述第一芯片还包括：多条字线，每条所述字线均在平行于所述第一衬底的平面上延伸并且垂直于所述半导体层的延伸方向，其中，在所述字线的延伸方向上设置有一个存储单元列，每条所述字线由该一个存储单元列的一个存储单元的晶体管的栅极形成；或者，在所述字线的延伸方向上设置有多个存储单元列，每条所述字线由该多个存储单元列的沿所述字线的延伸方向排列的多个存储单元的晶体管的栅极连接在一起形成。在本申请实施例中，所述第一内部支撑层还可以设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸。
在本申请实施例中，所述第一芯片还包括：多条位线，每条所述位线均沿垂直于所述第一衬底的方向延伸，在与所述半导体层的延伸方向平行的方向上，相邻的两个存储单元列的多个存储单元的晶体管的源极区均与一条共用的位线连接。
在本申请实施例中，所述电容器可以环绕在所述漏极区的电容区的侧壁上。在本申请实施例中，所述电容器可以包括第一电极板、第二电极板以及设置在所述第一电极板和所述第二电极板之间的介电质层，所述第一电极板、所述介电质层和所述第二电极板依次环绕在所述漏极区的电容区的侧壁上。在本申请实施例中，所述半导体器件还可以包括第二芯片，所述第二芯片和所述第一芯片层叠结合在一起并且所述第二芯片和所述存储单元列分别位于 所述第一衬底的两侧，所述第二芯片的电路与所述第一芯片的电路电连接；
所述第二芯片包括依次设置在第二衬底上的外围电路、金属接触层和金属互连层，所述金属接触层设置在所述外围电路远离所述第二衬底的一侧，所述金属互连层设置在所述金属接触层远离所述第二衬底的一侧并且位于所述第一衬底远离所述存储单元列的一侧，所述金属接触层中设置有金属接触柱，所述金属互连层中设置有金属线，所述金属线的一端与所述第一芯片的位线、字线或电容器电连接，所述金属线的另一端通过所述金属接触柱与所述外围电路电连接。
在本申请实施例中，沿垂直于所述第一衬底的方向间隔排列的位于不同层的多条字线可以呈阶梯状。
在本申请实施例中，所述半导体层的材料可以选自第IVA族元素形成的半导体材料中的任意一种或多种，所述字线的材料选自第IVA族元素形成的导体材料中的任意一种或多种。
在本申请实施例中，所述半导体层的材料可以为单晶硅；所述字线的材料可以选自多晶硅和多晶硅锗中的任意一种或多种。
在本申请实施例中，所述存储单元列还可以包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，所述层间隔离层配置为将相邻的两个存储单元的晶体管的栅极隔离开。
在本申请实施例中，所述半导体器件还可以包括一个或多个沿垂直于所述第一衬底的方向延伸的存储单元隔离柱，在所述半导体层的延伸方向上每间隔两个存储单元列设置有一个所述存储单元隔离柱。
在本申请实施例中，所述半导体器件还可以包括第二内部支撑层，所述第二内部支撑层设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层之间并且位于非电容区，所述第二内部支撑层配置为对所述半导体层提供支撑。
在本申请实施例中，所述第一电极板可以为内电极板，所述第二电极板可以为外电极板；所述漏极区可以与所述第一电极板连接。本申请实施例还提供一种半导体器件的制造方法，包括：
在第一衬底的一侧按照第一牺牲层和半导体层的顺序沿垂直于所述第一衬底的方向堆叠形成多个由所述第一牺牲层和所述半导体层组成的复合层；
在多个所述复合层中沿垂直于所述第一衬底的方向刻蚀出沟槽，并对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料形成第一内部支撑层；
去除剩余的第一牺牲层，剩余的半导体层沿平行于所述第一衬底的方向延伸并且依次包括源极区、沟道区和漏极区，所述漏极区包括电容区；
在所述第一衬底上形成第二牺牲层，使所述第二牺牲层覆盖所述半导体层；
去除所述半导体层的沟道区侧壁上的第二牺牲层，在所述半导体层的沟道区的侧壁上依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层和所述栅极组成晶体管；
去除所述半导体层的漏极区的电容区侧壁上的第二牺牲层，在所述半导体层的漏极区的电容区的侧壁上依次形成电容器，得到第一芯片。
在本申请实施例中，所述半导体器件的制造方法还可以包括：形成多条在平行于所述第一衬底的平面上延伸并且垂直于所述半导体层的延伸方向的字线；
其中，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线。
在本申请实施例中，所述半导体器件的制造方法还可以包括：形成多条沿垂直于所述第一衬底的方向延伸的位线；
其中，形成所述位线包括：
在多个所述复合层中刻蚀所述沟槽时，在多个所述复合层中沿垂直于所 述第一衬底的方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料；
在形成所述电容器之后，去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料，形成位线，将所述位线和与该位线相接触的多个半导体层的所述源极区连接，使得该多个半导体层的所述源极区共用一条位线。
在本申请实施例中，所述半导体器件的制造方法还可以包括：
在第二衬底的一侧依次设置外围电路、带有金属接触柱的金属接触层、和带有金属线的金属互连层，将所述金属线的一端通过所述金属接触柱与所述外围电路电连接，得到第二芯片；
将所述第一芯片和所述第二芯片层叠结合在一起，并将所述第二芯片的电路与所述第一芯片的电路进行电连接。
在本申请实施例中，对所述沟槽进行侧边刻蚀，在每个所述复合层的第一牺牲层中形成第一内部支撑槽，在所述第一内部支撑槽中填充支撑材料形成第一内部支撑层，可以包括：
对所述沟槽进行侧边刻蚀，在每个所述复合层的第一牺牲层中形成第一内部支撑槽，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层；或者，
在所述沟槽中填充支撑材料，形成设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸的第一内部支撑层；对所述沟槽进行侧边刻蚀，在每个所述复合层的第一牺牲层中形成第一内部支撑槽，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层。
在本申请实施例中，所述在所述半导体层的漏极区的电容区的侧壁上依次形成电容器，可以包括：在所述半导体层的漏极区的电容区的侧壁上依次形成环绕所述电容区的侧壁的第一电极板、介电质层和第二电极板，所述第一电极板、所述介电质层和所述第二电极板构成所述电容器。
本申请实施例还提供一种电子设备，包括如上本申请实施例提供的所述 半导体器件。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得更加清楚，或者通过实施本申请而了解。本申请的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1A为本申请示例性实施例的一种半导体器件的主视剖面结构示意图；
图1B为图1A所示的半导体器件的俯视剖面结构示意图；
图1C为图1A所示的半导体器件的晶体管的放大图；
图1D为图1A所示的半导体器件的电容器的放大图；
图2A为本申请示例性实施例的另一种半导体器件的主视剖面结构示意图；
图2B为图2A所示的导体器件的俯视结构示意图图；
图3为本申请示例性实施例的半导体器件的沿垂直于第一衬底的方向间隔排列的多条字线在侧视方向上的分布状态图；
图4A为本申请示例性实施例的半导体器件的第二芯片的主视剖面结构示意图；
图4B为图3A所示的半导体器件的第二芯片的俯视结构示意图；
图5为本申请示例性实施例的半导体器件的制造方法的工艺流程图；
图6A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图6B为图6A所示的中间品的俯视结构示意图；
图7A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图7B为图7A所示的中间品的俯视结构示意图；
图8A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图8B为图8A所示的中间品的俯视结构示意图；
图9A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图9B为图9A所示的中间品的俯视结构示意图；
图10A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图10B为图10A所示的中间品的俯视结构示意图；
图11A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；
图11B为图11A所示的中间品的俯视结构示意图。
附图中的标记符号的含义为：
1000-第一芯片；2000-第二芯片；3000-第二衬底；100-第一衬底；200-存储单元列；300-位线；300’-位线槽；400-字线；501-第一内部支撑层；501’-第一内部支撑槽；502-第二内部支撑层；502’-第二内部支撑槽；600-外围电路；601-第一晶体管；6011-第一源极；6012-第一漏极；6013-第一沟道；6014-第一栅极；602-第二晶体管；6021-第二源极；6022-第二漏极；6023-第二沟道；6024-第二栅极；603-第一型阱；604-第二型阱；700-金属接触层；701-金属接触柱；800-金属互连层；801-金属线；901-第一牺牲层；902-第二牺牲层；1-存储单元；10-晶体管；11-半导体层111-源极区；112-沟道区；113-漏极区；12-栅极；20-电容器；21-第一电极板；22-第二电极板；23-介电质层；2-层间隔离层；3-存储单元隔离柱；3’-存储单元隔离槽；4-沟槽；5-隔离材料；6-间隔槽。
详述
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图 对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本文中的实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是实现方式和内容可以在不脱离本申请的宗旨及其范围的条件下被变换为各种各样的形式。因此，本申请不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本申请中的附图比例可以作为实际工艺中的参考，但不限于此。例如：半导体层的宽长比、各个膜层的厚度和间距，可以根据实际需要进行调整。本申请中所描述的附图仅是结构示意图，本申请的一个方式不局限于附图所示的形状或数值等。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“垂直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“设置”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本申请的描述中，“第一”、“第二”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“介电质层”换成为“介电质膜”。
本申请实施例提供了一种半导体器件，所述半导体器件包括第一芯片， 所述第一芯片包括：
第一衬底；
设置在所述第一衬底上的多个存储单元列，每个所述存储单元列均垂直于所述第一衬底并且由堆叠设置在所述第一衬底一侧的多个存储单元形成；
每个所述存储单元均包括晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿平行于所述第一衬底的方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在平行于所述第一衬底的方向上的侧壁依次包括源极区、沟道区和漏极区，所述漏极区包括电容区；所述栅极环绕在所述沟道区的侧壁，并且所述栅极与所述沟道区之间设置有栅极绝缘层；所述电容器设置在所述漏极区的电容区的侧壁上；
第一内部支撑层，所述第一内部支撑层设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间，所述第一内部支撑层配置为对所述电容器和相邻的两个半导体层提供支撑，所述电容器被所述第一内部支撑层间隔为网格式电容器。
在本申请实施例中，所述第一芯片还可以包括：多条字线，每条所述字线均在平行于所述第一衬底的平面上延伸并且垂直于所述半导体层的延伸方向，其中，在所述字线的延伸方向上设置有一个存储单元列，每条所述字线由该一个存储单元列的一个存储单元的晶体管的栅极形成；或者，在所述字线的延伸方向上设置有多个存储单元列，每条所述字线由该多个存储单元列的沿所述字线的延伸方向排列的多个存储单元的晶体管的栅极连接在一起形成。
在本申请实施例中，所述第一内部支撑层还可以设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸。
在本申请实施例中，所述第一芯片还可以包括：多条位线，每条所述位线均沿垂直于所述第一衬底的方向延伸，在与所述半导体层的延伸方向平行的方向上，相邻的两个存储单元列的多个存储单元的晶体管的源极区均与一条共用的位线连接。
在本申请实施例中，所述电容器可以环绕在所述漏极区的电容区的侧壁上。本申请实施例提供的半导体器件可以应用于DRAM领域，例如，可以应用于通过超晶格结构形成的具有3D存储单元的DRAM。
例如，衬底上的多层超晶格可以用于形成多层存储单元，每层存储单元可以是阵列分布的存储单元，各层中在二维平面中相同位置的存储单元构成一个垂直方向的一列存储单元，简称存储单元列。
图1A为本申请示例性实施例的一种半导体器件的主视剖面结构示意图；图1B为图1A所示的半导体器件的俯视剖面结构示意图；图1C为图1A所示的半导体器件的晶体管的放大图；图1D为图1A所示的半导体器件的电容器的放大图。如图1A至图1D所示，所述半导体器件可以包括：第一芯片1000，所述第一芯片1000包括：第一衬底100、多个存储单元列200、多条位线300(Bit Line,BL)、多条字线400(Word Line,WL)和第一内部支撑层501。
其中，每个存储单元列200均垂直于第一衬底100并且由堆叠设置在第一衬底100一侧的多个存储单元1形成。
每个存储单元1均包括晶体管10和电容器20，晶体管10包括半导体层11和栅极12，半导体层11沿平行于第一衬底100的方向延伸为条状结构，所述条状结构具有侧壁和两端，所述条状结构的横截面可以为矩形、圆形、椭圆形等，并且在平行于所述第一衬底的方向上的侧壁依次包括源极区111、沟道区112和漏极区113，漏极区113包括电容区；栅极12环绕在沟道区112的侧壁，并且栅极12与沟道区112之间设置有栅极绝缘层(图中未示)。
所述电容器20设置在所述漏极区113的电容区的侧壁上，即所述电容器20设置在相邻两个半导体层之间。例如，可以如图1A所示，所述电容器20环绕在所述漏极区113的电容区的侧壁上，即所述电容器20套设在所述漏极区113的电容区四周的侧壁上。在其他实施例中，所述电容器20可以设置在所述漏极区113的电容区相对两侧的侧壁上。
在本申请实施例中，如图1D所示，电容器20包括第一电极板21、第二电极板22以及设置在第一电极板21和第二电极板22之间的介电质层23，第一电极板21、介电质层23和第二电极板22依次环绕在漏极区113的电容 区的侧壁上。
每条位线300均沿垂直于第一衬底100的方向延伸，在与半导体层11的延伸方向平行的方向上，相邻的两个存储单元列200的多个存储单元1的晶体管10的源极区111均与一条共用的位线300连接。例如，沿半导体层的延伸方向上相邻的两个存储单元1呈镜像分布，所述相邻的两个存储单元1的晶体管10的源极区111与一条共用的位线300连接。
沿半导体层的延伸方向上每相邻两个存储单元整体作为一个重复单元，沿半导体层的延伸方向上有2n个存储单元时，有n个重复单元，每个重复单元包含两个结构上镜像对称的存储单元；一个重复单元中，两个晶体管相邻设置，位于一个半导体层上的电容器位于两端，两个相邻设置的晶体管之间设置有沿垂直衬底方向分布的位线300，两个存储单元中的晶体管和电容器关于所述位线300镜像对称分布。
每条字线400均在平行于第一衬底100的平面上延伸并且垂直于半导体层11的延伸方向，其中，在字线400的延伸方向上设置有一个存储单元列200，每条字线400由该一个存储单元列200的各个层的一个存储单元1的晶体管10的栅极12形成；或者，在字线400的延伸方向上设置有多个存储单元列200，每条字线400由该多个存储单元列200的沿字线400的延伸方向排列的多个存储单元1的位于同一层的晶体管10的栅极12连接在一起形成。
第一内部支撑层501设置在沿垂直于第一衬底100的方向上相邻的两个半导体层11的漏极区113的电容区之间，第一内部支撑层501配置为对电容器20和相邻的两个半导体层11提供支撑，电容器20被第一内部支撑层501间隔为网格式(Mesh)电容器。
在图1A中，两个存储单元列200共用一条位线300，图1A、图1B所示的半导体器件中共有3条位线300；图1A、图1B所示的半导体器件为三层超晶格形成的三层存储单元，每层存储单元对应有2条字线400，图1A、图1B所示的半导体器件中共有6条字线400。
在本申请的描述中，每个存储单元列均由沿垂直于第一衬底堆叠设置在第一衬底一侧的多个存储单元形成；本申请将属于同一层的一个或多个存储单元作为一个组，该组存储单元在垂直于第一衬底的方向叠层设置，不同叠 层的存储单元组构成沿着垂直于第一衬底方向延伸的列。所述的多个组构成一个阵列，也就是说每个层的存储单元组构成一个阵列，或多个叠层的存储单元组形成的多列构成一个阵列，例如，不同的所述存储单元列200在所述第一衬底100上沿所述半导体层的延伸方向和所述字线的延伸方向排列形成阵列。
本申请实施例的半导体器件，通过采用横向半导体层(即沿平行于所述第一衬底的方向延伸的半导体层)和横向电容器(即将电容器设置在晶体管的半导体层之间，而不是设置在晶体管左右两侧)，使得晶体管和电容器可以形成立体堆叠结构，并且由晶体管和电容器形成的存储单元可以沿垂直于第一衬底的方向堆叠在一起，增加了半导体器件的存储密度；另外，第一内部支撑层的设计使得电容器具有网格式电容结构，可以起到支撑较长的横向电容器的作用，避免较长的横向电容器在选择性刻蚀中倒塌。
示例性地，在与所述半导体层的延伸方向平行的方向上，相邻的两个存储单元列的多个存储单元的晶体管的源极可以共用一条位线，可以减小半导体器件的尺寸，进一步增加半导体器件的存储密度，从而减少单位Gb的制作成本，为DRAM微缩瓶颈下，提供了一种新的技术研发方向。
在本申请实施例中，如图1B所示，第一内部支撑层501还可以设置在沿字线400的延伸方向上相邻的两个半导体层11的漏极区的电容区之间并且沿垂直于第一衬底100的方向延伸。
在本申请实施例中，一个存储单元列可以由2个至100个沿垂直于所述第一衬底的方向堆叠设置的存储单元形成，例如，可以由2个、3个、4个、5个、10个、13个、15个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个存储单元形成。
在本申请实施例中，所述多个存储单元列在所述第一衬底上沿所述半导体层的延伸方向和所述字线的延伸方向排列形成阵列；这里，可以理解为每个层的存储单元组构成一个阵列，或多个叠层的存储单元组形成的多列构成一个阵列。
在本申请实施例中，在沿所述半导体层的延伸方向上可以设置有2个至1000个存储单元列，例如，可以设置有2个、4个、6个、8个、10个、12 个、14个、16个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个、200个、300个、400个、500个、600个、700个、800个、900个、1000个存储单元列；在沿所述字线的延伸方向上可以设置有1个至100个存储单元列，例如，可以设置有1个、2个、3个、4个、5个、12个、14个、16个、18个、20个、30个、40个、50个、60个、70个、80个、90个、100个存储单元列。
在本申请实施例中，所述网格式(Mesh)电容器的结构可以参考1z技术节点的网格电容器的结构。
在本申请实施例中，可以根据电容器的长度设置第一内部支撑层的数量，使得电容器具有网格式结构。例如，可以每间隔200nm至300nm设置一个第一内部支撑层；当前1z技术节点的电容器的长度大约为1000nm，其中可以设置两个第一内部支撑层。
图2A为本申请示例性实施例的另一种半导体器件的主视剖面结构示意图；图2B为图2A所示的半导体器件的俯视结构示意图。如图2A和图2B所示，在本申请示例性实施例中，所述半导体器件还可以包括第二芯片2000，第二芯片2000和第一芯片1000层叠结合在一起并且第二芯片2000和存储单元列200分别位于第一衬底100的两侧，第二芯片2000的电路与第一芯片1000的电路电连接；
第二芯片2000包括依次设置在第二衬底3000上的外围电路600、金属接触层700和金属互连层800，金属接触层700设置在外围电路600远离第二衬底3000的一侧，金属互连层800设置在金属接触层700远离第二衬底3000的一侧并且位于第一衬底100远离存储单元列200的一侧，金属接触层700包括金属接触柱701和绝缘介质，金属互连层800包括金属线801和绝缘介质，金属线801的一端与第一芯片1000的位线300、字线400或电容器20的第二电极板(可以根据具体电路而定)电连接，金属线801的另一端通过金属接触柱701与外围电路600电连接。
本申请实施例的半导体器件结构，将存储单元和外围电路分别设置在不同芯片的衬底上，而且采用CuA(CMOS under Array)结构将外围电路设置在存储单元列下方，因此外围电路不会占用存储单元所在的第一芯片的第一 衬底的面积，可以在整片第一衬底上都设置存储单元，使得能够在有限的第一衬底面积上设置更多的存储单元，提高半导体存储器的存储密度。
在本申请实施例中，所述第一衬底可以为半导体衬底，例如，可以为单晶硅衬底，还可以为绝缘体上半导体(Semiconductor on Insulator,SOI)衬底，例如，蓝宝石上硅(Silicon On Sapphire,SOS)衬底、玻璃上硅(Silicon On Glass,SOG)衬底，基底半导体基础上的硅的外延层或其它半导体或光电材料，例如硅-锗(Si 1-xGe x，其中x可以是例如0.2与0.8之间的摩尔分数)、锗(Ge)、砷化镓(GaAs)、氮化镓(GaN)或磷化铟(InP)。所述第一衬底可经掺杂或可未经掺杂；所述第二衬底可以为经掺杂或可未经掺杂的单晶硅衬底。
在本申请实施例中，所述位线的材料可以选自钨、钼、钴等具有相似性质的其他金属材料中的任意一种或多种。
图3为本申请示例性实施例的半导体器件的沿垂直于第一衬底的方向间隔排列的多条字线在侧视方向上的分布状态图。如图3所示，在本申请实施例中，沿垂直于所述第一衬底100的方向间隔排列的位于不同层的多条字线400的长度可以不同，使得沿垂直于所述第一衬底100的方向排列的位于不同层的多条字线400可以呈现为阶梯状。
在本申请实施例中，所述半导体层的材料可以选自第IVA族元素形成的半导体材料中的任意一种或多种，例如，所述半导体层的材料可以为单晶硅。
在本申请实施例中，所述字线的材料可以为与所述半导体层兼容的材料，例如，所述字线的材料可以选自第IVA族元素形成的导体材料中的任意一种或多种，再例如，所述字线的材料可以选自多晶硅、多晶硅锗等中的任意一种或多种。第IVA族元素形成的半导体材料和第IVA族元素形成的导体材料都由第IVA族元素形成，它们之间可以更好的兼容。
在本申请实施例中，所述半导体层在垂直于第一衬底的方向上的高度可以根据实际的电性需求来设置，例如，可以为10nm至50nm。
在本申请实施例中，所述第一电极板可以为内电极板，所述第二电极板可以为外电极板。如图1A和图2A所示，漏极区113可以与第一电极板21(即内电极板)相连接。如图1B和图2B所示，沿与所述字线的延伸方向平行的方向排列的多个电容器20的第二电极板22可以连接在一起，但其第一 电极板21是分开的。
在本申请实施例中，如图1A和图2A所示，一个晶体管10可以对应一个电容器20，即存储单元1可以为1T1C结构。
在本申请实施例中，在垂直于第一衬底的方向上相邻的两个电容器可以共用一个外电极板。
在本申请实施例中，所述第一电极板和所述第二电极板的材料可以各自独立地选自氮化钛(例如，TiN)、铝钛基合金(例如，TiAl)、氮化钽(例如，TaN)等具有相似性质的其他金属材料的任意一种或多种。所述第一电极板的厚度可以为5nm至15nm，所述第二电极板的厚度可以为5nm至15nm。
在本申请实施例中，所述介电质层的材料可以为高介电常数(K)材料，例如，可以选自氧化铪(例如，HfO 2)、氧化铝(例如，Al 2O 3)、氧化锆(例如，ZrO)和钛酸锶(例如，SrTiO 3,STO)中的任意一种或多种。所述介电质层的厚度可以为5nm至15nm。
在本申请实施例中，如图1A和图2A所示，存储单元列200还可以包括层间隔离层2，层间隔离层2设置在存储单元列200中相邻的两个存储单元1的晶体管10的栅极12之间，将相邻的两个存储单元1的晶体管10的栅极12隔离开。
在本申请实施例中，所述层间隔离层的材料可以为氧化硅，例如，可以为SiO 2。
在本申请实施例中，如图1A和图2A所示，所述半导体器件还可以包括一个或多个沿垂直于第一衬底的方向延伸的存储单元隔离柱3。例如，在所述半导体层的延伸方向上每间隔两个存储单元列200可以设置有一个存储单元隔离柱3。
在本申请实施例中，所述存储单元隔离柱的材料可以为氧化硅，例如，可以选自旋转涂敷(Spin-On Deposition,SOD)氧化硅薄膜、高密度等离子体(High Density Plasma,HDP)氧化硅薄膜和高深宽比工艺(High Aspect Ratio Process，HARP)氧化硅薄膜中的任意一种或多种。
在本申请实施例中，所述栅极绝缘层的材料可以选自氧化硅(例如，SiO 2)、 氧化铪(例如，HfO 2)、氧化锆(例如，ZrO)和氧化铝(例如，Al 2O 3)中的任意一种或多种。
在本申请实施例中，所述栅极绝缘层可以为单层或多层，例如，可以包括由氧化硅和氧化铪形成的两层结构，其中，氧化硅层与沟道区接触，氧化铪层与栅极接触。
在本申请实施例中，所述栅极绝缘层的厚度可以根据实际的电性需求来设置，例如，可以为2nm至5nm。
在本申请实施例中，如图1A和图2A所示，所述半导体器件还可以包括第二内部支撑层502，第二内部支撑层502设置在沿垂直于第一衬底的方向上相邻的两个半导体层11之间并且位于非电容区，第二内部支撑层502第二内部支撑层502配置为对半导体层11提供支撑。
在本申请实施例中，如图1A和图2A所示，第二内部支撑层502可以位于位线300两侧，或者可以位于位线300两侧和存储单元隔离柱3两侧。当位线300两侧和存储单元隔离柱3两侧均设置有第二内部支撑层502时，可以对半导体层11提供更牢固的支撑。
在本申请实施例中，所述第一内部支撑层和所述第二内部支撑层的材料可以为具有支撑作用的薄膜材料，例如，可以为氮化硅(例如，SiN)。
在本申请示例性实施例中，如图1A和图2A所示，所述半导体器件还可以包括第二牺牲层902，第二牺牲层902设置在第一芯片1000的空白空间中并且覆盖半导体层11。
在本申请实施例中，所述第二牺牲层的材料可以为介电质材料，例如，可以为氧化硅(例如，SiO 2)等具有相似性质的其他材料中的任意一种或多种。
在本申请实施例中，所述第二芯片可以采用常用的外围电路的芯片结构，例如，所述外围电路可以为CMOS晶体管。
图4A为本申请示例性实施例的半导体器件的第二芯片的主视剖面结构示意图；图4B为图3A所示的半导体器件的第二芯片的俯视结构示意图。如图4A和图4B所示，在本申请实施例中，外围电路600可以包括第一晶体管 601和第二晶体管602，第一晶体管601和第二晶体管602可以并排设置在第二衬底3000的第一侧，并且第一晶体管601与第二衬底3000之间还可以设置有第一型阱603，第二晶体管602与第二衬底3000之间还可以设置有第二型阱604；第一晶体管601可以包括第一源极6011、第一漏极6012、设置在第一源极6011和第一漏极6012之间的第一沟道6013、设置在第一沟道6013一侧的第一栅极6014，第一源极6011和第一漏极6012的材料可以相同，例如，可以均为N型半导体材料或P型半导体材料，第一沟道6013的材料和第一型阱603的材料相同，可以均为P型半导体材料或N型半导体材料，但第一源极6011、第一漏极6012与第一沟道6013、第一型阱603的材料不同；第一沟道6013与第一栅极6014之间还可以设置有第一栅极绝缘层(或叫栅极氧化层，图中未示)；第二晶体管602包括第二源极6021、第二漏极6022、设置在第二源极6021和第二漏极6022之间的第二沟道6023、设置在第二沟道6023一侧的第二栅极6024，第二源极6021和第二漏极6022的材料相同，可以均为P型半导体材料或N型半导体材料，第二沟道6023和第二型阱604的材料相同，可以均为N型半导体材料或P型半导体材料，但第二源极6021、第二漏极6022与第二沟道6023、第二型阱604的材料不同；第二沟道6023与第二栅极6024之间还可以设置有第二栅极绝缘层(或叫栅极氧化层，图中未示)。
在本申请实施例中，如图4A所示，第一晶体管601和第二晶体管602可以并列设置在同一个平面上。
在本申请实施例中，所述第一晶体管和所述第二晶体管可以与不同的金属接触柱连接，金属接触柱的另一端通过所述金属线与所述第一芯片的位线、字线或电容器电连接。
在本申请实施例中，所述第一晶体管和所述第二晶体管可以为选通晶体管。
在本申请实施例中，所述外围电路还可以包括第三晶体管，所述第三晶体管可以与所述第一晶体管和所述第二晶体管设置在同一平面上。
在本申请实施例中，所述金属线的材料可以选自铜和铝中的任意一种或多种，例如，可以为铜；所述金属接触柱的材料可以选自钨和钼中的任意一 种或多种，例如，可以为钨。
在本申请实施例中，所述半导体器件可以为动态随机存取存储器(DRAM)。
本申请实施例还提供一种半导体器件的制造方法。如上所述本申请实施例提供的半导体器件可以通过该制造方法得到。
图5为本申请示例性实施例的半导体器件的制造方法的工艺流程图。如图5所示，所述制造方法可以包括：
S10：在第一衬底的一侧按照第一牺牲层和半导体层的顺序沿垂直于所述第一衬底的方向堆叠形成多个由所述第一牺牲层和所述半导体层组成的复合层；
S20：在多个所述复合层中沿垂直于所述第一衬底的方向刻蚀出沟槽，并对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料形成第一内部支撑层；
S30：去除剩余的第一牺牲层，剩余的半导体层沿平行于所述第一衬底的方向延伸并且依次包括源极区、沟道区和漏极区，所述漏极区包括电容区；
S40：在所述第一衬底上形成第二牺牲层，使所述第二牺牲层覆盖所述半导体层；
S50：去除所述半导体层的沟道区侧壁上的第二牺牲层，在所述半导体层的沟道区的侧壁上依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层和所述栅极组成晶体管；
S60：去除所述半导体层的漏极区的电容区侧壁上的第二牺牲层，在所述半导体层的漏极区的电容区的侧壁上依次形成电容器，得到第一芯片。
在本申请实施例中，所述的半导体器件的制造方法还可以包括：形成多条沿垂直于所述第一衬底的方向延伸的位线；
其中，形成所述位线包括：
步骤S20在多个所述复合层中刻蚀所述沟槽时，在多个所述复合层中沿垂直于所述第一衬底的方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料；
在步骤S60形成所述电容器之后，S70：去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料，形成位线，将所述位线和与该位线相接触的多个半导体层的所述源极区连接，使得该多个半导体层的所述源极区共用一条位线。
在本申请实施例中，步骤S50还可以包括形成多条在平行于所述第一衬底的平面上延伸并且垂直于所述半导体层的延伸方向的字线；
其中，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线。
在本申请实施例中，所述半导体器件的制造方法可以包括：
S10：在第一衬底的一侧按照第一牺牲层和半导体层的顺序沿垂直于所述第一衬底的方向堆叠形成多个由所述第一牺牲层和所述半导体层组成的复合层；
S20：在多个所述复合层中沿垂直于所述第一衬底的方向刻蚀出位线槽和沟槽，并对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料形成第一内部支撑层，以及在所述位线槽中填充隔离材料；
S30：去除剩余的第一牺牲层，剩余的半导体层沿平行于所述第一衬底的方向延伸并且依次包括源极区、沟道区和漏极区，所述漏极区包括电容区；
S40：在所述第一衬底上形成第二牺牲层，使所述第二牺牲层覆盖所述半导体层；
S50：去除所述半导体层的沟道区侧壁上的第二牺牲层，在所述半导体 层的沟道区的侧壁上依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层和所述栅极组成晶体管；以及，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线；
S60：去除所述半导体层的漏极区的电容区侧壁上的第二牺牲层，在所述半导体层的漏极区的电容区的侧壁上依次形成环绕所述电容区的第一电极板、介电质层和第二电极板，所述第一电极板、所述介电质层和所述第二电极板组成电容器；
S70：去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料，形成位线，将所述位线和与该位线相接触的多个半导体层的所述源极区连接，使得该多个半导体层的所述源极区共用一条位线，得到第一芯片。
在本申请实施例中，步骤S20可以包括：
在所述多个复合层中沿垂直于所述第一衬底的方向刻蚀出位线槽和沟槽，并对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层，以及在所述位线槽中填充隔离材料；或者，
在所述多个复合层中沿垂直于所述第一衬底的方向刻蚀出位线槽和沟槽，在所述沟槽中填充支撑材料，形成设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸的第一内部支撑层；对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合壁的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导 体层的漏极区的电容区之间的第一内部支撑层，以及在所述位线槽中填充隔离材料。
在本申请实施例中，步骤S20可以包括：
S21：在所述多个复合层中沿垂直于所述第一衬底的方向刻蚀出存储单元隔离槽、位线槽和沟槽；
S22：在所述沟槽中填充支撑材料，形成设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸的第一内部支撑层；对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层；
任选地，S23：对所述存储单元隔离槽进行侧边刻蚀，使得在每个所述复合壁的第一牺牲层中形成第二内部支撑槽，这里的第二内部支撑槽位于所述存储单元隔离槽两侧，在所述第二内部支撑槽中填充支撑材料，所述第二内部支撑槽中的支撑材料形成第二内部支撑层；
任选地，S24：对所述位线槽进行侧边刻蚀，在每个所述复合壁的第一牺牲层中形成第二内部支撑槽，这里的第二内部支撑槽位于所述位线槽两侧，在所述第二内部支撑槽中填充支撑材料，所述第二内部支撑槽中的支撑材料形成第二内部支撑层；
S25：在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中填充隔离材料。
例如，在本申请示例性实施例中，
i)步骤S20可以包括：
S21：在所述多个复合层中沿垂直于所述第一衬底的方向刻蚀出存储单元隔离槽、位线槽和沟槽；
S22：在所述沟槽中填充支撑材料，形成设置在沿所述字线的延伸方向 上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸的第一内部支撑层；对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层；
S23：对所述存储单元隔离槽进行侧边刻蚀，使得在每个所述复合壁的第一牺牲层中形成第二内部支撑槽，这里的第二内部支撑槽位于所述存储单元隔离槽两侧，在所述第二内部支撑槽中填充支撑材料，所述第二内部支撑槽中的支撑材料形成第二内部支撑层；
S25：在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中填充隔离材料。
或者，ii)步骤S20可以包括：
S21：在所述多个复合层中沿垂直于所述第一衬底的方向刻蚀出存储单元隔离槽、位线槽和沟槽；
S22：在所述沟槽中填充支撑材料，形成设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸的第一内部支撑层；对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层；
S24：对所述位线槽进行侧边刻蚀，在每个所述复合壁的第一牺牲层中形成第二内部支撑槽，这里的第二内部支撑槽位于所述位线槽两侧，在所述第二内部支撑槽中填充支撑材料，所述第二内部支撑槽中的支撑材料形成第二内部支撑层；
S25：在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中 填充隔离材料。
或者，iii)步骤S20可以包括：
S21：在所述多个复合层中沿垂直于所述第一衬底的方向刻蚀出存储单元隔离槽、位线槽和沟槽；
S22：在所述沟槽中填充支撑材料，形成设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸的第一内部支撑层；对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层；
S23：对所述存储单元隔离槽进行侧边刻蚀，使得在每个所述复合壁的第一牺牲层中形成第二内部支撑槽，这里的第二内部支撑槽位于所述存储单元隔离槽两侧，在所述第二内部支撑槽中填充支撑材料，所述第二内部支撑槽中的支撑材料形成第二内部支撑层；
S24：对所述位线槽进行侧边刻蚀，在每个所述复合壁的第一牺牲层中形成第二内部支撑槽，这里的第二内部支撑槽位于所述位线槽两侧，在所述第二内部支撑槽中填充支撑材料，所述第二内部支撑槽中的支撑材料形成第二内部支撑层；
S25：在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中填充隔离材料。
在本申请实施例中，步骤S30可以包括：去除剩余的第一牺牲层，剩余的半导体层沿平行于所述第一衬底的方向延伸并且依次包括源极区、沟道区和漏极区，所述漏极区包括电容区。
在本申请实施例中，步骤S50可以包括：
S51：去除所述半导体层的沟道区四周的第二牺牲层，在所述半导体层的沟道区四周依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层 和所述栅极组成晶体管；以及，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线；
任选地，S52：将沿垂直于所述第一衬底的方向排列的位于不同层的多条字线设置为不同的长度，使得沿垂直于所述第一衬底的方向排列的位于不同层的多条字线呈现出阶梯状；
任选地，S53：在每个存储单元列中相邻的两个存储单元的晶体管的栅极之间设置层间隔离层，从而将每个存储单元列中相邻的两个存储单元的晶体管的栅极隔离开。
例如，在本申请示例性实施例中，
i)步骤S50可以包括：
S51：去除所述半导体层的沟道区四周的第二牺牲层，在所述半导体层的沟道区四周依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层和所述栅极组成晶体管；以及，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线；
S52：将沿垂直于所述第一衬底的方向排列的位于不同层的多条字线设置为不同的长度，使得沿垂直于所述第一衬底的方向排列的位于不同层的多条字线呈现出阶梯状；
或者，ii)步骤S50可以包括：
S51：去除所述半导体层的沟道区四周的第二牺牲层，在所述半导体层的沟道区四周依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层和所述栅极组成晶体管；以及，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的 栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线；
S53：在每个存储单元列中相邻的两个存储单元的晶体管的栅极之间设置层间隔离层，从而将每个存储单元列中相邻的两个存储单元的晶体管的栅极隔离开；
或者，iii)步骤S50可以包括：
S51：去除所述半导体层的沟道区四周的第二牺牲层，在所述半导体层的沟道区四周依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层和所述栅极组成晶体管；以及，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线；
S52：将沿垂直于所述第一衬底的方向排列的位于不同层的多条字线设置为不同的长度，使得沿垂直于所述第一衬底的方向排列的位于不同层的多条字线呈现出阶梯状；
S53：在每个存储单元列中相邻的两个存储单元的晶体管的栅极之间设置层间隔离层，从而将每个存储单元列中相邻的两个存储单元的晶体管的栅极隔离开。
在本申请实施例中，所述制造方法还可以包括：
S80：在第二衬底的一侧依次设置外围电路、带有金属接触柱的金属接触层、和带有金属线的金属互连层，将所述金属线的一端通过所述金属接触柱与所述外围电路电连接，得到第二芯片；
S90：将所述第一芯片和所述第二芯片层叠结合在一起，并将所述第二芯片的电路与所述第一芯片的电路进行电连接。
在本申请实施例中，步骤S80可以包括：
S81：在所述第二衬底的一侧依次设置外围电路、带有金属接触柱的金 属接触层、带有金属线的金属互连层，所述外围电路包括第一晶体管和第二晶体管，
S82：将所述第一晶体管和所述第二晶体管分别与所述金属接触柱连接。
在本申请实施例中，步骤S90可以包括：采用X-Tracking技术将所述第一芯片的第一衬底与所述第二芯片的金属互连层层叠结合在一起，并将所述金属互连层的金属线与所述第一芯片的位线、字线或电容器电连接。
图6A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图6B为图6A所示的中间品的俯视结构示意图；图7A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图7B为图7A所示的中间品的俯视结构示意图；图8A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图8B为图8A所示的中间品的俯视结构示意图；图9A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图9B为图9A所示的中间品的俯视结构示意图；图10A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图10B为图10A所示的中间品的俯视结构示意图；图11A为本申请示例性实施例的半导体器件的制造方法的中间步骤得到的中间品的主视剖面结构示意图；图11B为图11A所示的中间品的俯视结构示意图。如图6A至图11B所示，在示例性实施例中，所述半导体器件的制造方法可以包括：
S10：在第一衬底100一侧按照第一牺牲层901和半导体层11的顺序沿垂直于第一衬底100的方向堆叠形成多个由第一牺牲层901和半导体层11组成的复合层，得到如图6A和图6B所示的中间品；
S21：在多个复合层中沿垂直于第一衬底100的方向刻蚀出存储单元隔离槽3’、位线槽300’和沟槽4，得到如图7A和图7B所示的中间品；
S22：在沟槽4中填充支撑材料，形成沿垂直于第一衬底100的方向延伸的第一内部支撑层501(如图8B所示)；对沟槽4进行侧边刻蚀，形成多个垂直于第一衬底100的间隔槽6并且在每个复合层的第一牺牲层901中形成第一内部支撑槽501’，间隔槽6将多个复合层间隔为多个垂直于第一衬底 100的复合壁，第一内部支撑槽501’将第一牺牲层901间隔为网格结构，在第一内部支撑槽501’中填充支撑材料，形成设置在沿垂直于第一衬底100的方向上相邻的两个半导体层11之间的第一内部支撑层501(如图8A所示)；
S23：对存储单元隔离槽3’进行侧边刻蚀，使得在每个复合壁的第一牺牲层901中形成第二内部支撑槽502’，这里的第二内部支撑槽502’位于存储单元隔离槽3’两侧，在第二内部支撑槽502’中填充支撑材料，第二内部支撑槽502’中的支撑材料形成第二内部支撑层502；
S24：对位线槽300’进行侧边刻蚀，在每个复合壁的第一牺牲层901中形成第二内部支撑槽502’，这里的第二内部支撑槽502’位于位线槽300’两侧，在第二内部支撑槽502’中填充支撑材料，第二内部支撑槽502’中的支撑材料形成第二内部支撑层502；
S25：在存储单元隔离槽3’中填充存储单元隔离柱3和在位线槽300’中填充隔离材料5，得到如图8A和图8B所示的中间品；
S30：去除剩余的第一牺牲层901，剩余的半导体层11沿平行于第一衬底100的方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在垂直于第一衬底1000方向上的侧壁依次包括源极区111、沟道区112和漏极区113，漏极区113包括电容区，得到如图9A和图9B所示的中间品；
S40：在第一衬底100上形成第二牺牲层902，使第二牺牲层902覆盖步骤S30得到的中间品的表面(覆盖半导体层11)，得到如图10A和图10B所示的中间品；
S51：去除半导体层11的沟道区112侧壁上的第二牺牲层902，在半导体层11的沟道区112侧壁上依次形成环绕沟道区112的栅极绝缘层和栅极12，半导体层11和栅极12组成晶体管10；以及，在平行于第一衬底100的平面上并且沿垂直于半导体层11的延伸方向上设置有一个半导体层11，使该一个半导体层11上的栅极12作为字线400；或者，在平行于第一衬底100的平面上并且沿垂直于半导体层11的延伸方向上设置有多个半导体层11，使该多个半导体层11上的栅极12连接在一起形成字线400；
S52：将沿垂直于第一衬底100的方向排列的位于不同层的多条字线400设置为不同的长度，使得沿垂直于第一衬底100的方向排列的位于不同层的 多条字线400呈现出阶梯状；
S53：在每个存储单元列中相邻的两个存储单元的晶体管10的栅极12之间设置层间隔离层2，从而将每个存储单元列中相邻的两个存储单元的晶体管10的栅极12隔离开，得到如图11A和图11B所示的中间品；
S60：去除半导体层11的漏极区113的电容区侧壁上的第二牺牲层902，在半导体层11的漏极区113的电容区侧壁上依次形成环绕电容区的第一电极板21、介电质层23和第二电极板22，第一电极板21、介电质层23和第二电极板22组成电容器20；
S70：去除位线槽300’中的隔离材料5，在位线槽300’中填充位线材料，形成位线，将位线和与该位线相接触的多个半导体层11的源极区111连接，使得该多个半导体层11的源极区111共用一条位线，得到第一芯片1000，得到如图1A和图1B所示的中间品；
S81：在第二衬底的一侧依次设置外围电路、带有金属接触柱的金属接触层、带有金属线的金属互连层，外围电路包括第一晶体管10和第二晶体管10，
S82：将第一晶体管10和第二晶体管10分别与金属接触柱连接；
S90：采用X-Tracking技术将第一芯片1000的第一衬底100与第二芯片的金属互连层层叠结合在一起，并将金属互连层的金属线与第一芯片1000的位线、字线400或电容器电连接，得到如图2A和图2B所示的中间品。
在本申请实施例中，形成第一芯片的步骤S10至S70与形成第二芯片的步骤S80可以同时进行；或者，先进行步骤S10至S60，后进行步骤S80；或者，先进行步骤S80，后进行步骤S10至S60。
在本申请实施例中，所述第一牺牲层的材料可以为与所述半导体层的材料之间的刻蚀选择比较大的材料，例如，所述第一牺牲层的材料与所述半导体层的材料之间的刻蚀选择比可以≥50:1，再例如，所述半导体层的材料可以为单晶硅，所述第一牺牲层的材料可以选自SiGe等具有相似性质的其他材料中的任意一种或多种。所述第一牺牲层的厚度可以为30nm至50nm，例如，可以为30nm、35nm、40nm、45nm、50nm。
在本申请实施例中，所述第二牺牲层的材料可以为与所述半导体层的材料之间的刻蚀选择比较大的材料，例如，所述第二牺牲层的材料与所述半导体层的材料之间的刻蚀选择比可以≥50:1。再例如，所述半导体层的材料可以为单晶硅，所述第二牺牲层的材料可以为SiO 2等具有相似性质的其他材料中的任意一种或多种；SiO 2与单晶硅的刻蚀选择比较高，而且SiO 2的刻蚀工艺成熟且所需的刻蚀时间较短。
在本申请实施例中，步骤S10中可以通过外延设备在所述第一衬底的第一侧生长出由第一牺牲层和半导体层组成的超晶格(super lattice)薄膜堆叠层，得到多个由第一牺牲层和半导体层组成的复合外延层。
在本申请实施例中，步骤S21中可以利用同一层图案光罩(Photo mask)通过光照曝光进行图案化刻蚀，形成存储单元隔离槽、位线槽和沟槽。
在本申请实施例中，步骤S22至S24中，可以通过湿法刻蚀对所述沟槽、所述存储单元隔离槽或所述位线槽进行侧边刻蚀。
在本申请实施例中，步骤S22至S24中，可以通过ALD工艺在所述第一内部支撑层槽、所述第二内部支撑槽和所述沟槽中填充支撑材料，例如，可以通过ALD工艺在所述第一内部支撑层槽、所述第二内部支撑槽和所述沟槽中填充SiN。
在本申请实施例中，步骤S25中可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽中填充存储单元隔离柱和在所述位线槽中填充隔离材料，例如，可以通过SOD、HDP或HARP工艺在所述存储单元隔离槽和所述位线槽中形成氧化硅薄膜。
在本申请实施例中，步骤S30中可以通过刻蚀法、选择超高第一牺牲层/半导体层刻蚀比将第一牺牲层刻蚀掉而保留半导体层，所述刻蚀法可以为干法刻蚀或湿法刻蚀。
在本申请实施例中，步骤S40中可以通过SOD、HDP或HARP工艺形成第二牺牲层，例如，可以通过SOD、HDP或HARP工艺形成SOD氧化硅薄膜、HDP氧化硅薄膜和HARP氧化硅薄膜中的任意一种或多种，作为第二牺牲层。
在本申请实施例中，步骤S50中可以通过刻蚀法、选择超高第二牺牲层/半导体层刻蚀比将第二牺牲层刻蚀掉而保留半导体层，所述刻蚀法可以为干法刻蚀或湿法刻蚀。
在本申请实施例中，步骤S52中可以通过修整刻蚀(trim etch)得到阶梯状字线(staircase WL)。
在本申请实施例中，步骤S53中可以通过ALD或化学气相沉积(Chemical Vapor Deposition,CVD)工艺设置层间隔离层，例如，可以通过ALD或CVD工艺填充SiO 2，形成层间隔离层。
在本申请实施例中，步骤S80中可以通过传统的CMOS工艺形成所述外围电路，然后在所述外围电路上制作金属接触层和金属互连层。所述金属接触层可以由金属接触柱和绝缘介质形成，可以先设置整层的绝缘介质，然后在绝缘介质中开设通孔并填充金属形成所述金属接触柱。所述金属互连层可以由金属线和绝缘介质形成，可以先设置整层的绝缘介质，然后在绝缘介质中开设通孔并填充金属形成所述金属线。
在本申请实施例中，步骤S90中可以采用X-Tracking技术实现第一芯片和第二芯片的结合和精确电连接，例如，可以包括将第一芯片和第二芯片结合在一起，根据需要选择将金属线与位线、字线或电容器电连接，例如，若想要金属线与位线电连接，则将金属线与位线对齐，并在第一衬底中开设连接金属线与位线的通孔以及在该通孔中填充导电金属，实现金属线与位线的精确电连接。
本申请实施例还提供一种电子设备，包括如上本申请实施例提供的所述半导体器件。
在本申请实施例中，所述电子设备可以包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种半导体器件，包括第一芯片，所述第一芯片包括：
    第一衬底；
    设置在所述第一衬底上的多个存储单元列，每个所述存储单元列均垂直于所述第一衬底并且由堆叠设置在所述第一衬底一侧的多个存储单元形成；
    每个所述存储单元均包括晶体管和电容器，所述晶体管包括半导体层和栅极，所述半导体层沿平行于所述第一衬底的方向延伸为条状结构，所述条状结构具有侧壁和两端，并且在平行于所述第一衬底的方向上的侧壁依次包括源极区、沟道区和漏极区，所述漏极区包括电容区；所述栅极环绕在所述沟道区的侧壁，并且所述栅极与所述沟道区之间设置有栅极绝缘层；
    所述电容器设置在所述漏极区的电容区的侧壁上；
    第一内部支撑层，所述第一内部支撑层设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间，所述第一内部支撑层配置为对所述电容器和相邻的两个半导体层提供支撑，所述电容器被所述第一内部支撑层间隔为网格式电容器。
  2. 根据权利要求1所述的半导体器件，其中，所述第一芯片还包括：多条字线，每条所述字线均在平行于所述第一衬底的平面上延伸并且垂直于所述半导体层的延伸方向，其中，在所述字线的延伸方向上设置有一个存储单元列，每条所述字线由该一个存储单元列的一个存储单元的晶体管的栅极形成；或者，在所述字线的延伸方向上设置有多个存储单元列，每条所述字线由该多个存储单元列的沿所述字线的延伸方向排列的多个存储单元的晶体管的栅极连接在一起形成。
  3. 根据权利要求2所述的半导体器件，其中，所述第一内部支撑层还设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸。
  4. 根据权利要求1至3中任一项所述的半导体器件，其中，所述第一芯片还包括：多条位线，每条所述位线均沿垂直于所述第一衬底的方向延伸，在与所述半导体层的延伸方向平行的方向上，相邻的两个存储单元列的多个 存储单元的晶体管的源极区均与一条共用的位线连接。
  5. 根据权利要求1至4中任一项所述的半导体器件，其中，所述电容器环绕在所述漏极区的电容区的侧壁上。
  6. 根据权利要求1至4中任一项所述的半导体器件，其中，所述电容器包括第一电极板、第二电极板以及设置在所述第一电极板和所述第二电极板之间的介电质层，所述第一电极板、所述介电质层和所述第二电极板依次环绕在所述漏极区的电容区的侧壁上。
  7. 根据权利要求1至6中任一项所述的半导体器件，还包括第二芯片，所述第二芯片和所述第一芯片层叠结合在一起并且所述第二芯片和所述存储单元列分别位于所述第一衬底的两侧，所述第二芯片的电路与所述第一芯片的电路电连接；
    所述第二芯片包括依次设置在第二衬底上的外围电路、金属接触层和金属互连层，所述金属接触层设置在所述外围电路远离所述第二衬底的一侧，所述金属互连层设置在所述金属接触层远离所述第二衬底的一侧并且位于所述第一衬底远离所述存储单元列的一侧，所述金属接触层中设置有金属接触柱，所述金属互连层中设置有金属线，所述金属线的一端与所述第一芯片的位线、字线或电容器电连接，所述金属线的另一端通过所述金属接触柱与所述外围电路电连接。
  8. 根据权利要求1至6中任一项所述的半导体器件，其中，沿垂直于所述第一衬底的方向间隔排列的位于不同层的多条字线呈阶梯状。
  9. 根据权利要求2或3所述的半导体器件，其中，所述半导体层的材料选自第IVA族元素形成的半导体材料中的任意一种或多种，所述字线的材料选自第IVA族元素形成的导体材料中的任意一种或多种。
  10. 根据权利要求9所述的半导体器件，其中，所述半导体层的材料为单晶硅；所述字线的材料选自多晶硅和多晶硅锗中的任意一种或多种。
  11. 根据权利要求1至10中任一项所述的半导体器件，其中，所述存储单元列还包括层间隔离层，所述层间隔离层设置在所述存储单元列中相邻的两个存储单元的晶体管的栅极之间，所述层间隔离层配置为将相邻的两个存 储单元的晶体管的栅极隔离开。
  12. 根据权利要求1至10中任一项所述的半导体器件，还包括一个或多个沿垂直于所述第一衬底的方向延伸的存储单元隔离柱，在所述半导体层的延伸方向上每间隔两个存储单元列设置有一个所述存储单元隔离柱。
  13. 根据权利要求1至12中任一项所述的半导体器件，还包括第二内部支撑层，所述第二内部支撑层设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层之间并且位于非电容区，所述第二内部支撑层配置为对所述半导体层提供支撑。
  14. 根据权利要求6所述的半导体器件，其中，所述第一电极板为内电极板，所述第二电极板为外电极板；所述漏极区与所述第一电极板连接。
  15. 一种半导体器件的制造方法，包括：
    在第一衬底的一侧按照第一牺牲层和半导体层的顺序沿垂直于所述第一衬底的方向堆叠形成多个由所述第一牺牲层和所述半导体层组成的复合层；
    在多个所述复合层中沿垂直于所述第一衬底的方向刻蚀出沟槽，并对所述沟槽进行侧边刻蚀，形成多个垂直于所述第一衬底的间隔槽并且在每个所述复合层的第一牺牲层中形成第一内部支撑槽，所述间隔槽将多个所述复合层间隔为多个垂直于所述第一衬底的复合壁，所述第一内部支撑槽将所述第一牺牲层间隔为网格结构，在所述第一内部支撑槽中填充支撑材料形成第一内部支撑层；
    去除剩余的第一牺牲层，剩余的半导体层沿平行于所述第一衬底的方向延伸并且依次包括源极区、沟道区和漏极区，所述漏极区包括电容区；
    在所述第一衬底上形成第二牺牲层，使所述第二牺牲层覆盖所述半导体层；
    去除所述半导体层的沟道区侧壁上的第二牺牲层，在所述半导体层的沟道区的侧壁上依次形成环绕所述沟道区的栅极绝缘层和栅极，所述半导体层和所述栅极组成晶体管；
    去除所述半导体层的漏极区的电容区侧壁上的第二牺牲层，在所述半导体层的漏极区的电容区的侧壁上依次形成电容器，得到第一芯片。
  16. 根据权利要求15所述的半导体器件的制造方法，还包括：形成多条在平行于所述第一衬底的平面上延伸并且垂直于所述半导体层的延伸方向的字线；
    其中，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有一个半导体层，使该一个半导体层上的栅极作为字线；或者，在平行于所述第一衬底的平面上并且沿垂直于所述半导体层的延伸方向上设置有多个半导体层，使该多个半导体层上的栅极连接在一起形成字线。
  17. 根据权利要求16所述的半导体器件的制造方法，还包括：形成多条沿垂直于所述第一衬底的方向延伸的位线；
    其中，形成所述位线包括：
    在多个所述复合层中刻蚀所述沟槽时，在多个所述复合层中沿垂直于所述第一衬底的方向刻蚀出位线槽，以及在所述位线槽中填充隔离材料；
    在形成所述电容器之后，去除所述位线槽中的隔离材料，在所述位线槽中填充位线材料，形成位线，将所述位线和与该位线相接触的多个半导体层的所述源极区连接，使得该多个半导体层的所述源极区共用一条位线。
  18. 根据权利要求17所述的半导体器件的制造方法，还包括：
    在第二衬底的一侧依次设置外围电路、带有金属接触柱的金属接触层、和带有金属线的金属互连层，将所述金属线的一端通过所述金属接触柱与所述外围电路电连接，得到第二芯片；
    将所述第一芯片和所述第二芯片层叠结合在一起，并将所述第二芯片的电路与所述第一芯片的电路进行电连接。
  19. 根据权利要求16至18中任一项所述的半导体器件的制造方法，其中，对所述沟槽进行侧边刻蚀，在每个所述复合层的第一牺牲层中形成第一内部支撑槽，在所述第一内部支撑槽中填充支撑材料形成第一内部支撑层，包括：
    对所述沟槽进行侧边刻蚀，在每个所述复合层的第一牺牲层中形成第一内部支撑槽，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内 部支撑层；或者，
    在所述沟槽中填充支撑材料，形成设置在沿所述字线的延伸方向上相邻的两个半导体层的漏极区的电容区之间并且沿垂直于所述第一衬底的方向延伸的第一内部支撑层；对所述沟槽进行侧边刻蚀，在每个所述复合层的第一牺牲层中形成第一内部支撑槽，在所述第一内部支撑槽中填充支撑材料，形成设置在沿垂直于所述第一衬底的方向上相邻的两个半导体层的漏极区的电容区之间的第一内部支撑层。
  20. 根据权利要求15至19中任一项所述的半导体器件的制造方法，其中，所述在所述半导体层的漏极区的电容区的侧壁上依次形成电容器，包括：在所述半导体层的漏极区的电容区的侧壁上依次形成环绕所述电容区的侧壁的第一电极板、介电质层和第二电极板，所述第一电极板、所述介电质层和所述第二电极板构成所述电容器。
  21. 一种电子设备，包括根据权利要求1至14中任一项所述的半导体器件。
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